CN111193959B - Analog video signal processing method and analog video processing apparatus - Google Patents
Analog video signal processing method and analog video processing apparatus Download PDFInfo
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- CN111193959B CN111193959B CN201811358746.4A CN201811358746A CN111193959B CN 111193959 B CN111193959 B CN 111193959B CN 201811358746 A CN201811358746 A CN 201811358746A CN 111193959 B CN111193959 B CN 111193959B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream, rendering scenes according to MPEG-4 scene graphs
- H04N21/44008—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream, rendering scenes according to MPEG-4 scene graphs involving operations for analysing video streams, e.g. detecting features or characteristics in the video stream
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/4302—Content synchronisation processes, e.g. decoder synchronisation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/431—Generation of visual interfaces for content selection or interaction; Content or additional data rendering
- H04N21/4312—Generation of visual interfaces for content selection or interaction; Content or additional data rendering involving specific graphical features, e.g. screen layout, special fonts or colors, blinking icons, highlights or animations
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/431—Generation of visual interfaces for content selection or interaction; Content or additional data rendering
- H04N21/4318—Generation of visual interfaces for content selection or interaction; Content or additional data rendering by altering the content in the rendering process, e.g. blanking, blurring or masking an image region
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Abstract
The embodiment of the invention discloses an analog video signal processing method and an analog video processing device, wherein the method comprises the following steps: receiving an analog video signal, and extracting characteristics to obtain the characteristic information of the analog video signal; carrying out synchronous signal separation on the analog video signal to obtain a synchronous signal and analog image data; performing time sequence parameter matching on the characteristic information of the analog video signal to obtain a target time sequence parameter; generating a first configuration parameter and a third configuration parameter; sequentially generating a plurality of second configuration parameters; generating a sampling clock based on the synchronization signal and the first configuration parameter; carrying out phase adjustment operation on the sampling clocks in sequence to obtain a plurality of adjusted sampling clocks; obtaining a digital video signal based on the third configuration parameter, the synchronization signal and the digital image data; and obtaining and setting a target second configuration parameter and a target third configuration parameter based on the line edge characteristic information. The embodiment of the invention can quickly and efficiently realize the optimization and adjustment of the analog/digital video signal conversion.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to an analog video signal processing method and an analog video processing apparatus.
Background
In the field of video processing, input sources can be divided into analog signals and digital video. VGA video signals are still widely used as analog signals because they have the advantages of not synthesizing video components and transmitting video images of more than 1080P. Before the VGA signals are used as video input source for video processing, the analog-to-digital conversion work needs to be completed first. Because the VGA signal transmission does not include a clock signal, the clock signal needs to be recovered at the signal receiving end to sample and quantize the analog video signal, and if the sampling clock frequency is not matched with the image data in the VGA analog/digital conversion process, the converted image quality is abnormal, so that the phase adjustment of the sampling clock frequency is needed.
Disclosure of Invention
Embodiments of the present invention provide an analog video signal processing method and an analog video processing apparatus, which can quickly and efficiently implement the optimization adjustment of the analog/digital video signal conversion and reduce the hardware requirement.
Specifically, an analog video signal processing method provided by an embodiment of the present invention includes the steps of:
receiving an analog video signal and extracting the characteristics of the analog video signal to obtain the characteristic information of the analog video signal; carrying out synchronous signal separation on the analog video signal to obtain a synchronous signal and analog image data; performing time sequence parameter matching on the analog video signal characteristic information to obtain a target time sequence parameter matched with the analog video signal characteristic information; generating a first configuration parameter and a third configuration parameter according to the target time sequence parameter; sequentially generating a plurality of second configuration parameters; generating a sampling clock based on the synchronization signal and the first configuration parameter; carrying out phase adjustment operation on the sampling clock based on the plurality of second configuration parameters in sequence to obtain a plurality of adjusted sampling clocks; performing analog-to-digital conversion on the analog image data based on the plurality of adjusted sampling clocks in sequence to obtain digital image data; obtaining a digital video signal based on the third configuration parameter, the synchronization signal and the digital image data; detecting the digital video signal to obtain line edge characteristic information; and setting a target second configuration parameter and a target third configuration parameter based on the line edge feature information.
In one embodiment of the present invention, the analog video signal processing method further includes: carrying out phase adjustment operation on the sampling clock based on the target second configuration parameter to obtain a target sampling clock; performing analog-to-digital conversion on the analog image data based on the target sampling clock to obtain second digital image data; and obtaining a digital video signal based on the target third configuration parameter, the synchronization signal and the second digital image data.
In an embodiment of the present invention, the step of detecting the digital video signal to obtain the line edge feature information includes: acquiring line blanking area pixel data outside the line effective display data enable signal edge of each of a plurality of pixel lines in the process of carrying out analog-to-digital conversion on the analog image data based on each of the plurality of adjusted sampling clocks; comparing the pixel data of the line blanking area of each pixel line in the plurality of pixel lines with a preset threshold value, and counting the continuous point pixels exceeding the threshold value to obtain the number of line overrun pixels of each pixel line; obtaining an overrun pixel data distribution based on the line overrun pixel number of the plurality of pixel lines; repeating the steps, and sequentially carrying out analog-to-digital conversion on the analog image data based on the plurality of adjusted sampling clocks to obtain a plurality of sets of overrun pixel data distribution; and distributing a plurality of sets of the overrun pixel data corresponding to the adjusted sampling clocks respectively as the line edge characteristic information.
In an embodiment of the present invention, the setting of the target second configuration parameter and the target third configuration parameter based on the line edge feature information includes: extracting the multiple sets of over-limit pixel data distribution from the line edge characteristic information; calculating the respective dispersion degree of the distribution of the multiple sets of the overrun pixel data; and setting the target second configuration parameter according to the second configuration parameter corresponding to the ultralimit pixel data distribution with the minimum discrete degree, and setting the target third configuration parameter according to the ultralimit pixel data distribution with the minimum discrete degree.
In one embodiment of the invention, the line blanking region pixel data outside the edge of the line effective display data enable signal of each pixel line comprises left blanking region pixel data and right blanking region pixel data in the region where the line effective display data is located.
On the other hand, an analog video processing apparatus provided in an embodiment of the present invention includes: the device comprises an analog video decoder, a microcontroller and a programmable logic device, wherein the microcontroller is connected with the analog video decoder; the programmable logic device is respectively connected with the microcontroller and the analog video decoder;
wherein the analog video decoder is to: receiving an analog video signal, performing feature extraction on the analog video signal to obtain analog video signal feature information and outputting the analog video signal feature information, performing synchronous signal separation on the analog video signal to obtain a synchronous signal and analog image data, receiving a first configuration parameter and a third configuration parameter, sequentially receiving a plurality of second configuration parameters, generating a sampling clock based on the synchronous signal and the first configuration parameter, sequentially performing phase adjustment operation on the sampling clock based on the plurality of second configuration parameters to obtain a plurality of adjusted sampling clocks, sequentially performing analog-to-digital conversion on the analog image data based on the plurality of adjusted sampling clocks to obtain digital image data, and obtaining and outputting a digital video signal based on the third configuration parameter, the synchronous signal and the digital image data;
the programmable logic device is used for detecting the digital video signal to obtain line edge characteristic information;
the microcontroller is configured to: and performing time sequence parameter matching on the analog video signal characteristic information to obtain a target time sequence parameter matched with the analog video signal characteristic information, generating and outputting the first configuration parameter and the third configuration parameter according to the target time sequence parameter, sequentially outputting the plurality of second configuration parameters, and setting and outputting the target second configuration parameter and the target third configuration parameter based on the line edge characteristic information.
In one embodiment of the present invention, the analog video decoder is further configured to: carrying out phase adjustment operation on the sampling clock based on the target second configuration parameter to obtain a target sampling clock; performing analog-to-digital conversion on the analog image data based on the target sampling clock to obtain second digital image data; and obtaining a digital video signal based on the target third configuration parameter, the synchronization signal and the second digital image data.
In an embodiment of the present invention, the step of detecting the digital video signal by the programmable logic device to obtain the line edge feature information specifically includes: acquiring line blanking area pixel data outside the line effective display data enable signal edge of each of a plurality of pixel lines in the process of carrying out analog-to-digital conversion on the analog image data based on each of the plurality of adjusted sampling clocks; comparing the pixel data of the line blanking area of each pixel line in the plurality of pixel lines with a preset threshold value, and counting the continuous point pixels exceeding the threshold value to obtain the number of line overrun pixels of each pixel line; obtaining an overrun pixel data distribution based on the line overrun pixel number of the plurality of pixel lines; repeating the steps, and sequentially carrying out analog-to-digital conversion on the analog image data based on the plurality of adjusted sampling clocks to obtain a plurality of sets of overrun pixel data distribution; and distributing a plurality of sets of the overrun pixel data corresponding to the adjusted sampling clocks respectively as the line edge characteristic information.
In an embodiment of the present invention, the setting and outputting the target second configuration parameter and the target third configuration parameter based on the line edge feature information by the microcontroller specifically includes: extracting the multiple sets of over-limit pixel data distribution from the line edge characteristic information; calculating the respective dispersion degree of the distribution of the multiple sets of the overrun pixel data; and setting the target second configuration parameter according to the second configuration parameter corresponding to the ultralimit pixel data distribution with the minimum discrete degree, and setting the target third configuration parameter according to the ultralimit pixel data distribution with the minimum discrete degree.
In another aspect, an analog video processing apparatus provided in an embodiment of the present invention includes: a characteristic extraction module, a synchronous signal separation module, a microcontroller, a phase-locked loop, a data conversion module, a phase adjustment module, a time sequence reconstruction module and a line edge detection module, wherein,
the characteristic extraction module is used for receiving an analog video signal and extracting the characteristics of the analog video signal to obtain the characteristic information of the analog video signal; the synchronous signal separation module is used for carrying out synchronous signal separation on the analog video signal to obtain a synchronous signal and analog image data; the microcontroller is connected with the characteristic extraction module and is used for carrying out time sequence parameter matching on the analog video signal characteristic information to obtain a target time sequence parameter matched with the analog video signal characteristic information, generating and outputting a first configuration parameter and a third configuration parameter according to the target time sequence parameter, and sequentially outputting a plurality of second configuration parameters; the phase-locked loop is respectively connected with the microcontroller and the synchronous signal separation module and is used for generating a sampling clock based on the synchronous signal and the first configuration parameter; the phase adjusting module is respectively connected with the phase-locked loop and the microcontroller and is used for sequentially carrying out phase adjusting operation on the sampling clock based on the plurality of second configuration parameters to obtain a plurality of adjusted sampling clocks; the data conversion module is connected with the phase adjustment module and the synchronous signal separation module and is used for carrying out analog-to-digital conversion on the analog image data based on the adjusted sampling clocks to obtain digital image data; the time sequence reconstruction module is respectively connected with the data conversion module, the synchronous signal separation module and the microcontroller and is used for obtaining a digital video signal based on the third configuration parameter, the synchronous signal and the first digital image data; the line edge detection module is respectively connected with the time sequence reconstruction module and the microcontroller and is used for detecting the digital video signal and obtaining line edge characteristic information; wherein the microcontroller is further configured to set a target second configuration parameter and a target third configuration parameter based on the row edge feature information.
In another aspect, an embodiment of the present invention provides a non-volatile storage medium for storing a computer-readable program for a processing device, such as a computer, to execute the above analog video signal processing method.
The above technical solution may have one or more of the following advantages: in the process of converting the analog video signal into the digital video signal, the phase parameter of the sampling clock is continuously adjusted, and the multi-line edge characteristic information of the adjusted digital video signal is detected in real time to obtain blanking region pixel data positioned at the edge of an image display region, and then the phase parameter when the blanking region pixel data is optimal is selected to process the input analog video signal, so that the digital video signal with the best display effect is finally obtained.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a flow chart of an analog video signal processing method according to a first embodiment of the present invention;
FIG. 2 is a diagram illustrating edge features in a display screen according to a first embodiment of the present invention;
FIG. 3 is a schematic diagram of an edge characteristic of the target sampling clock of FIG. 2;
FIG. 4 is a schematic diagram of edge characteristics of the target sample clock of FIG. 2 when the target sample clock is normal;
FIG. 5 is a flowchart illustrating a portion of steps of an analog video signal processing method according to a second embodiment of the present invention;
FIG. 6 is a diagram illustrating a second embodiment of obtaining line edge feature information;
FIG. 7 is a schematic structural diagram of an analog video processing apparatus according to a third embodiment of the present invention;
fig. 8 is a schematic structural diagram of an analog video processing apparatus according to a fourth embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
First embodiment
Fig. 1 is a diagram illustrating an analog video signal processing method according to a first embodiment of the present invention, including the steps of:
s00: receiving an analog video signal and extracting the characteristics of the analog video signal to obtain the characteristic information of the analog video signal;
s01: carrying out synchronous signal separation on the analog video signal to obtain a synchronous signal and analog image data;
s02: performing time sequence parameter matching on the analog video signal characteristic information to obtain a target time sequence parameter matched with the analog video signal characteristic information;
s03: generating a first configuration parameter and a third configuration parameter according to the target time sequence parameter;
s04: sequentially generating a plurality of second configuration parameters;
s05: generating a sampling clock based on the synchronization signal and the first configuration parameter;
s06: carrying out phase adjustment operation on the sampling clock based on the plurality of second configuration parameters in sequence to obtain a plurality of adjusted sampling clocks;
s07: performing analog-to-digital conversion on the analog image data based on the plurality of adjusted sampling clocks in sequence to obtain digital image data;
s08: obtaining a digital video signal based on the third configuration parameter, the synchronization signal and the digital image data;
s09: detecting the digital video signal to obtain line edge characteristic information;
s10: and setting a target second configuration parameter and a target third configuration parameter based on the line edge characteristic information.
The present embodiment relates to an analog signal decoding process, such as VGA signal decoding process, and the scheme is implemented on the premise that VGA signal identification and timing detection are completed first. The decoding process includes, for example, the following flows: firstly, detecting a line synchronizing signal (HS) and a field synchronizing signal (VS) in an input VGA video to obtain a total vertical line number (Vtotal), a frame frequency (Vfreq) and a line frequency (Hfreq), then matching the closest item in a VGA signal time sequence template, wherein the time sequence template has necessary information in analog-to-digital conversion such as resolution, a pixel clock, Htotal and the like, then setting a VGA analog sampling clock according to the matched time sequence in the template to configure a digital image signal output time sequence after sampling, and then outputting the digital image after position and phase adjustment. The technical scheme of the embodiment of the invention adjusts the position and the sampling clock phase of the digital image, adjusts the set phase for multiple times, measures the image parameter, evaluates the optimal phase according to the image parameter under different phases, and finally converts the VGA analog video into the optimized digital video by using the obtained optimal phase.
In order to understand the present embodiment more clearly, the foregoing steps S00-S09 are described in detail below with specific examples.
Firstly, acquiring analog video signal characteristic information of a VGA video source from an input VGA analog video, wherein the analog video signal characteristic information comprises the total vertical line number, the frame frequency and the line frequency; meanwhile, a synchronization signal including, for example, an RGB analog signal and a field synchronization signal are separated from the input VGA analog video, and analog image data; then, matching the acquired analog video signal characteristic information with a VGA signal time sequence template to obtain an initialization time sequence parameter (target time sequence parameter) corresponding to the VGA signal characteristic; then generating a first configuration parameter and a third configuration parameter according to the target time sequence parameter, and sequentially generating a plurality of second configuration parameters (phase parameters of the sampling clock); then, generating a sampling clock (a sampling clock without phase parameters loaded) through the synchronization signal and the first configuration parameter, and then performing phase adjustment operation on the sampling clock sequentially based on the plurality of second configuration parameters to obtain a plurality of adjusted sampling clocks (a sampling clock with a plurality of phase parameters loaded sequentially); further, performing analog-to-digital conversion on the analog image data in step S01 sequentially based on the plurality of adjusted sampling clocks to obtain first digital image data; and obtaining a digital video signal based on the third configuration parameter, the synchronization signal and the first digital image data, wherein the digital video signal is a plurality of phase-adjusted digital video signals obtained by applying the second configuration parameter for a plurality of times.
In the above, after obtaining a plurality of adjusted digital video SIGNALs, detecting the synthesized digital video SIGNALs to obtain line edge feature information, specifically, as shown in fig. 2, a region in the center of the figure is a line image data display period (Displayed Area), gray regions on the left and right sides of the region are Horizontal Blanking regions (Horizontal Blanking), the region corresponds to a line effective display data enable SIGNAL (DE SIGNAL, data enable SIGNAL), the right side of the display region is an enlarged view of the edge feature information of a certain line cut out, and the edge feature information is pixel information at the boundary between the display region and the Blanking region; and finally, setting the second configuration parameter and the third configuration parameter based on the line edge characteristic information.
In addition, the total multi-line edge characteristic information of the image is respectively intercepted to obtain multi-line blanking area pixel data positioned at the edge of the image display area, and the optimal phase parameter is obtained after the multi-line blanking area pixel data is calculated. Specifically, referring to fig. 3, it is seen that the left side of the edge of the display region is a pixel in the display region, the right side is a pixel in the blanking region, and the default pixel in the blanking region is black, but there is a situation where a plurality of pixels are not black; in contrast, as shown in fig. 4, the edge feature information when the sampling clock phase parameter is normal is shown, and it can be seen that the pixels in the blanking area are all uniform pure black. The method of this embodiment is to adjust the phase parameter of the sampling clock continuously to achieve the image edge characteristics as shown in fig. 4 as much as possible, and the phase parameter used at this time is the optimal phase parameter capable of outputting the optimal digital video signal.
To sum up, in the process of converting the analog video signal into the digital video signal, the phase parameter of the sampling clock is continuously adjusted, and the multi-line edge characteristic information of the adjusted digital video signal is detected in real time to obtain the blanking region pixel data located at the edge of the image display region, and then the phase parameter when the blanking region pixel data is optimal is selected to process the input analog video signal, so as to finally obtain the digital video signal with the best display effect.
Second embodiment
On the basis of the foregoing embodiment, a method for processing an analog video signal according to a second embodiment of the present invention, as shown in fig. 5, further includes, after step S10:
s11: carrying out phase adjustment operation on the sampling clock based on the target second configuration parameter to obtain a target sampling clock;
s12: performing analog-to-digital conversion on the analog image data based on the target sampling clock to obtain second digital image data;
s13: and obtaining a digital video signal based on the target third configuration parameter, the synchronization signal and the second digital image data.
The steps are mainly used for continuously optimizing the digital video signals output after the phase adjustment. In the first embodiment, after the digital video signal without phase adjustment is obtained through the set initial first, second, and third configuration parameters, the digital video signal is evaluated by detecting the line edge feature information, if the output effect is not good, the second configuration parameter is adjusted, and the above steps are repeated in this way until the digital video signal reaches the standard value and is output to the display device, which is a test adjustment step of analog signal conversion.
Further, in step S09 of the foregoing embodiment, a method for evaluating line edge feature information includes:
firstly, acquiring line blanking area pixel data outside the edge of a line effective display data enabling signal of each of a plurality of pixel lines in the process of carrying out analog-to-digital conversion on analog image data on the basis of each adjusted sampling clock in a plurality of adjusted sampling clocks in sequence; comparing the pixel data of the line blanking area of each pixel line in the plurality of pixel lines with a threshold value, and counting the continuous point pixels exceeding the threshold value to obtain the line overrun pixel number of each pixel line; then, obtaining an overrun pixel data distribution based on the number of line overrun pixels of a plurality of pixel lines; and finally, distributing a plurality of sets of overrun pixel data respectively corresponding to the adjusted sampling clocks as line edge characteristic information.
With reference to fig. 6, the following describes how to set the optimal second and third configuration parameters based on the line edge feature information, by taking an example of an acquisition process of an overrun pixel data distribution:
in the scheme, any line of a line synchronizing signal is intercepted as a first line, and a first phase parameter corresponding to the first line synchronizing signal is set, wherein the first phase parameter is an initial phase parameter; next, a phase parameter is set for any line subsequent to the first line, and a line edge characteristic corresponding to the phase parameter is detected, where the any line may be a second line adjacent to the first line, or an ith line after skipping a plurality of lines from the first line, and for example, edge characteristic information to which the ith phase parameter is applied is designated as ith line edge characteristic information. By analogy, after N (N is more than 1) lines of edge characteristic information is detected and collected, the corresponding N lines of blanking area pixel data can be obtained. Comparing the pixel data of the blanking areas of the N lines with a threshold value one by one, if the set sampling clock phase parameter is not good, the pixel data of partial blanking areas exceed the threshold value, and at the moment, counting the continuous point pixels exceeding the threshold value from the edge of the display area to the direction of the blanking areas to obtain the number of the line exceeding the limit pixel; repeating the steps, and extracting the characteristics of the N lines to obtain the ultralimit pixel data distribution of the pixel data of the blanking area of the N lines. Then, the number of the overrun pixels of the N lines is counted to obtain the discrete degree of the pixel data of the corresponding blanking area, and the set phase parameter with the minimum discrete degree is selected as the optimal phase parameter.
It should be noted that, in the present embodiment, the threshold is, for example: a chromaticity range based on the chromaticity of pure black. If the difference of the chroma of a certain pixel in the blanking area relative to the pure black chroma exceeds a threshold value, the pixel can be marked as an overrun pixel, and the number of all the overrun pixels in the line blanking area is counted.
Meanwhile, due to the fact that pixel data outside the display area are counted, when the position of the image in the horizontal direction is deviated, the direction and the position of the image deviation can be detected, and then the horizontal deviation position of the VGA image is adjusted, and therefore the integrity of image display is guaranteed.
Third embodiment
As shown in fig. 7, an analog video processing apparatus 10 according to a third embodiment of the present invention includes: the device comprises an analog video decoder 11, a microcontroller 12 and a programmable logic device 13, wherein the three components are connected in pairs. Wherein the microcontroller 12 is, for example, an ARM-based embedded processor, and the Programmable logic device 13 is, for example, an FPGA (Field Programmable Gate Array).
The specific workflow of the analog video processing apparatus 10 is as follows:
first, the analog video decoder 11 acquires analog video signal characteristic information of the VGA video source from an input analog video such as a VGA analog video, the analog video signal characteristic information including, for example, the total number of vertical lines, the frame frequency, and the line frequency; then, a synchronous signal and analog image data are separated from the input VGA analog video, wherein the analog image data comprises RGB analog signals, and the synchronous signal comprises a line synchronous signal and a field synchronous signal;
then, the microcontroller 12 matches the acquired analog video signal characteristic information with a VGA signal timing template to obtain an initialization timing parameter (target timing parameter) corresponding to the VGA signal characteristic; generating a first configuration parameter, a third configuration parameter and a plurality of sequentially generated second configuration parameters according to the target time sequence parameter, and sending the first configuration parameter, the third configuration parameter and the plurality of sequentially generated second configuration parameters to the analog video decoder 11;
then, the analog video decoder 11 generates a sampling clock (a sampling clock without phase parameters loaded) through the synchronization signal and the first configuration parameter, performs multiple phase adjustment operations on the sampling clock sequentially based on a plurality of second configuration parameters to obtain an adjusted sampling clock (a sampling clock with phase parameters loaded), and performs analog-to-digital conversion on the analog image data based on the adjusted sampling clock to obtain first digital image data; then, based on the third configuration parameter, the synchronous signal and the first digital image data, obtaining a digital video signal;
then, the programmable logic device 13 performs a plurality of detections on the synthesized digital video signal to obtain line edge feature information. Specifically, as shown in fig. 2, the Area in the center of the figure is a line image data display period (Displayed Area), the gray areas on the left and right sides of the Area corresponding to a line effective display data enable SIGNAL (DE SIGNAL, data enable SIGNAL), the right side of the display Area is an enlarged view of edge feature information of the clipped plural lines, and the edge feature information is pixel information at the boundary of the display Area and the blank Area;
then, the microcontroller 12 extracts a plurality of distributions of the overrun pixel data from all the line edge feature information, and then performs the dispersion evaluation on the distributions of the overrun pixel data, and sets the optimal (target) second and third configuration parameters for the second and third configuration parameters corresponding to the distribution of the overrun pixel data with the minimum dispersion degree, as described in the second embodiment in detail
Finally, the analog video encoder 11 receives and executes the optimal (target) second and third configuration parameters, and outputs the digital video signal with the optimal display effect.
Fourth embodiment
As shown in fig. 8, an analog video processing apparatus 20 according to a fourth embodiment of the present invention includes: the device comprises a feature extraction module 21, a synchronous signal separation module 22, a microcontroller 23, a phase-locked loop 24, a data conversion module 25, a phase adjustment module 26, a time sequence reconstruction module 27 and a row edge detection module 28. The microcontroller 23 in the present embodiment may refer to the microcontroller 12 in the third embodiment, the row edge detection module 28 may refer to the programmable logic device 13 in the third embodiment, and the functions of the feature extraction module 21, the synchronization signal separation module 22, the phase-locked loop 24, the data conversion module 25, the phase adjustment module 26, and the timing reconstruction module 27 in the present embodiment may refer to the analog video decoder 11 in the third embodiment.
Specifically, the feature extraction module 21 is configured to receive an analog video signal, perform feature extraction on the analog video signal, obtain and output feature information of the analog video signal; a synchronous signal separation module 22, configured to perform synchronous signal separation on the analog video signal to obtain a synchronous signal and analog image data; the phase-locked loop 24 is respectively connected with the microcontroller 23 and the synchronous signal separation module 22, and is used for generating a sampling clock based on the synchronous signal and the first configuration parameter; the phase adjusting module 26 is respectively connected to the phase-locked loop 24 and the microcontroller 23, and is configured to perform a phase adjusting operation on the sampling clock sequentially based on the plurality of second configuration parameters to obtain a plurality of adjusted sampling clocks; the data conversion module 25 is connected to the phase adjustment module 26 and the synchronous signal separation module 22, and is configured to perform analog-to-digital conversion on the analog image data based on the adjusted sampling clocks to obtain digital image data; and the time sequence reconstruction module 27 is respectively connected to the data conversion module 25, the synchronization signal separation module 22 and the microcontroller 23, and is configured to obtain a digital video signal based on the third configuration parameter, the synchronization signal and the first digital image data.
Fifth embodiment
A fifth embodiment of the invention relates to a non-volatile storage medium for storing a computer-readable program for a processing device to perform some or all of the above method embodiments.
That is, as can be understood by those skilled in the art, all or part of the steps in the method for implementing the embodiments described above may be implemented by a program instructing related hardware, where the program is stored in a storage medium and includes several instructions to enable a device (which may be a single chip, a chip, or the like) or a Processor (Processor) to execute all or part of the steps of the method described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and/or method may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units/modules is only one logical division, and there may be other divisions in actual implementation, for example, multiple units or modules may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units/modules described as separate parts may or may not be physically separate, and parts displayed as units/modules may or may not be physical units, may be located in one place, or may be distributed on multiple network units. Some or all of the units/modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.
In addition, each functional unit/module in the embodiments of the present invention may be integrated into one processing unit/module, or each unit/module may exist alone physically, or two or more units/modules may be integrated into one unit/module. The integrated units/modules may be implemented in the form of hardware, or may be implemented in the form of hardware plus software functional units/modules.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. An analog video signal processing method, comprising:
receiving an analog video signal and extracting the characteristics of the analog video signal to obtain the characteristic information of the analog video signal;
carrying out synchronous signal separation on the analog video signal to obtain a synchronous signal and analog image data;
performing time sequence parameter matching on the analog video signal characteristic information to obtain a target time sequence parameter matched with the analog video signal characteristic information;
generating a first configuration parameter and a third configuration parameter according to the target time sequence parameter;
sequentially generating a plurality of second configuration parameters;
generating a sampling clock based on the synchronization signal and the first configuration parameter;
carrying out phase adjustment operation on the sampling clock based on the plurality of second configuration parameters in sequence to obtain a plurality of adjusted sampling clocks;
performing analog-to-digital conversion on the analog image data based on the plurality of adjusted sampling clocks in sequence to obtain digital image data;
obtaining a digital video signal based on the third configuration parameter, the synchronization signal and the digital image data;
detecting the digital video signal to obtain line edge characteristic information;
and setting a target second configuration parameter and a target third configuration parameter based on the line edge characteristic information.
2. The analog video signal processing method of claim 1, further comprising:
carrying out phase adjustment operation on the sampling clock based on the target second configuration parameter to obtain a target sampling clock;
performing analog-to-digital conversion on the analog image data based on the target sampling clock to obtain second digital image data;
and obtaining a digital video signal based on the target third configuration parameter, the synchronization signal and the second digital image data.
3. The method of analog video signal processing according to claim 1, wherein said step of detecting said digital video signal to obtain line edge feature information comprises:
acquiring line blanking area pixel data outside the line effective display data enable signal edge of each of a plurality of pixel lines in the process of carrying out analog-to-digital conversion on the analog image data based on each of the plurality of adjusted sampling clocks;
comparing the pixel data of the line blanking area of each pixel line in the plurality of pixel lines with a preset threshold value, and counting the continuous point pixels exceeding the threshold value to obtain the number of line overrun pixels of each pixel line;
obtaining an overrun pixel data distribution based on the line overrun pixel number of the plurality of pixel lines;
repeating the steps, and sequentially carrying out analog-to-digital conversion on the analog image data based on the plurality of adjusted sampling clocks to obtain a plurality of sets of overrun pixel data distribution; and
and distributing a plurality of sets of the overrun pixel data corresponding to the adjusted sampling clocks respectively as the line edge characteristic information.
4. The method of analog video signal processing according to claim 1, wherein said step of setting a target second configuration parameter and a target third configuration parameter based on said line edge feature information comprises:
extracting multiple sets of overrun pixel data distribution from the line edge characteristic information;
calculating the respective discrete degrees of the distribution of a plurality of sets of the overrun pixel data;
and setting the target second configuration parameter according to the second configuration parameter corresponding to the ultralimit pixel data distribution with the minimum dispersion degree, and setting the target third configuration parameter according to the ultralimit pixel data distribution with the minimum dispersion degree.
5. The method of claim 3, wherein the line blanking region pixel data outside the edge of the line active display data enable signal for each of said pixel lines comprises left blanking region pixel data and right blanking region pixel data located in a region where the line active display data is located.
6. An analog video processing apparatus, comprising:
an analog video decoder;
the programmable logic device is connected with the analog video decoder;
the microcontroller is connected with the analog video decoder and the programmable logic device;
wherein the analog video decoder is to: receiving an analog video signal, performing feature extraction on the analog video signal to obtain analog video signal feature information and outputting the analog video signal feature information, performing synchronous signal separation on the analog video signal to obtain a synchronous signal and analog image data, receiving a first configuration parameter and a third configuration parameter, sequentially receiving a plurality of second configuration parameters, generating a sampling clock based on the synchronous signal and the first configuration parameter, sequentially performing phase adjustment operation on the sampling clock based on the plurality of second configuration parameters to obtain a plurality of adjusted sampling clocks, sequentially performing analog-to-digital conversion on the analog image data based on the plurality of adjusted sampling clocks to obtain digital image data, and obtaining and outputting a digital video signal based on the third configuration parameter, the synchronous signal and the digital image data;
the programmable logic device is used for detecting the digital video signal to obtain and output line edge characteristic information;
the microcontroller is configured to: and performing time sequence parameter matching on the analog video signal characteristic information to obtain a target time sequence parameter matched with the analog video signal characteristic information, generating and outputting the first configuration parameter and the third configuration parameter according to the target time sequence parameter, sequentially outputting the plurality of second configuration parameters, and setting and outputting the target second configuration parameter and the target third configuration parameter based on the line edge characteristic information.
7. The analog video processing device of claim 6, wherein the analog video decoder is further configured to:
carrying out phase adjustment operation on the sampling clock based on the target second configuration parameter to obtain a target sampling clock;
performing analog-to-digital conversion on the analog image data based on the target sampling clock to obtain second digital image data;
and obtaining a digital video signal based on the target third configuration parameter, the synchronization signal and the second digital image data.
8. The analog video processing device of claim 6, wherein the programmable logic device for detecting the digital video signal to obtain the line edge feature information specifically comprises:
acquiring line blanking area pixel data outside the line effective display data enable signal edge of each of a plurality of pixel lines in the process of carrying out analog-to-digital conversion on the analog image data based on each of the plurality of adjusted sampling clocks;
comparing the pixel data of the line blanking area of each pixel line in the plurality of pixel lines with a preset threshold value, and counting the continuous point pixels exceeding the threshold value to obtain the number of line overrun pixels of each pixel line;
obtaining an overrun pixel data distribution based on the line overrun pixel number of the plurality of pixel lines;
repeating the steps, and sequentially carrying out analog-to-digital conversion on the analog image data based on the plurality of adjusted sampling clocks to obtain a plurality of sets of overrun pixel data distribution;
and distributing a plurality of sets of the overrun pixel data corresponding to the adjusted sampling clocks respectively as the line edge characteristic information.
9. The analog video processing device of claim 6, wherein said microcontroller is configured to set and output a target second configuration parameter and a target third configuration parameter based on said line edge feature information, and specifically comprises:
extracting multiple sets of overrun pixel data distribution from the line edge characteristic information;
calculating the respective discrete degrees of the distribution of a plurality of sets of the overrun pixel data;
and setting the target second configuration parameter according to the second configuration parameter corresponding to the ultralimit pixel data distribution with the minimum dispersion degree, and setting the target third configuration parameter according to the ultralimit pixel data distribution with the minimum dispersion degree.
10. An analog video processing apparatus, comprising:
the system comprises a characteristic extraction module, a characteristic extraction module and a characteristic extraction module, wherein the characteristic extraction module is used for receiving an analog video signal, extracting the characteristics of the analog video signal, obtaining the characteristic information of the analog video signal and outputting the characteristic information;
the synchronous signal separation module is used for carrying out synchronous signal separation on the analog video signal to obtain a synchronous signal and analog image data;
the microcontroller is connected with the characteristic extraction module and is used for carrying out time sequence parameter matching on the analog video signal characteristic information to obtain a target time sequence parameter matched with the analog video signal characteristic information, generating and outputting a first configuration parameter and a third configuration parameter according to the target time sequence parameter, and sequentially outputting a plurality of second configuration parameters;
the phase-locked loop is respectively connected with the microcontroller and the synchronous signal separation module and is used for generating a sampling clock based on the synchronous signal and the first configuration parameter;
the phase adjusting module is respectively connected with the phase-locked loop and the microcontroller and is used for sequentially carrying out phase adjusting operation on the sampling clock based on the plurality of second configuration parameters to obtain a plurality of adjusted sampling clocks;
the data conversion module is connected with the phase adjustment module and the synchronous signal separation module and is used for carrying out analog-to-digital conversion on the analog image data based on the adjusted sampling clocks to obtain digital image data;
the time sequence reconstruction module is respectively connected with the data conversion module, the synchronous signal separation module and the microcontroller and is used for obtaining a digital video signal based on the third configuration parameter, the synchronous signal and the digital image data;
the line edge detection module is respectively connected with the time sequence reconstruction module and the microcontroller and is used for detecting the digital video signal and obtaining line edge characteristic information;
wherein the microcontroller is further configured to set a target second configuration parameter and a target third configuration parameter based on the row edge feature information.
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| CN114520856A (en) * | 2020-11-20 | 2022-05-20 | 西安诺瓦星云科技股份有限公司 | Video time sequence signal generation method, programmable logic device and video control equipment |
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