CN206193088U - Detection circuitry of trackable peak value - Google Patents
Detection circuitry of trackable peak value Download PDFInfo
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- CN206193088U CN206193088U CN201621275084.0U CN201621275084U CN206193088U CN 206193088 U CN206193088 U CN 206193088U CN 201621275084 U CN201621275084 U CN 201621275084U CN 206193088 U CN206193088 U CN 206193088U
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- voltage comparator
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Abstract
The utility model provides a detection circuitry of trackable peak value, its characterized in that includes the voltage comparater that operational amplifier constitutes, the clock, the AND gate, scale up the counter, the DA converter, voltage comparater's homophase end is with continuous by the detected signal end, voltage comparater's output links to each other with one of them input of AND gate, the clock links to each other with another input of AND gate, the output of AND gate links to each other with the timing clock input who scales up counter end, the digital output who scales up the counter links to each other with DA converter digital input, the output of DA converter links to each other with voltage comparater's inverting terminal through resistance DELTA R, resistance R connects on 2 voltage comparater's outputs and inverting terminal. Compared with the prior art, the utility model, it is simple reliable to have the circuit, is fit for high low frequency and is surveyed the letter signal, and the interference killing feature is strong, and dynamic is big for peak detection electricity voltage.
Description
Technical field
The utility model is related to detect circuit, more particularly to a kind of peak detection circuit.
Background technology
Peak detection circuit is made an uproar in crest voltage detection, the burr seizure of waveform, impulse signal peakvalue's checking, bear vibration
The peakvalue's checking of sound, AGC (automatic growth control) circuits and sensor maximum are asked for etc. being all widely used in circuit.With
Continuous ripe and the development, peakvalue's checking application specific integrated circuit (peak of domestic semiconductor technology and IC design technology
Value detects ASIC) penetrate independent design module during detector front end reads chip as detection and study, turn into
One hot subject of domestic and international association area.Present peak value detection circuit be primarily present Peak detection accuracy it is not high, sampling frequency
The defects such as rate is too low, poor anti jamming capability, the non-linear ambassador's distorted signals of capacitance integral and system debug difficulty.
Current peak holding circuit is used as the important line unit for detecting circuit.From the sixties so far, peak holding circuit
Prime (detector and preamplifier) and rear class (A/D converters etc.) development it is extremely rapid, and as the peak of bridge
Value holding circuit but develops relatively slow, becomes the bottleneck that restriction whole system performance is improved.Traditional peak holding
Circuit is voltage-type, and the principle of circuit is simple, but integral nonlinearity is big, dynamic range it is small (small signal amplitudes difference in response,
General signal amplitude requirement is more than 200mV), passband is also small, and when fast signal is processed, performance is less than satisfactory.80
In the age, transconductance type peak-holding circuit is occurred in that, its performance is better than voltage-type.And constantly develop and be suitable for different needs
Transconductance type peak-holding circuit device.Although the peak holding circuit of transconductance type is better than voltage-type in performance, in circuit design
On there is also difficulty.Due to using trsanscondutance amplifier, there is an integrating factor relevant with electric capacity C in loop gain, in order to
The linear properties of circuit are improved, C as big as possible is needed, and increasing C can reduce the passband and Slew Rate of circuit.Meanwhile, it is
Big dynamic range and good small signal amplitudes response performance is obtained, the gain of most systems requirement circuit is 1, and
Small C can make circuit gain be 1 when it is unstable, so more difficult design existing larger passband and Slew Rate, have again compared with
Good linear properties and gain are 1 circuit.So there is no the preferable universal circuit of performance so far.
Utility model content
Goal of the invention of the present utility model be overcome existing peak detection circuit be primarily present Peak detection accuracy it is not high,
The defects such as sample frequency is too low, poor anti jamming capability, the non-linear ambassador's distorted signals of capacitance integral and system debug difficulty, carry
For a kind of traceable peak value that system debug is easy, accuracy of detection is high being suitable for wider frequency range, being not easy distortion
Detection road.
The utility model is achieved in that the voltage comparator constituted including operational amplifier, clock and door, is incremented by
Counter, D/A converter, the in-phase end of voltage comparator are connected with detected signal end, the output end of voltage comparator with
A wherein input of door is connected, and clock is connected with another input with door, output end and the meter of count-up counter with door
When input end of clock be connected, the numeral output of count-up counter is connected with D/A converter numeral input, the output of D/A converter
It is connected with the end of oppisite phase of voltage comparator through resistance Δ R, resistance R is attempted by 2 points of the output end and end of oppisite phase of voltage comparator
On, while D/A converter is output as the peak value of the tracing detection for tracking peak detection circuit.
Under original state, count-up counter is reset, and counter is output as zero, D/A converter output VOUT=0V, now by
Survey electric signal VINDuring≤0V, the voltage comparator that operational amplifier is constituted is output as zero i.e. low level, believes with the locked clock of door
Number can not be added on counter, counter output remains nought state, i.e. D/A converter output keeps VOUT=0V。
Under working condition, tested electric signals VIN>During 0V, voltage comparator upset is output as high level, is now beaten with door
Open, clock is added on counter, counter is started counting up, the input of D/A converter event counter is relevant voltage, and D/A turns
Parallel operation exports VOUTTracking VINChange, until VINReach one peak value VP1, now VOUT=VIN=VP1, voltage comparator output
It is zero i.e. low level, can not be added on counter with the locked clock signal of door, counter output keeps constant, i.e. D/A turns
Parallel operation output keeps VOUT==VIN=VP1.If VIN≤VP1Then VOUT=VP1Keep constant, if VINContinue to become big, voltage comparator
Upset again is output as high level, is now opened with door, and clock is added on counter, and counter is started counting up, and D/A converter turns
The input of counter is changed for relevant voltage, D/A converter output VOUTContinue to track VINChange, until VINReach its next
Peak value VP2, so not after tracking.
It is anti-interference, prevent from being superimposed upon V to improve certainty of measurementINUpper small interference signal causes false triggering, and circuit is utilized
The operational amplifier of resistance Δ R, resistance R and composition voltage comparator, the output for devising hysteresis circuitry, i.e. D/A converter is led to
Cross resistance Δ R to be connected with the end of oppisite phase of voltage comparator, resistance is connected between the end of oppisite phase and output end of voltage comparator
R.If VPNIt is VINPresent peak value, VP(N+1)It is VINNext peak value, then VIN≥VPN+ Δ V voltage comparators overturn, go with
Track VP (N+1),Rather than VIN≥VPNWhen voltage comparator upset go track VP(N+1), that is to say, that VINUpper small interference signal is less than
During Δ V, circuit will not overturn and be tracked measurement, here。
The utility model compared with the prior art, due to using operational amplification circuit, D/A conversion and digital circuit technique,
Avoid the use of capacitor C in traditional scheme.Therefore, the utility model has circuit simple and reliable, is adapted to low-and high-frequency and is tested
Letter signal, strong antijamming capability, peakvalue's checking piezoelectric voltage dynamic range is big, and most I surveys the voltage of μ V magnitudes, numeral compatibility
By force, it is adaptable to which the main logic such as TTL, COMS circuit, dynamic power are lost small advantage.
Brief description of the drawings
Fig. 1 is circuit diagram of the present utility model.
Specific embodiment：
The utility model is described in further detail in conjunction with drawings and Examples：
As illustrated, the utility model includes voltage comparator, clock and door, the incremental count that operational amplifier is constituted
Device, D/A converter, the in-phase end of voltage comparator are connected with detected signal end, the output end of voltage comparator with door
A wherein input is connected, and clock is connected with another input with door, during timing with the output end of door and count-up counter
Clock input is connected, and the numeral output of count-up counter is connected with D/A converter numeral input, and the output of D/A converter is through electricity
Resistance Δ R is connected with the end of oppisite phase of voltage comparator, and resistance R is attempted by 2 points of the output end of voltage comparator and end of oppisite phase, together
When D/A converter be output as track peak detection circuit tracing detection peak value.
The output for being provided with hysteresis circuitry, i.e. D/A converter is connected by resistance Δ R with the end of oppisite phase of voltage comparator
It is logical, between the end of oppisite phase and output end of voltage comparator and connecting resistance R.
The selection of D/A converter digit,, depending on certainty of measurement requirement, D/A converter digit digit is higher, and peak value is surveyed for this
Amount is higher, and eight, ten, 12, the D/A converter of sixteen bit can be taken here；According to selected D/A converter digit
The digit of determines counting device.
1. eight, ten, 12, the D/A converter of sixteen bit are selected according to the requirement of precision；
2. according to the digit of selected D/A converter digit determines counting device；
3. the size of resistance Δ R and R is determined according to Δ V, and its precision is more than one thousandth；
4. connect circuit according to schematic diagram and always adjust.
Claims (1)
1. a kind of detection circuit of traceable peak value, it is characterised in that the voltage comparator that is constituted including operational amplifier, clock,
With door, count-up counter, D/A converter, the in-phase end of voltage comparator is connected with detected signal end, voltage comparator it is defeated
Go out end to be connected with the wherein input with door, clock is connected with another input with door, output end and incremental meter with door
The elapsed time clock input of number device is connected, and the numeral output of count-up counter is connected with D/A converter numeral input, D/A conversions
The output of device is connected through resistance Δ R with the end of oppisite phase of voltage comparator, and resistance R is attempted by the output end of voltage comparator and anti-phase
Hold on 2 points, while D/A converter is output as the peak value of the tracing detection for tracking peak detection circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621275084.0U CN206193088U (en) | 2016-11-25 | 2016-11-25 | Detection circuitry of trackable peak value |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621275084.0U CN206193088U (en) | 2016-11-25 | 2016-11-25 | Detection circuitry of trackable peak value |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206193088U true CN206193088U (en) | 2017-05-24 |
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ID=58724487
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201621275084.0U Expired - Fee Related CN206193088U (en) | 2016-11-25 | 2016-11-25 | Detection circuitry of trackable peak value |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN206193088U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106645881A (en) * | 2016-11-25 | 2017-05-10 | 佛山科学技术学院 | Detection circuit capable of tracking peak value |
| CN108398590A (en) * | 2017-07-07 | 2018-08-14 | 佛山科学技术学院 | A kind of voltage peak detection circuit of numeral output |
-
2016
- 2016-11-25 CN CN201621275084.0U patent/CN206193088U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106645881A (en) * | 2016-11-25 | 2017-05-10 | 佛山科学技术学院 | Detection circuit capable of tracking peak value |
| CN108398590A (en) * | 2017-07-07 | 2018-08-14 | 佛山科学技术学院 | A kind of voltage peak detection circuit of numeral output |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20170524 Termination date: 20201125 |
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| CF01 | Termination of patent right due to non-payment of annual fee |