JP2010002345A - Ac test facilitating circuit and ac test method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an AC test facilitating circuit and an AC test method enabling easy measuring AC of any semiconductor devices. <P>SOLUTION: In an AC test facilitating circuit 1, a flip-flop FF1 in which an output Q inverted by an inverter IV1 is feed backed to an input D through an AND gate AN1 generates an AC measurement signal AC1 obtained by dividing a clock signal CK by 2, and a multiplexer MUX1 outputs the AC measurement signal AC1 to a last-stage flip-flop FF101 of a semiconductor device 100 in an AC test mode switched by an AC test mode signal TE instead of a normal circuit signal. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an AC test facilitating circuit and an AC test method.

  Among the specifications of semiconductor devices, there are AC specifications for output pins and input pins. Here, the AC spec for the output pin refers to a prescribed value of the delay from the clock input time until the output of the flip-flop at the final stage of the circuit that changes in synchronization with the clock is transmitted to the output pin. The AC specification for the input pin refers to the prescribed values of the setup time and hold time for the data input clock of the flip-flop at the first stage of the circuit.

  In a manufacturing test of a semiconductor device, it is necessary to perform a test related to AC specifications for such output pins and input pins.

  As a test method, for example, in AC measurement of an output pin, a semiconductor device is operated with a test vector whose output is an expected value, and the value of the output pin is observed while changing the strobe position of the tester. The method of measuring the delay value is taken. Also, in the AC measurement of the input pin, a test is performed while changing the timing of data input to the flip-flop at the first stage of the circuit, and the output pin to which the output of the flip-flop is transmitted is observed. The method of measuring the timing at which an error occurs due to a hold time violation is taken.

  However, in recent years, when AC measurement is performed by the above-described method, there is a problem that the number of test vector steps becomes enormous due to the deterioration of testability accompanying the increase in the scale of a semiconductor device. That is, in the AC measurement of the output pin, it takes time to set a desired value in the flip-flop of the final stage of the circuit to be tested. In the AC measurement of the input pin, the output of the flip-flop of the first stage of the circuit to be tested is taken. There is a problem that it takes time to transmit the value of to the output pin. This causes a problem that a lot of cost and time are required to create a test vector.

  In contrast, a conventional LSI device having a boundary scan test function is provided with an interface circuit between the internal circuit and the boundary scan register, and the device input pin and the device output pin are used for AC measurement execution. A control circuit that receives a signal obtained by decoding a specific instruction by an instruction decoder and outputs a control signal is provided, and the device input pin to the first stage flip-flop and the last stage flip-flop to the device output pin are independently provided. An AC measurement circuit that can be observed has been proposed (see, for example, Patent Document 1).

  This proposal only needs to create test vectors that activate from any device input pin to the first flip-flop and from any final flip-flop to the device output pin. Is shortened.

However, the above-described method using the AC measurement circuit is effective only when the semiconductor device is an LSI device having a boundary scan test function, and cannot be applied to a semiconductor device having no boundary scan test function. There was a problem.
JP 2000-97997 A (page 3-4, FIG. 2)

  Accordingly, an object of the present invention is to provide an AC test facilitating circuit and an AC test method capable of easily performing AC measurement in any semiconductor device.

  According to one aspect of the present invention, AC measurement signal generation means for generating an AC measurement signal synchronized with a clock signal, and the AC measurement signal in place of the normal circuit signal in the final stage flip-flop in the AC test mode And an AC test facilitating circuit characterized in that the circuit has a signal selection means for outputting to an AC test.

  According to another aspect of the present invention, there is provided a data holding means for holding the output of the first stage flip-flop for one clock period, and an error when the output of the first stage flip-flop matches the output of the data holding means. An AC test facilitating circuit comprising an error detecting means for outputting a signal is provided.

  According to the present invention, AC measurement can be easily performed with any semiconductor device.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a circuit diagram showing an example of the configuration of an AC test facilitating circuit and a semiconductor device including the same according to Embodiment 1 of the present invention.

  The AC test facilitating circuit 1 of the present embodiment is a flip-flop that generates an AC measurement signal AC1 obtained by dividing the clock signal CK by two by feeding back the output Q inverted by the inverter IV1 to the input D via the AND gate AN1. A flop FF1 and a multiplexer MUX1 that outputs an AC measurement signal AC1 to the final flip-flop FF101 of the semiconductor device 100 instead of the normal circuit signal by switching according to the AC test mode signal TE.

  The reset signal R is input to the other input of the AND gate AN1. The reset signal R sets the value of the AC measurement signal AC1 in the reset state to “0”.

  In the semiconductor device 100, the final stage flip-flop FF101 to which the output of the AC test facilitating circuit 1 is input, the output buffer BUF101 to which the output of the final stage flip-flop FF101 is input, and the output of the output buffer BUF101 are connected. Output pin OP101.

  By using the AC test facilitating circuit 1, AC measurement of the output pin OP101 to which the output of the final stage flip-flop FF101 is connected can be easily performed.

  The AC measurement method will be described with reference to FIG.

  When the reset signal R is raised and the reset state of the flip-flop FF1 is released, the half frequency of the clock signal CK is output as the AC measurement signal AC1.

  When the AC test execution mode is set to “0” by setting the AC test mode signal TE to “0”, the AC measurement signal AC1 is input to the final stage flip-flop FF101.

  The final stage flip-flop FF101 takes in the AC measurement signal AC1 at the rising edge of the clock signal CK.

  The data fetched by the final flip-flop FF101 is output to the output pin OP101 via the output buffer BUF101.

  Therefore, a load defined by the AC specification is connected to the output pin OP101, and a delay value from when the clock signal CK rises until the expected value of the AC measurement signal AC1 is output is measured.

  Thereby, it is possible to determine whether or not the delay until the output of the final stage flip-flop FF101 is transmitted to the output pin OP101 satisfies the AC specification.

  According to the present embodiment, the AC test of the output pin to which the output of the final stage flip-flop is connected can be easily performed by inputting the clock signal in any semiconductor device. it can. As a result, the cost and time required for creating test vectors for AC testing can be greatly reduced.

  In the first embodiment, the initial value of the AC measurement signal is fixed to “0”, but in this embodiment, the initial value of the AC measurement signal can be set to either “0” or “1”. An example of an AC test facilitating circuit is shown.

  FIG. 3 is a circuit diagram showing an example of the configuration of an AC test facilitating circuit according to Embodiment 2 of the present invention.

  In the AC test facilitating circuit 2 of the present embodiment, instead of the AND gate AN1 of the first embodiment, the output of the flip-flop FF1 inverted by the inverter IV1 via the multiplexer MUX2 using the reset signal R as an input selection signal. Q is fed back to input D of flip-flop FF1.

  The initial value setting signal IS is input to the other input of the multiplexer MUX2.

  The multiplexer MUX outputs an initial value setting signal IS to the flip-flop FF1 when the reset signal R sets the reset state. Thus, in the reset state, the AC measurement signal AC2 output from the flip-flop FF1 is initialized to the value input by the initial value setting signal IS.

  Thereafter, when the reset by the reset signal R is released, the flip-flop FF1 performs a frequency division operation, and outputs the half frequency of the clock signal CK as the AC measurement signal AC2.

  FIG. 4 shows an example of initial value setting of the AC test facilitating circuit 2.

  4A shows an example in which the initial value setting signal IS is set to “0” and the initial value of the AC measurement signal AC2 is set to “0”. FIG. 4B shows the initial value setting signal IS set to “0”. As an example, an initial value of the AC measurement signal AC2 is set to “1” as “1”.

  An effective use of the AC test facilitating circuit 2 of this embodiment is to use it in a semiconductor device in which a plurality of final stage flip-flops are connected to one output pin via a combinational logic circuit. By connecting one AC test facilitating circuit 2 of this embodiment to each input of a plurality of final stage flip-flops, the output delay from each final stage flip-flop to the output pin is measured. be able to.

  FIG. 5 shows an example of a semiconductor device including the AC test facilitating circuit 2 of the present embodiment. Here, an example is shown in which three final-stage flip-flops are connected to one output pin via a combinational logic circuit.

  In the semiconductor device 200 shown in FIG. 5, the outputs of the three final-stage flip-flops FF201, FF202, and FF203 are input to the output buffer BUF201 via the combinational logic circuit including the AND gate AN201 and the OR gate OR201, and the output buffer BUF201. Are connected to the output pin OP201.

  In this semiconductor device 200, the AC test facilitating circuits 2A, 2B, and 2C of this embodiment are connected to the inputs of the final stage flip-flops FF201, FF202, and FF203 one by one.

  Individual reset signals R1, R2, and R3 and individual initial value setting signals IS1, IS2, and IS3 are input to the AC test facilitating circuits 2A, 2B, and 2C, respectively. Therefore, the reset state and the initial value of the AC measurement signal AC2 can be individually set in the AC test facilitating circuits 2A, 2B, and 2C.

  That is, when the AC test mode is set by the AC test mode signal TE, the initial value of the AC measurement signal AC2 having an arbitrary value is output to the outputs S1, S2, and S3 of the AC test facilitating circuits 2A, 2B, and 2C at an arbitrary timing. A value can be output.

  Thus, an arbitrary signal transmission path can be formed in the combinational logic circuit, and only the output of the final stage flip-flop to be measured can be transmitted to the output pin OP201. That is, the AC test of the final stage flip-flop can be executed.

  For example, when the AC test of the final flip-flop FF201 is performed, the output S2 of the AC test facilitating circuit 2B is set to ‘1’, and the output S3 of the AC test facilitating circuit 2C is set to ‘0’. Similarly, when the AC test of the final flip-flop FF202 is performed, the output S1 of the AC test facilitating circuit 2A is set to ‘1’, and the output S3 of the AC test facilitating circuit 2C is set to ‘0’. Further, when performing the AC test of the final flip-flop FF203, either the output S1 of the AC test facilitating circuit 2A or the output S2 of the AC test facilitating circuit 2B may be set to '0'.

  FIG. 6 shows an example of output delay measurement at the output pin OP201 of the semiconductor device 200.

  In this example, by operating the reset signals R1, R2, and R3 and the initial value setting signals IS1, IS2, and IS3, the rising delay and falling delay of the final stage flip-flop FF201 are measured at times t1 and t2, and the time t4. T5, the rising delay and falling delay of the final flip-flop FF202 are measured, and the rising delay and falling delay of the final flip-flop FF203 are measured at times t7 and t8.

  According to the present embodiment, even in a semiconductor device in which a plurality of final stage flip-flops are connected to one output pin via a combinational logic circuit, an AC test of each final stage flip-flop is performed. Can be easily implemented with simple combinations of test signals. As a result, the cost and time required for creating a test vector for AC test can be further reduced.

  In the first and second embodiments, an example of an AC test facilitating circuit for the final stage flip-flop is shown. However, in this embodiment, an example of an AC test facilitating circuit for the first stage flip-flop is shown.

  FIG. 7 is a circuit diagram showing an example of the configuration of an AC test facilitating circuit and a semiconductor device including the same according to Embodiment 3 of the present invention.

  The AC test facilitating circuit 3 of this embodiment includes a flip-flop FF3 that holds the output of the first-stage flip-flop FF301 of the semiconductor device 300 for one clock period of the clock signal CK, and the output of the first-stage flip-flop FF301 and the flip-flop. And an EX-NOR gate EN3 that outputs “1” as the error signal ER when the outputs of the FF3 coincide with each other.

  In the semiconductor device 300, the input signal IN input to the input pin IP301 is input to the first stage flip-flop FF301 via the input buffer BUF301. The first-stage flip-flop FF301 takes in the output of the input buffer BUF301 at the rising edge of the clock signal CK.

  Next, a method for measuring the data input timing margin of the first stage flip-flop FF301 using the AC test facilitating circuit 3 of this embodiment will be described with reference to FIG.

  When measuring the data input timing margin of the first-stage flip-flop FF301, the value of the input signal IN is inverted every clock and input to the input pin IP301 while changing the input timing every clock.

  At this time, if there is a sufficient timing margin between the data input of the first stage flip-flop FF301 and the clock signal CK, the output value of the first stage flip-flop FF301 and the flip-flop as shown in FIG. This is different from the value one clock before held in FF3. Therefore, the error signal ER output from the EX-NOR gate EN3 is “0”.

  On the other hand, as shown in FIG. 8B, when the setup time for data input of the first-stage flip-flop FF301 with respect to the clock signal CK begins to be insufficient, the first-stage flip-flop FF301 is the value after the change of the input signal IN. The value before the change will be imported. As a result, the output value of the first stage flip-flop FF301 and the value of the flip-flop FF3 coincide with each other, and '1' is output to the error signal ER output from the EX-NOR gate EN3.

  Therefore, the time difference between the input signal IN and the clock signal CK at this time is measured, and the value is set as the setup time of the first stage flip-flop FF301.

  On the other hand, as shown in FIG. 8C, when the hold time of the data input of the first stage flip-flop FF301 with respect to the clock signal CK begins to run short, the first stage flip-flop FF301 cannot capture the value before the change of the input signal IN. The value after the change will be taken in. As a result, also in this case, the value of the output of the first stage flip-flop FF301 and the value of the flip-flop FF3 match, and “1” is output to the error signal ER output from the EX-NOR gate EN3. become.

  Therefore, the time difference between the input signal IN and the clock signal CK at this time is measured, and the value is set as the hold time of the first stage flip-flop FF301.

  In this way, the timing margin of the first stage flip-flop can be easily measured by simply connecting the AC test facilitating circuit 3 of this embodiment to the output of the first stage flip-flop and observing the error signal ER.

  FIG. 9 is a circuit configuration example of the semiconductor device 400 in which the AC test facilitating circuit 3 of this embodiment is connected to each of the outputs of the plurality of first-stage flip-flops, and the error signal ER is output as one signal. is there.

  In this example, the AC test facilitating circuits 3A, 3B, and 3C of this embodiment are connected to the outputs of the three first-stage flip-flops FF301, FF302, and FF303, respectively.

  The outputs of the AC test facilitating circuits 3A, 3B, and 3C are input to AND gates AN31, AN32, and AN33, respectively. The outputs of the AND gates AN31, AN32, and AN33 are input to the OR gate 31, and the output of the OR gate 31 becomes an error signal ER.

  Test enable signals EN1, EN2, and EN3 are input to the other inputs of the AND gates AN31, AN32, and AN33, respectively.

  The inputs of the first stage flip-flops FF301, FF302, and FF303 are connected to the input pins IP301, IP302, and IP303 via the input buffers BUF301, BUF302, and BUF303, respectively.

  When measuring the input timing margin of each first stage flip-flop of this semiconductor device 400, only the test enable signal of the output path of the first stage flip-flop to be measured is set to '1', and the input signal to the first stage flip-flop Is changed as shown in FIG.

  That is, when measuring the input timing margin of the first stage flip-flop FF301, the test enable signal EN1 = “1” (EN2 = “0”, EN3 = “0”) and the value of the input signal IN1 is set every clock. The signal is inverted and input to the input pin IP301 while changing the input timing every clock.

  Similarly, when measuring the input timing margin of the first stage flip-flop FF302, the test enable signal EN2 = '1' (EN1 = '0', EN3 = '0') and the value of the input signal IN2 is set for each clock. And input to the input pin IP302 while changing the input timing every clock.

  Further, when measuring the input timing margin of the first stage flip-flop FF303, the test enable signal EN3 = “1” (EN1 = “0”, EN2 = “0”) and the value of the input signal IN3 is set every clock. The signal is inverted and input to the input pin IP303 while changing the input timing every clock.

  In each measurement, the input timing margin for the clock signal CK of each first stage flip-flop is measured by measuring the time difference between the input signal when the error signal ER starts to output “1” and the clock signal CK. be able to.

  According to this embodiment, since an error signal is output when a timing error starts to occur in the first stage flip-flop, it is possible to easily know the timing margin limit of the first stage flip-flop. AC measurement of the input pin connected to the flop can be easily performed.

1 is a circuit diagram illustrating an example of a configuration of an AC test facilitating circuit according to a first embodiment of the present invention and a semiconductor device including the same. FIG. 3 is a diagram illustrating an execution example of an AC test using the AC test facilitating circuit according to the first embodiment. FIG. 6 is a circuit diagram illustrating an example of the configuration of an AC test facilitating circuit according to a second embodiment of the invention. FIG. 10 is a diagram illustrating an example of initial value setting of the AC test facilitating circuit according to the second embodiment. FIG. 6 is a circuit diagram illustrating an example of a configuration of a semiconductor device including an AC test facilitating circuit according to a second embodiment. FIG. 10 is a diagram illustrating an execution example of an AC test using the AC test facilitating circuit according to the second embodiment. FIG. 6 is a circuit diagram illustrating an example of the configuration of an AC test facilitating circuit according to a third embodiment of the present invention and a semiconductor device including the same. FIG. 10 is a diagram illustrating an execution example of an AC test using the AC test facilitating circuit according to the third embodiment. FIG. 10 is a circuit diagram illustrating an example of the configuration of another semiconductor device including the AC test facilitating circuit according to the third embodiment.

Explanation of symbols

1, 2, 3 AC test facilitating circuit FF1, FF3 Flip flop IV1 Inverter AN1, AN31-AN33 AND gate MUX1, MUX2 Multiplexer EN3 EX-OR gate OR31 OR gate

Claims (5)

AC measurement signal generation means for generating an AC measurement signal synchronized with the clock signal;
An AC test facilitating circuit comprising: signal selection means for outputting the AC measurement signal to a final flip-flop in place of a normal circuit signal in an AC test mode. 2. The AC test facilitating circuit according to claim 1, further comprising initial value setting means for setting an initial value of the AC measurement signal. An AC measurement method for a semiconductor device comprising the AC test facilitating circuit according to claim 1,
AC measurement of the output pin to which the output of the final stage flip-flop is connected,
An AC test method comprising: measuring a delay value from input of the clock signal to output of an expected value of the AC measurement signal. Data holding means for holding the output of the first stage flip-flop for one clock period;
An AC test facilitating circuit comprising error detection means for outputting an error signal when the output of the first stage flip-flop coincides with the output of the data holding means. An AC measurement method for a semiconductor device comprising the AC test facilitating circuit according to claim 4,
AC measurement of the input pin connected to the input of the first stage flip-flop,
A signal whose value is inverted every clock is applied to the input pin while changing the input timing every clock, and the input timing at which the error signal is output is measured as a timing margin for the clock signal at the input pin. AC test method characterized by the above.

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