JPH05240920A - Circuit for reducing waveform deterioration of clock transfer circuit - Google Patents

Abstract

PURPOSE:To reduce waveform deterioration caused by a clock transfer circuit by giving the output of a clock generator to the clock transfer circuit through a frequency dividing circuit and connecting a leading and trailing edge detection circuits to the output of the clock transfer circuit, and then, synthesizing the outputs of the leading and trailing edge detection circuits by means of a synthe sizing circuit. CONSTITUTION:A clock generator 1 generates a clock 11 and a frequency dividing circuit 2 divides the frequency of the clock 11. A transfer circuit 3 inputs the output of the circuit 2 and the output of the circuit 3 is connected to a leading and trailing edge detection circuits 4 and 5. A synthesizing circuit synthesizes the outputs of the circuits 4 and 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for reducing waveform deterioration of a clock transfer circuit used in an IC tester.

[0002]

2. Description of the Related Art Next, a schematic structure of an IC tester will be described with reference to FIG. In FIG. 4, 1 is a clock generator, 7 is a pattern generator, 8 is a waveform formatter, and 9 is pin electronics.

The clock generator 1 generates a clock 11 every test cycle. When the clock 11 is input, the pattern generator 7 outputs the pattern data to the waveform formatter 8 for each test cycle. The waveform formatter 8 holds the pattern data with the clock 11 and then waveform-formats the pattern data and supplies the pattern data to the pin electronics 9.

In FIG. 4, the clock 11 is applied to the pattern generator 7 and the waveform formatter 8. As the system becomes larger, the distance between the units becomes longer and the connecting cable also becomes longer. For example, the length of the connecting cable is 4m
From 6m. On the other hand, the pulse width of the clock 11 becomes narrower as the test cycle becomes faster, and the pulse width of the clock 11 becomes 5 ns when the test cycle is 100 MHz.
When the test cycle is 200MHz, the pulse width of clock 11 is only 2.5ns. Accurate transfer of these clocks 11 requires the use of high-speed devices and advanced pulse transmission technology.

Next, the configuration of the clock transfer circuit according to the prior art will be described with reference to FIG. 5A is a driver 3
B is a cable and 3C is a receiver. Driver 3A,
The cable 3B and the receiver 3C constitute the clock transfer circuit 3. The clock 11 of the clock generator 1 is given to the pattern generator 7 through the clock transfer circuit 3.

Next, the waveform diagram of each part of FIG. 5 will be described with reference to FIG. 6A shows the output of the driver 3A, FIG. 6A shows the input of the receiver 3C, and FIG. 6C shows the output of the receiver 3C. When transferring a high-speed clock, the clock waveform from the driver 3A goes down before the clock completely rises by passing through the cable 3B, and as a result, the receiver 3C has a pulse width smaller than that of the original clock. A narrow pulse comes out. The phenomenon becomes remarkable when the distance of the cable is long or when the high frequency characteristics are poor. Therefore,
In order to transfer the clock 11 accurately, it is necessary to shorten the physical distance between the units and to use a cable having good high frequency characteristics.

[0007]

In FIG. 5, it is difficult to transfer a narrow clock pulse width while preventing waveform deterioration. According to the present invention, the output of the clock generator 1 is supplied to the clock transfer circuit 3 through a frequency dividing circuit, the rising edge detection circuit and the falling edge detection circuit are connected to the output of the clock transfer circuit 3, and the rising edge detection circuit and the falling edge are connected. An object of the present invention is to provide a circuit that reduces waveform deterioration due to the clock transfer circuit 3 by combining the outputs of the edge detection circuits.

[0008]

To achieve this object, according to the present invention, a clock generator 1 for generating a clock 11, a frequency dividing circuit 2 for dividing the clock 11 and an output of the frequency dividing circuit 2 are provided. The transfer circuit 3 used as an input and the rising edge detection circuit 4 for detecting the rising edge of the output of the transfer circuit 3
And a falling edge detection circuit 5 for detecting the falling edge of the output of the transfer circuit 3, and a combining circuit 6 for combining the outputs of the rising edge detection circuit 4 and the falling edge detection circuit 5.

[0009]

Next, the configuration of the circuit for reducing the waveform deterioration of the clock transfer circuit according to the present invention will be described with reference to FIG. 1 is a frequency dividing circuit, 4 is a rising edge detecting circuit, 5 is a falling edge detecting circuit, 6 is a combining circuit, and the others are the same as those in FIG. The output of the synthesis circuit 6 is supplied to the pattern generator 7 of FIG.

The clock 11 is output from the clock generator 1, and the frequency dividing circuit 2 divides the frequency of the clock 11. The output of the frequency dividing circuit 2 is supplied to the transfer circuit 3, and the output of the transfer circuit 3 is connected to the rising edge detection circuit 4 and the falling edge detection circuit 5. The rising edge detection circuit 4 generates a pulse synchronized with the rising edge of the output of the transfer circuit 3, and the falling edge detection circuit 5 generates a pulse synchronized with the falling edge of the output of the transfer circuit 3. The output of the rising edge detection circuit 4 and the output of the falling edge detection circuit 5 are combined by the combining circuit 6, and a clock having the same shape as the clock 11 is supplied to the pattern generator 7.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the circuit of the embodiment of FIG. 1 will be described with reference to FIG. In FIG. 2, a D-type flip-flop is used for the frequency dividing circuit 2, and the driver 3A, cable 3B, and receiver 3C of FIG. 5 are used for the transfer circuit 3. The clock 11 is applied to the clock terminal of the D-type flip-flop 2, and the D-type flip-flop 2 divides the clock 11 in half in synchronization with the rising edge of the clock 11. The output is given to the rising edge detection circuit 4 through the driver 3A, the cable 3B and the receiver 3C. The rising edge detection circuit 4 is composed of a delay line 4A and an AND gate 4B. The input of the AND gate 4B is supplied with the delayed inverted output and the non-delayed output from the receiver 3C, and the output of the AND gate 4B outputs a pulse having the width of the delay amount of the delay line 4A synchronized with the rising edge. .

The falling edge detection circuit 5 includes delay lines 5A and A
It is composed of the ND gate 5B. Falling edge detection circuit 5
A pulse having the width of the delay amount of the delay line 5A synchronized with the falling edge is output to the output of the. The combining circuit 6 is composed of an OR gate, and the output of the AND gate 4B and the output of the AND gate 5B are combined by the OR gate.

Next, a time chart of each part of FIG. 2 is shown in FIG.
Will be explained. FIG. 3A shows the waveform of the clock 11,
FIG. 3A shows the output waveform of the driver 3A. 3C shows an input waveform of the receiver 3C, and FIG. 3D shows an AND gate 4B.
Is an output waveform of. 3E shows the output waveform of the AND gate 5B, and FIG. 3C shows the output waveform of the OR gate 6, and the same clock as the clock 11 of the clock generator 1 is obtained from the output of the OR gate 6.

[0014]

According to the present invention, a clock having a frequency half that of the test cycle passes through the transfer circuit, so that the clock completely rises and then falls, so that the deterioration of the waveform is small and the clock is faithful. Can be transferred to.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a clock transfer circuit according to the present invention.

FIG. 2 is a circuit diagram of the embodiment shown in FIG.

FIG. 3 is a time chart of each part of FIG.

FIG. 4 is a schematic explanatory diagram of an IC tester.

FIG. 5 is a configuration diagram of a clock transfer circuit according to a conventional technique.

FIG. 6 is a waveform diagram of FIG.

[Explanation of symbols]

 1 Clock Generator 2 Dividing Circuit 3 Transfer Circuit 4 Rising Edge Detection Circuit 5 Falling Edge Detection Circuit 6 Synthesis Circuit 7 Pattern Generator 8 Waveform Format 9 Pin Electronics 11 Clock

Claims (1)

[Claims] 1. A clock generator for generating a clock (11)
(1), a divider circuit (2) that divides the clock (11), a transfer circuit (3) that receives the output of the divider circuit (2) as input, and a rising edge of the output of the transfer circuit (3). Rising edge detection circuit (4), a falling edge detection circuit (5) that detects the falling edge of the output of the transfer circuit (3), a rising edge detection circuit (4) and a falling edge detection circuit ( Five)
And a synthesis circuit (6) for synthesizing the outputs of the clock transfer circuit.