JP2817132B2 - IC test equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC test apparatus used for testing the operation of an IC.

[0002]

2. Description of the Related Art FIG. 2 shows a configuration of a conventional IC test apparatus. In the figure, reference numeral 10 denotes an IC tester main body, and reference numeral 20 denotes a test head. The IC under test 21 is mounted on the test head 20. Although not particularly shown in the drawing, a test pattern signal is supplied to the IC under test 21 from the IC tester main body 10, and a response output thereof is taken into the first timing circuit 22.

The first timing circuit 22 is generally constituted by a D-type flip-flop, and is provided with a strobe pulse STR sent from the IC tester main body 10 through a first signal path 31.
The response output of the IC under test 21 is timed at the timing of B, and the timed response output signal is sent to the IC tester main body 10 through the second signal path 32. A second timing circuit 11 is provided on the IC tester main body 10 side.
Then, the response output of the IC under test 21 is sent to the logical comparator 12.

The logic comparator 12 receives the response output signal of the IC under test 21 and the expected value pattern signal, compares them, monitors the presence or absence of a mismatch, and determines the quality of the IC 21 under test. Conventionally, a strobe pulse is applied to a second timing circuit 11 provided in the IC tester main body 10 through a delay circuit 13. The delay time of the delay circuit 13 includes a delay time t ₁ + t _cb + t ₂ of the first signal path 31, a delay time t ₃ of the first timing circuit 22, and a delay time t ₄ of the second signal path 32.
In addition to the sum of + t _cb + t ₅ , a delay time tα is added in order to time a portion where a sufficient time has elapsed from a change point of the response output signal supplied to the second time adjustment circuit 11.

This situation will be described with reference to FIG. FIG. 3A
Shows the waveform of the strobe pulse STRB at the point a shown in FIG. One cycle t _c of the strobe pulse STRB corresponds to one test cycle, and the user can set this cycle t _c within an allowable range. That is, when testing a high-speed element, the cycle t _c is set to a short time.

FIG. 3B shows a strobe pal at point b shown in FIG.
3 shows a waveform of the STRB. The strobe pulse at this point b
STRB is the first signal path 31 from the strobe pulse at point a.
Delay time t₁+ T_cb+ T_TwoOnly late. FIG. 3C is FIG.
The response output signal SOUT at the point c shown in FIG. At this point c
The response output signal SOUT to be output is the strobe signal at point b.
The delay time t of the first timing circuit 22_ThreeOnly further delay
You. FIG. 3D shows the response output signal SOUT at point d shown in FIG.
The waveform is shown. At the point d, the second signal is more than the signal at the point c.
Delay time t of road 32_Four+ T _cb+ T_FiveJust delay.

FIG. 3E shows the timing of the strobe pulse STRB given to the point e shown in FIG. The strobe pulse STRB is supplied to the first signal path 31 and the second signal path 32
At the timing obtained by adding the delay time t ₃ of the first timing circuit 22 to the delay time of
A delay time obtained by adding a delay time tα for matching the time elapsed from the change point of OUT to the delay circuit 1
3 and to the clock input terminal of the second timing circuit 11.

As described above, the delay set in the delay circuit 13
The breakdown of time will be understood. The delay circuit 13 is a first signal
Gate G included in road 31₁With the same semiconductor chip
Gate D for delay₁, D_Two, D_Three… D_nTo form
Is done. Gate G₁And gate D₁Is the same semiconductor chip
The gate G can be formed close to the gate. ₁
Delay time t₁And gate D₁Delay time is small
Key (error). In general
It is said that the variability within the loop is within the range of ± 10%.

On the other hand, the gates D _{2 to} D of the delay circuit 13
_n denotes gates G ₂ , G ₄ ,
G ₅ and the delay times t ₂ , t ₃ ,
t _4, t ₅ and the delay time of the cable 2t _cb and t alpha delay time plus _{t dc = t 2 + t 3} + t 4 + t 5 + 2t cb + tα
Must have a delay time that conforms to Gate G
₂ , G ₄ and G ₅ are formed on a semiconductor chip different from the semiconductor chip constituting the delay circuit 13. The variation in delay time between semiconductor chips is said to be ± 30%. It is said that the variation in the delay time of the cable is ± 1%.

As described above, even if a gate of the same standard is formed in a semiconductor chip or in another semiconductor chip, the delay time of the delay circuit 13 and the delay time of the second signal path 32 vary. When the worst value of the variation in delay time in consideration of this variation and _{t cmax1 t cmax1 = 0.2t 1 +0.6} (t 2 + t 3 + t 4 + t 5 + t dc) + 0.02 (2t cb) + t s + t _h ... (1) Incidentally, t _s is the setup time of the flip-flops constituting the second sage circuit 11, t _h indicates the hold time of the flip-flop.

[0011]

The worst value of the variation of the delay time between the second signal path 32 and the delay circuit 13 is t _cmax1.
Causes a shift in the timing of the second timing circuit 11 shown in FIG. 3E. If the shift amount increases, for example, in addition, the phase of the strobe pulse STRB shifts in the delay direction, so that the allowable time T _M (see FIG. 3E) in which the second output circuit 11 can time the response output signal is short. Cycle time t _{c that} can be set by the user
(FIG. 3A) cannot be set for a short time. That is, a high-speed test cannot be performed.

An object of the present invention is to make the worst value of the delay time variation for adjusting the phase of the strobe pulse given to the second timing circuit 11 as small as possible, and to perform a test of a high-speed element. The purpose of the present invention is to provide an IC test apparatus which enables the test.

[0013]

According to the present invention, a first timing circuit is provided on the test head side, a strobe pulse is supplied to the first timing circuit through a first signal path, and the response of the IC under test 21 is caused by the strobe pulse. Time the output signal. The response output of the IC under test timed by the first timing circuit is sent to the IC tester main body through the second signal path, and is again timed by the second timing circuit provided in the IC tester main body. An IC test apparatus having a structure to supply a comparator with a strobe pulse supplied to a first timing circuit through a third signal path configured to be equivalent to the second signal path. is there. Therefore, according to the present invention, the reference timing point of the strobe pulse becomes the strobe pulse supply point of the first timing circuit. As a result, the second
The delay time of the strobe pulse given to the time setting circuit is only one-way delay time of the signal path, and is about half of the delay time given by the conventional delay circuit 13.

Accordingly, the worst value of the delay time of the strobe pulse given to the second timing circuit can be halved, and a high-speed test can be performed accordingly.

[0015]

FIG. 1 shows the configuration of an IC test apparatus according to the present invention. In the present invention, a strobe pulse STRB for timing is provided to a first timing circuit 22 provided on the test head 20 side through a first signal path 31, and a response output of the IC under test 21 timed by the first timing circuit 22 is provided. The signal is timed by the first timed circuit, and the timed output is passed through the second signal path 32 to the IC.
A second timing circuit 11 provided on the tester body 10 side
In the IC test apparatus having a structure in which the timing is output again by the timing circuit 11, the output of the timing is input to the logical comparator 12, and the logical value is compared with the expected value to determine the quality of the IC under test 21. The third signal path 33 is provided to return the strobe pulse given to the second 22 and to give it to the second timing circuit 11. That is, the strobe pulse given to the first timing circuit 22 is changed to the third signal having the same delay time as the second signal path 32.
The signal is sent back to the IC tester main body 10 through the signal path 33, and the second staging circuit 11 performs a time-out operation using the returned strobe pulse.

According to the configuration of the present invention, the strobe pulse
The reference point of the timing is the clock input of the first timing circuit 22.
Move to force terminal (point b). That is, the second timing circuit 11
The delay time of the strobe pulse given to
The delay time t of the time circuit 22_ThreeAnd when the second signal path 32 is delayed
Interval t_Four+ T_cb+ T_FiveAnd the delay time obtained by adding the correction value tα
Just give it. The correction value tα is applied to the third signal path 33 here.
Delay time t of the part of the cable inserted_cb1Included in
t_cb1= T_cb+ Tα so that the cable length is
Set. Therefore, the delay time of the third signal path 33 is t_Three+ T_Four
+ T_cb1+ T_FiveSet so that This delay time
Delay time t described in the prior art₁+ T _Two+ T_Three+ T_Four
+ T_Five+ 2t_cbThe value is about 1/2 compared to + tα.

Here, the second signal path 32 and the third signal path 33
Worst value t of variation in delay time between _cmax2Is t_cmax2= 0.2 (t_Three+ T_Four+ T_Five) +0.02 (t_cb+ T_cb1) + T_s + T_h ... (2)

The difference Δt _cmax between t _cmax1 and t _cmax2 = t
_{cmax1− tcmax2} is obtained. _{Δt cmax = {0.2t 1 +0.6 (} t 2 + t 3 + t 4 + t 5 + t dc) + 0.02 (2t cb) + t s + t h} - {0.2 (t 3 + t 4 + t 5) +0 .02 become _{(t cb + t cb1) +} t s + t h} = (0.2t 1 + 1.2t 2 + t 3 + t 4 + t 5 + 1.2t cb + 0.58tα). That is, according to the present invention, it can be seen that the worst value t _cmax2 of the variation of the delay time given to the second timing circuit 11 is smaller than the conventional worst value t _cmax1 by Δt _cmax .

[0019]

As described above, according to the present invention, the delay amount of the strobe pulse applied to the second timing circuit 11 can be reduced. As a result, the second timing circuit 11
, The worst value t _{cmax2 of the} deviation due to the variation in the delay time between the response output signal SOUT of the IC under test 21 and the strobe pulse STRB.

Therefore, the amount of deviation of the timing in the second timing circuit 11 can be reduced, so that when the user sets the cycle time T _c (see FIG. 3A),
The cycle time _Tc can also be set to a small value. That is, the allowable setting range of the cycle time _Tc can be extended to the shorter cycle side. Therefore, a high-speed test can be performed.

[Brief description of the drawings]

FIG. 1 is a connection diagram showing one embodiment of the present invention.

FIG. 2 is a connection diagram for explaining a conventional technique.

FIG. 3 is a connection diagram for explaining the operation of the conventional technique.

[Explanation of symbols]

 Reference Signs List 10 IC tester main body 11 Second timing circuit 12 Logical comparator 20 Test head 21 IC under test 22 First timing circuit 31 First signal path 32 Second signal path 33 Third signal path

Claims (1)

(57) [Claims] 1. A strobe pulse is applied from a main body of an IC tester to a first timing circuit provided in a test head through a first signal path, and a response output signal output from an IC under test is timed in the first timing circuit. The timed response output signal is provided to the IC tester main body through a second signal path.
An I signal having a structure for determining whether the IC under test is good or not by giving the signal timed by the second timed circuit 11 to a logical comparator.
In the C test apparatus, the strobe pulse given to the first timing circuit is sent back to the main body of the IC tester through a third signal path having a delay time equivalent to that of the second signal path. An IC test apparatus characterized in that it is configured to be timed by being given to a user.