JP2001266594A - Memory pause test circuit of semiconductor integrated circuit and test method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve such a problem that when memory macro-cells of various kinds incorporated in a semiconductor integrated circuit are tested and a pause test is performed, it takes a long time to perform testing successively. SOLUTION: There is a test method using a BIST circuit in a method for testing a memory macro-cell, but in order to perform efficiently and easily a pause test of many memory macro-cells incorporated in a semiconductor integrated circuit, such a circuit other than the BIST circuit is incorporated in the semiconductor integrated circuit that memory macro-cells of which address directions are the same are made a unit with which control is performed by the BIST, even if a time for writing a checker pattern in the memory macro- cell being timing of pause is different depending on BIST controllers, the circuit that makes the BIST controller wait until a checker patter is written in the BIST controller is mounted on the semiconductor integrated circuit in addition to the BIST controller.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test circuit and a test method for a semiconductor integrated circuit, and more particularly to a test circuit and a test method for simultaneously detecting faults in memories of different sizes mounted on a single semiconductor integrated circuit. is there.

[0002]

2. Description of the Related Art In recent years, semiconductor manufacturing technology has been remarkably miniaturized.
It has become possible to mount a large number of memories on one semiconductor integrated circuit device. As a memory means built in the integrated circuit, it is common to put each terminal of the built-in memory outside the integrated circuit, but there is a problem that the number of test terminals increases. On the other hand, BIST circuits that can determine the quality of a memory inside a semiconductor integrated circuit have been widely used.

The BIST circuit shown in FIG. 7 is as follows. The address generator operates as a kind of counter that can sequentially indicate the address of the memory macro cell. The pattern generation unit can automatically generate a test pattern. Since a pattern for testing a memory macro cell is regular, it can be automatically generated. The comparator determines whether the output result of the memory macro cell is correct. If an expected signal cannot be obtained from the memory macro cell, the comparator determines that the memory macro cell has failed. In addition, the controller is a state machine that controls them, and a series of these operations can verify the operation of the memory macro cell, which is the circuit under test, without inserting a pattern from outside the semiconductor integrated circuit. It can be done. FIG.
As shown in FIG. 1, a configuration of a BIST circuit that can simultaneously measure memories has been proposed.

[0004] Generally, a memory test consists of a march pattern,
It is known to use a checker pattern. This flow is shown in FIG.

[0005] The march pattern means that 0 is written to all addresses of the memory, 0 is read from the lower address of the memory,
Write 1 Next, an operation of reading out 1s in order and writing 0s is performed, and it is possible to screen for an address-related defect. As shown in FIG. 10, the checker pattern writes a value to all the memory cells of the memory so that cells adjacent in a checkered pattern always become 0 and 1, and reads the value. The positions of 0 and 1 are switched. Those are called the front pattern and the back pattern, respectively. The checker test can screen for short-circuiting or interference between memory cells. The pattern generator of the BIST circuit can automatically generate the march pattern and the checker pattern.

In the test of a memory macro cell, in order to further enhance the screening effect, a checker pattern is written to all the memory cells from the writing to the reading.
The clock supplied to the memory is stopped, and a pause test is performed.

The pause test is a test in which data is written to all addresses of a memory macro cell, a clock signal is stopped, and data is read again at a later time, and a test for guaranteeing that data is held for a long time. It is. In addition, when the data to be written to the memory macro cell is formed in a checker pattern, a defect that can be detected by the checker pattern becomes prominent, and is used for measuring a leak current. This pause test is performed twice when the front and back sides of the checker pattern are written.

[0008]

However, in the prior art, a BIST circuit capable of simultaneously testing a plurality of memories capable of executing a march pattern and a checker pattern has been provided in order to improve the efficiency of the memory test. If there are multiple memories with different memory addresses, the write time of the checker pattern in the memory will be different for each memory as shown in FIG. 11, and the pause test using the checker pattern cannot be performed at all. Would. In this case, the screening of the memory becomes insufficient in the inspection, and the defective chip is shipped as a non-defective product.

On the other hand, when a plurality of memories are not shared, a BIST circuit is provided for each memory, so that each BIST circuit can be independently controlled.

However, in this case, conventionally, when a pause test is to be performed on memories of various sizes mounted on a semiconductor integrated circuit, a method of sequentially executing the tests on each memory is a design. And the testing method is easy, but for one memory, 0.4
When a memory pause test that takes seconds takes place, the time required for inspection becomes very long, and costs are increased.

On the other hand, in this case, in order to simultaneously test memories having different sizes, the judgment at the end of the checker pattern is checked in advance by a preliminary simulation for each type of memory mounted on the semiconductor integrated circuit. In the test vector, where all the memories are in a state where the checker pattern is written, a state where the state of the memories can be paused simultaneously by the LSI tester must be created by a test pattern, which is very inefficient. When there are many types of memories, it is easy to make a mistake in creating a pattern.

[0012]

According to the present invention, a plurality of addresses using a BIST circuit are tested in different memory tests.
An object of the present invention is to provide a circuit and a method for easily performing a memory pause test.

First, the memory that shares the BIST circuit is limited to those having the same address direction. BIST
To share a circuit means to test a plurality of memory macro cells with one BIST circuit (constituted of an address generation unit, a pattern generation unit, and a result comparison unit).

As a result, the timing of the end of writing the checker pattern is uniquely determined by the BIST circuit. Even if the memory size is different, the same number of addresses (the memory size that can be stored per address is different) ) May share the BIST circuit, and therefore, depending on the configuration, an increase in the number of circuits by the BIST circuit can be suppressed as compared with the case where the BIST circuit is inserted into each memory macro cell. Each BIST circuit is provided with a hold mode in which the state of the circuit and the memory macro cell can be stopped with one signal. The hold mode is a mode in which the state of the flip-flop and the non-test memory in the BIST circuit is held.
This can be realized by stopping the clocks of the IST circuit and the non-test memory by applying a gate.

Second, in order to allow pauses at different check pattern writing timings to be paused at the same time, the BIST circuit for which the checker pattern writing has been completed first ends with the checker pattern writing last.
This is to make it wait until the IST circuit writes a pattern. At this time, the BIST circuit in which the checker pattern is written and the memory are stopped using the hold mode signal provided in each BIST circuit. Further, when the BIST circuit for testing the largest memory in the address direction mounted in the semiconductor integrated circuit comes to a standstill state, all the memories to be tested are ready to be paused. At this time, a signal indicating a state can be output outside the semiconductor integrated circuit.

In the test method, the test pattern can be created by minimizing the test mode switching and clock input only by mounting the test circuit inside.
Further, the memory is characterized in that the time for pausing the memory is also generated from the test circuit.

[0017]

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing the outline of the present invention. There is a BIST circuit 1 for inspecting a memory macro cell A to be inspected, and a BIST circuit 2 for inspecting a memory macro cell B to be inspected. At this time, there are a memory macro cell A to be inspected, a memory macro cell B to be inspected, and a memory macro cell C to be inspected, but one word (the number of bits that can be stored in one address) of the memory is different between the memory macro cells B and C. However, the size of the address is the same. Memory macro cell A is composed of memory macro cells B and C
And the address size is different. There may be any number of such combinations of the BIST circuit and the circuit under test in one semiconductor integrated circuit.

Reference numerals 3 and 4 denote hold signal generators for determining the quiescent state of each BIST circuit. Reference numerals 3 and 4 each include a counter 5, a comparator 6, and a hold signal control unit 7. The counter 5 has a configuration shown in detail in FIG. 3, and has a configuration in which an inverted signal of the most significant bit of the address generated by the address generation unit of the BIST circuit is input. Reference numeral 5 denotes a counter capable of counting the number of times that all addresses of the memory under test are accessed sequentially. The number of bits to be counted is determined as follows. For example, BIS
If the state of the test order of the T circuit is the state shown in FIG. 8, when the writing of the table of the checker board is completed, the uppermost bit signal of the memory address scans the entire address space of the memory from the start of the test. The number of times falls five times, which is the same as the number of times of writing, and falls seven times at the end of writing on the back of the checkerboard. In such a case, 5 is a counter of 3 bits or more. The bits of the counter are determined so that the number of times of falling of the upper-order bit of the address when the writing of the front and back of the checker board is completed can be counted.

The comparator 6 has a BIST circuit of interest.
This is a combinational circuit that outputs H when the writing of the checkerboard is completed, and is shown in detail in FIG.
The signal output from the comparator is sent to 7 so that each BIST controller is stopped when the checkerboard writing is completed.

The hold control unit 7 is a circuit for controlling the hold signal of the BIST controller, and is shown in detail in FIG. 7
For example, when the input signal 16 from the comparator changes from H to L when taking 3 as an example, the hold signal 18 as an output signal is initially H, but is changed from H to L. , The clock of each BIST controller and memory macro cell can be stopped. The clocks stopped at this time are only the BIST controller and the memory under test, and the clocks supplied to the 7 and 10 flip-flops are not stopped. The other input 20 of 7 is a hold control signal. This hold control signal is normally H
However, when the signal changes from H to L, the output signal 18
Does not cause any change, but when the hold control signal changes from L to H, the signal 18 can be changed from L to H, and the supply of clocks to the BIST controller and the memory macro cell can be restarted. The hold control signal generator 8 ORs the hold signals from all the hold signal generators mounted on the semiconductor integrated circuit by the OR gate 9. As a result, when all the hold signals have become L, the output of the OR gate 9 also becomes L and is passed to the OR 10 which generates a pulse for two clock times and the OR gate 11.

The hold control signal 20, which is the output of the hold signal generator 8, is normally H, but returns to H after generating a pulse that is L for two clock times after all the hold signals have gone L. Configuration. The signal 20 is output to the LSI tester using an external output pin of the semiconductor integrated circuit. When the pulse width of the L section for two clock times of the hold control signal is obtained, the clock can be stopped on the LSI tester side.

When the operation of the circuit of FIG. 1 is represented by a waveform, FIG.
become that way.

The waveform 21 represents the comparison result output 16 of the comparator of FIG. At the time of 26, all the memories A to be inspected in FIG. 1 have finished writing the checker pattern.
In response to the results of 5 and 6 in FIG. 1, the waveform of 21 changes from H to L. In response to this change, the hold signal having the waveform 22 falls from H to L. Next, 23 corresponding to the signal 17 in FIG. 1 has finished writing the checker pattern in the memory macro cell in FIG. In this case, the memory having the largest address size mounted in the semiconductor integrated circuit is the memory macro cell and the B memory.
Assume that the memories under test B and C in the IST circuit 2 (FIG. 1) are used. At this time, since the input of 9 in FIG.
The output of the R gate also falls to L, and the waveform 25, which is the signal 20 in FIG. 1, becomes L for two clocks and returns to H. The section where the waveform 25 is L is the section where all memories mounted on the semiconductor integrated circuit can be held. When the signal returns to H, the waveforms of 22 and 24 return to H by the operation of the hold control unit in FIG. 1, and the BIST circuit can automatically continue the test.

An actual test method can be performed as follows. This will be described with reference to FIG.

Reference numeral 42 denotes an LSI tester, and reference numeral 43 denotes a semiconductor integrated circuit. The operation performed by the LSI tester for the test switches the test mode / normal mode switching signal 45 to the test side, and sets the semiconductor integrated circuit including the circuit shown in FIG. Thereby, BI
When the output pin of the signal 47 indicating the failure result of ST and the output pin of the hold control signal 48 are also used for the normal mode,
These signals can be output outside the semiconductor integrated circuit. The BIST failure results of 47 are provided by the number of BIST controllers so that when the BIST controller outputs a failure, it is possible to determine which BIST controller is outputting the failure.

When the test mode is entered, the maximum address of the memory mounted on the semiconductor integrated circuit keeps adding a clock of a cycle obtained by adding four or more clock cycles to the clock cycle as much as possible for the test shown in FIG. To At this time, the hold release signal may change to L for two clock times. By stopping the supply of the clock of the LSI tester when the level becomes L, a pause test can be realized. The presence or absence of a memory macro cell failure can be determined when the expected value of the failure result of the 47 BIST does not match. As described above, since the test circuit is contained in the semiconductor integrated circuit, the test pattern is set to the test mode regardless of the number and type of the memory macro cells mounted on the semiconductor integrated circuit, the clock is continuously supplied, and the pause is performed. Since a point to be indicated is also indicated by a signal from the semiconductor integrated circuit, the test can be performed very easily.

By performing this test at the lower limit of the power supply voltage guaranteed for the product of the semiconductor integrated circuit, data retention of the memory at a low voltage can be performed for all the mounted memories.

Further, by performing this test when the power supply voltage is at the maximum and the temperature is at the upper limit of the product guarantee of the semiconductor integrated circuit, it is possible to measure the total leak current of the transistors of the memory cell.

Further, since the test circuit shown in FIG. 1 is a synchronous circuit operated by the supplied clock, it is possible to easily detect a failure of the test circuit itself by inserting a scan chain.

[0031]

According to the present method, in a semiconductor integrated circuit in which a large number of memories having different sizes are mounted, such as in a case where a large-scale system is housed in one semiconductor integrated circuit, the memory pause test can be performed on all the memories simultaneously. This can be performed on the memory, and the test time can be shortened, which leads to a reduction in cost.

Further, since a circuit for detecting a pause portion for performing a memory pause test is incorporated in the semiconductor integrated circuit, the test vector can be easily created, and the man-hour and labor for creating the test vector are omitted. Can be easily tested.

Further, since the built-in circuit is small in scale in which the conventional BIST circuit is loaded, it is possible to minimize an increase in circuit scale and an increase in design cost.

[Brief description of the drawings]

FIG. 1 is a diagram schematically illustrating a test circuit according to the present invention.

FIG. 2 is a diagram showing signals in a test circuit of the present invention.

FIG. 3 is a diagram illustrating a counter circuit.

FIG. 4 is a diagram showing a comparator.

FIG. 5 is a configuration diagram of a hold control unit.

FIG. 6 is a diagram showing a mechanism of a test method.

FIG. 7 is a diagram showing a conventional BIST circuit.

FIG. 8 is a diagram illustrating a state of simultaneous measurement of memories in a conventional BIST circuit.

FIG. 9 is a test flowchart of a memory macro cell.

FIG. 10 is a diagram showing a checkerboard.

FIG. 11 is a diagram showing a state of writing a checker pattern in a memory according to a conventional technique.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Memory macro cell and BIST circuit 2 Another memory macro cell and BIST circuit 3 Hold signal generation part 4 Another hold signal generation part 5 Counter 6 Comparator 7 Hold control part 8 Hold control signal generation part 9 OR gate 10 Flip-flop x2 11 One side Is a negative input OR gate 12 Upper-order bit signal of address of BIST circuit 13 Upper-order bit signal of address of another BIST circuit 14 Counter output 15 Output of another counter 16 Comparison result 17 Another comparison result 18 Hold signal 19 Another hold signal 20 Hold control signal 21 Waveform of signal 16 of FIG. 1 22 Waveform of signal 18 of FIG. 1 23 Waveform of signal 17 of FIG. 1 24 Waveform of signal 19 of FIG. 1 25 Waveform of signal 20 of FIG. BIST circuit of 1 in 1 writes checker pattern The time when the BIST circuit of FIG. 1 finishes writing the checker pattern 27 The time when the hold is released after two clock times of 27 27 The time when the BIST circuit of FIG. 1 finishes reading the checker pattern 30 The time when the BIST circuit of 1 and 2 has finished reading the checker pattern 31 clock signal 32 reset signal 33 most significant bit of memory address 34 inverter 35 n-bit counter 36 output of counter 37 signal from counter 38 comparator body 39 comparison Result signal 40 Input from comparator 41 Hold control signal 42 LSI tester 43 Semiconductor integrated circuit 44 Circuit shown in FIG. 1 45 Test mode / normal mode switching signal 46 Clock signal 47 BIST failure result signal 48 Hold system Your signal

Continued on front page F term (reference) 2G032 AA07 AC08 AC10 AD01 AE08 AE11 AG02 AG07 AK16 AK19 AL14 5B018 GA03 HA31 JA12 JA23 MA31 NA10 PA03 QA13 5B048 AA19 CC02 CC18 DD05 FF01 5L106 DD03 DD08 DD22 DD23 GG03 BB06 BB06 BB06

Claims (6)

[Claims] In a semiconductor integrated circuit having a plurality of memory macro cells having different configurations, an address generation and a test pattern of the memory macro cell are automatically generated and used as an input of the memory macro cell, and data read from the memory macro cell and expected data are obtained. When a BIST circuit is inserted into each memory macro cell in the BIST test for comparing the values inside the semiconductor integrated circuit, only those having the same size in the address direction of the memory macro cells are placed adjacent to each other on the semiconductor integrated circuit. A memory pause test circuit for a semiconductor integrated circuit, comprising: 2. A BIST circuit of a first memory macro cell in which a pattern has been written first and a checker pattern have been written last so that BIST circuits of a plurality of memory macro cells having different sizes in the address direction are almost simultaneously stopped. 2. The semiconductor integrated circuit according to claim 1, further comprising a circuit for controlling the second memory macro cell to wait until the second memory macro cell comes to a stationary state, and outputting a signal to notify the LSI tester of the time. Circuit memory pause test circuit. 3. A clock signal is input from an LSI tester, a failure of the memory is determined inside the circuit, and the clock signal is stopped at a point where all the non-inspection memories have written the checker pattern, so that the circuit is mounted on the semiconductor integrated circuit. Test method for testing a memory macro cell. 4. The test according to claim 3, wherein a pause test of whether or not the data of the memory macro cell can be held at the time of low voltage is simultaneously performed on all the memory macro cells mounted on one semiconductor integrated circuit. Method. 5. A test method for testing a memory cell as a circuit under test, wherein a leakage current of a transistor in the memory macro cell is simultaneously measured for all the memory macro cells mounted on one semiconductor integrated circuit. 4. The test method according to claim 3, wherein the test is performed. 6. The test circuit according to claim 2, wherein the synchronous circuit is capable of easily detecting a failure of the test circuit itself by inserting a scan chain.