JPH0454472A - Semiconductor testing device - Google Patents

Abstract

PURPOSE:To easily conduct an efficient test without any waste by providing a 1st, a 2nd, and a 3rd storage means with write instructions for the number of parallel measurements and the specific number of terminals to be tested as test program header information. CONSTITUTION:A register circuit 36 is provided and terminal output decision signals Sj outputted from a pin cathode 35 are stored in FFs 36-1 - 36-n individually. A test program stored in a memory 31 is provided with the write instructions for the number of parallel measurements and the specific number of terminals to be tested as the test program header information, thereby storing the number of parallel measurements in a register 37 and the specific number of terminals to be tested in a register 38 with the respective write instructions. It can be judged from the information in the registers 37 and 38 which of devices 41-1 - 41-5 individual terminal output decision signals Sj in the register circuit 36 correspond to and the contents of the register circuit 36 are read out in measurement item units to test and decide the respective object devices 41-1 - 41-5.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to the structure of a semiconductor testing device for testing the electrical characteristics of a semiconductor device.

(Prior Art) Conventionally, such semiconductor test equipment has a device under test (D
There are devices that can measure only one UT> at a time and do not have a parallel measurement function, and devices that have a parallel measurement function for up to two devices under test. This semiconductor test equipment that can perform parallel measurements on up to two devices under test has an operation system (○, S ), and the test results (PASS, FAIL) of the device under test are determined by the operation system. Examples of the configuration are shown in FIGS. 2 and 3.

FIG. 2 is a block diagram of the configuration of a conventional semiconductor testing device, and FIG. 3 is a circuit diagram of the pin circuit in FIG.

This semiconductor test equipment has a two-parallel measurement function, and uses, for example, input terminal IN, output terminal ○UTI, 0UT2, and power supply terminal POWER as terminals to be tested, and electrically conducts electrical tests on the devices under test 1 and 2 that each has. It performs a test by measurement to determine pass/fail, and includes a memory 11, a control unit 12, a pattern generator 13, power supply circuits 14 and 15, registers 16 and 17, and pins that are connected to each other via a data bus N1. It has a card 18 and has OR circuits 19 and 20 connected between the register 16 and the pin card 18, respectively.

The memory 11 has a function of storing a test program for the device under test 1.2.

The control unit 12 controls the execution of a test on the device under test 1.2 based on the test program stored in the memory 11, and outputs a predetermined control signal S1. ) etc.

The pattern generator 13 generates an input test pattern AI set in advance at a predetermined timing using a control signal S1.
, an expected output value test pattern L1, and an expected output value check strobe M1.

Power supply diagram Ji@14.15 is the device under test 1゜2, respectively.
This is a circuit for supplying power to the devices, and each has a current measurement circuit inside.

The registers 16 and 17 have a function of holding data at a predetermined timing using the output expected value check strobe M1.

The pin card 18 includes, for example, 128 pin circuits 18-1.
~18-128, and the configuration of each pin circuit is, for example, as shown in FIG. 3, an input driver circuit 18a,
Output comparator circuit 18b, exclusive OR (hereinafter referred to as F
It consists of a gate 18c (referred to as OR), a switch 18d whose switching is controlled by a control signal S1, and a test pin 18e. Here, the input driver times F418 a
The output comparator 18b converts the voltage level based on the reference voltages VIO and VO2, respectively, in response to switching of the switch 18d. Input driver circuit 1
The input test pattern A1 is connected to the input side of 8a together with the reference voltage ■o1. Also, EOR gate 18
The input of c (Jl!14) is connected to the output expected value test pattern L1 as well as the output of the output comparator 18b.

The OR gate 19 has pin circuits 18-1 to 1 based on its human power.
The outputs of each EOR gate 18c of 18-64 are connected. In addition, the OR gate 20 is connected to each EOR gate 18 of the pin times JiJ18-65 to 18-128 according to the person's law.
The output of c is connected.

Next, the operation when testing the device under test 1.2 using the semiconductor test apparatus configured as described above will be described.

First, the device under test 1.2 is set in the semiconductor test equipment. That is, the input terminal IN of the device under test 1 is connected to the pin circuit 18-
1 test pin 18e, output terminal 0UTI, 0
Connect UT2 to the test pin 18e of pin circuits 18-2 and 18-64, respectively, and connect the power supply terminal POWER.
is connected to the power supply circuit 14. Similarly, the device under test 2
Connect the input terminal IN to the test pin 18 of the pin circuit 18-65.
Connect output terminals 0UTI and 0UT2 to test pin 18e of pin circuits 18-66 and 18-128, respectively.
and connect the power supply terminal POWER to the power supply circuit 15.
Connect to.

Next, when the control unit 12 loads the test program stored in the memory 11, a predetermined power supply voltage is applied to the power supply terminal POWER of the device under test 1.2 according to the power supply diagram B14-15.
is input. Further, the input test pattern A1 is generated by the pattern generator 13, and the input test pattern A1 is inputted to the pin circuit B18-1, 18-65, and voltage level converted by the respective input driver circuit 18a. The signals are respectively input as signals Sin to the input terminals IN of the device under test 1.2. By inputting the input signal Sin, the devices under test 1 and 2 perform a predetermined function and output terminals 0UTI and 0UT2, respectively.
The output signal 5 outl.

Outputs 5out2.

The output signal 5outl of each device under test 1, 2 is output from the output comparator 1 of pin circuit & J18-2.18-66, respectively.
8b to the EOR gate 18c, and the output signal 5out2 of each device under test 1.2 is input to the pin circuit H
@1B-64, 18-128 output comparator 18b
The signal is input to the EOR gate 18c via the EOR gate 18c. At this time, from the pattern generator 13, the pin circuit 18-2.18
The expected output value test pattern L1 is output to the EOR gate 18c of -66 and the EOR gate 18C of pin circuit 18-64°18 to 128, respectively.

Pin circuit 118-2.18-66 and pin circuit 1864.1
Each EOR gate 18c of 8-128 is connected to the device under test 1.
The output signals 5outl and 5out2 from 2 and the corresponding output expected value test patterns L1 are compared, and the comparison results are used as terminal output determination signals Sj1 to Sj1.
Output as j4. Here, for example, by appropriately setting the input test pattern A1, if the device under test 1.2 is a good product, the output signals 5outl and 5out2 will be at a high level, and the corresponding output expected value test pattern L1 will be at a high level. Set it so that Therefore, if the outputs of the output signals 5outl and 5out2 are normal, each terminal output determination signal Sjl to Sj4 becomes low level.

Furthermore, the terminal output determination signal Sj1. Sj2 is input to the OR gate 19, and terminal output determination signals Sj3 and Sj4 are input to O
The signal is input to the R gate 20. Furthermore, OR gate 19.
The output of 20 is the expected value check strobe M1 output from the pattern generator 13 based on the control signal S1.
registers 16 and 17 at predetermined timing.
The outputs of the registers 16 and 17 are used to determine whether the device under test 1.2 is good or bad.

That is, when the output level of the registers 16 and 17 is low level, it is determined that the product is good (PASS), and when it is high level, it is determined that the product is defective (FAIL).

Here, the current measurement circuit in the power supply circuit 14.15 performs current measurement for each power supply terminal POWER of the device under test 1.2, and data based on the measurement is transmitted to the device under test 1.
．． It is added as a material for determining the quality of item 2.

(Problems to be Solved by the Invention) However, the semiconductor test device having the above configuration has the following problems.

In conventional semiconductor test equipment, pin circuits 18-1 to 18-
Divide 128 into two and create pin circuits 18-11 to 18-64
and pin circuits 18-65 to 18-128, respectively, are assigned to one device under test and tested by electrical measurements, etc., so a predetermined number of parallel measurements can be achieved. That is, the number of devices under test that can be measured at one time is, for example, two. Therefore, even when the number of test terminals of a device under test is small, the number of devices under test that can be measured in parallel is two, and parallel measurement of three or more devices cannot be performed.

Therefore, in order to increase the number of devices under test that can be measured in parallel, the pin circuits 18-11 to 18-128 were divided into N (N
22) It is possible to do so. However, as the number of divisions N increases, the number of parallel measurements can be increased, but the permissible number of terminals under test of the device under test decreases, and the types of devices under test that can be measured are limited.

The present invention provides a semiconductor testing apparatus that solves the problem of the prior art in that the number of measurable devices under test that can be measured in parallel and the number of terminals under test are fixed.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides a memory that stores a test program for a device under test having a plurality of terminals under test, and a memory that stores a test program for a device under test having a plurality of terminals under test, and a memory that stores a test program for a device under test having a plurality of terminals under test. a pattern generator that generates a test pattern based on the control signal; and a terminal output determination device that outputs a terminal output determination signal for each output signal based on the output signal of the device under test that corresponds to the test pattern. The present invention provides a semiconductor testing apparatus which includes a circuit and which determines whether the device under test is good or bad based on the terminal output determination signal, which takes the following measures.

That is, a write command for the number of parallel measurements of the device under test and a write command for a predetermined number of test target terminals among the plurality of test target terminals are stored in the memory as test program header information, and the respective terminal output determination signals are stored in the memory as test program header information. a first storage means for storing the number of parallel measurement terminals of the device under test based on the write instruction for the number of parallel measurement terminals, and a second storage means for storing the number of parallel measurement terminals for the device under test based on the write instruction for the predetermined number of terminals to be tested. and third storage means for storing the predetermined number of terminals to be tested.

(Function) According to the present invention, since the semiconductor testing apparatus is configured as described above, the device under test is stored in the second storage means based on a write command for the number of parallel measurements stored as test program header information. The number of parallel measurements is written th.

Furthermore, the predetermined number of terminals to be tested is written into the third storage means based on the write command for the predetermined number of terminals to be tested. Here, the predetermined terminal to be tested R is defined, for example, by the number of terminals to be tested that are connected to the terminal output determination circuit among the plurality of terminals to be tested.

When a test pattern generated by the pattern generator is input to the device under test and an output signal corresponding to the test pattern is output from one of the terminals under test, the terminal output determination circuit determines whether the output signal is A determination is made on each output signal for each terminal to be tested, and a terminal output determination signal is output for each terminal to be tested, that is, for each output signal. These terminal output determination signals are individually stored in the first storage means.

As a result, the control unit etc. can store h h in each of the first storage means, for example, based on the information on the number of parallel measurements and the predetermined number of terminals to be tested stored in the second and third storage means. The quality of the device under test is determined by evaluating the stored terminal output determination signals.

Therefore, the above problem can be solved.

(Embodiment) FIG. 1 is a schematic block diagram of a semiconductor testing apparatus showing an embodiment of the present invention.

This semiconductor test equipment performs electrical measurements on a device under test that has multiple terminals under test, tests each device under test for each measurement item, and determines the acceptability of each device under test. data bus Ni
A memory 31, a control unit 32, and a control unit 32 connected to each other by
Pattern generator 33, power supply circuits 34-1 to 34-
5. It has a pin card 35 which is a terminal output determination circuit, a register circuit 36 which is a first storage means, a register 37 which is a second storage means, and a register 38 which is a third storage means.

The memory 31 has a function of storing, as test program header information, a test program provided with write commands for the number of devices to be tested in parallel and a predetermined number of terminals to be tested, and is constituted by, for example, a RAM or the like.

The control unit 32 executes the test program in the memory 31 and outputs a predetermined control signal Sll to each unit, thereby
It has a function of controlling a test that performs electrical measurements on the devices under test 41-1 to 41-5 and determines their pass/fail.
It is made up of etc.

The pattern generator 33 is, for example, a pattern generator h7' created in advance.
, - Input test pattern Al l whose timing information such as output timing is controlled based on the control signal S11 by the pattern program, Expected value test pattern L
11 and an expected value check strobe Mll.

Power diagram! ! ! 434-1 to 34-5 are each equipped with a current measurement circuit, etc., and the power supply information is controlled by the control signal Sll, and they supply power to the device under test and control the current flowing through the device under test. It has the function of performing measurements, etc.

The pin card 35 is composed of a plurality of pin circuits 35-1 to 35-n whose pin card information such as switching modes of each part is controlled by a control signal Sll based on a test program. Each of the pin circuits 35-1 to 35-n is
For example, it is configured in the same way as the pin circuit in FIG. 3, and is in an input driver mode in which input test patterns All are output to the device under test as input signals Sin based on the control signal Sll, or in an input driver mode in which the output signal 5out from the device under test is output. The switch 18e switches to an output comparator mode in which the output signal 5o is input, and in the case of the output comparator mode, the output signal 5o
It has a function of determining whether or not the output of the output signal 5out is normal by comparing ut with the expected output value test pattern Lll, and outputting the determination result as the terminal output determination signal Sj.

The register circuit 36 includes, for example, a plurality of flip-flops 3.
6-1 to 36-n, each flip-flop 36
-1 to 36-n, each terminal output determination signal Sj of each pin circuit 35-1 to 35-n is input, and the output of each flip-flop 36-1 to 36-n is input to the pattern generator 33. Each of them is latched at a predetermined timing by an output expected value check strobe Mll.

The register 37 is configured using, for example, a plurality of flip-flops, and has a function of storing the number of parallel measurements of the device under test under the control of the control unit 32 based on a write command for the number of parallel measurements stored in the memory 31. ing.

The register 38 is configured using, for example, a plurality of flip-flops, and stores the number of terminals to be tested of the device under test under the control of the control unit 32 based on a write instruction for a predetermined number of terminals to be tested stored in the memory 31. It has a function.

The operation will be described when, for example, a test is performed on five devices under test 41-1 to 41-5 in parallel using the semiconductor test apparatus configured as described above. Here, the devices under test 41-1 to 41-5 each have a power terminal PO.
It has WER, a ground terminal GND, an input terminal IN, and output terminals 0UTI and 0UT2.

First, each ground terminal GND of each device under test 41-1 to 41-5 is grounded, and the power supply terminal POW is connected as the terminal under test.
4 of ER1 input terminal IN and output terminal 0UT10UT2
Set the pin. Next, the devices under test 41-1 to 41-5
Each power supply terminal p.

WER are connected to the power supply circuits 34-1 to 34-5, respectively, and each input terminal IN of the test equipment 41-1 to 41-5 is connected to the pin circuit 35-1.35-4゜35-7.35-1, respectively.
0.35-13 each test and connect to pin 18e. Furthermore, each output terminal 0UTI of the devices under test 441 to 44-5
are pin circuits 35-2.35-5.35-8., respectively.
35-11. Connect to each test pin 18e of 35-14, and each output terminal 0UT2 is connected to each pin circuit 35-3.
35-6.35-9.35-12.35-15 to each test pin 18e.

Here, the number of terminals to be tested for each of the devices under test 41-1 to 41-5 is r4. However, among these, the number r of input terminals IN and output terminals 0UTI and 0UT2, which are the terminals under test, connected to the pin card 35, which is the terminal output determination circuit.
3. is set as the predetermined number m2 of terminals to be tested.

Further, a test program is stored in the memory 31 in advance, and the test program is provided with a write command for the number of parallel measurements and a write command for a predetermined number of terminals to be tested as test program header information.

Thereafter, under the control of the control unit 32, the test programs in the memory 31 test the devices under test 411 to 41-5 as follows.

First, a control signal Sll is output from the control unit 32, and based on the control signal Sll, the parallel measurement number ml (in this embodiment, "5'') is written into the register 38, and a predetermined number m2 of terminals to be tested (in this embodiment, ``3'') is written into the register 38. Each power supply times! ! l34-1~3
4-5, power is supplied to each power terminal POWER of the devices under test 41-1 to 41-5, and the pattern generator 33 outputs input test patterns All.

This input test pattern All is set to pin circuit 3 in input driver mode by a preset pattern program.
5-1.35-4.35-7.35=10.35-13
is input. Then, pin circuit 35-1.35-4.
35-7.35-10゜35-13 respectively input the same input test pattern All, and input the input test pattern All to the input signal Sin having a voltage level suitable for the devices under test 41-1 to 41-5. The signals are converted and output to the input terminals IN of the devices under test 41-1 to 41-5, respectively.

Each device under test 41-1 to 41 to which input signal Sin was input
-5 each fulfill a predetermined function, and each output terminal ○U
Output the output signal 5outl from TI, and connect each output terminal 0U
Output signal Sout2 is output from T2. These output signals 5outl and 5put2 are output comparator mode pin numbers n35-2.35-5.35-8, respectively.
．． 3511.35-14 and output comparator mode pin circuit 35-3.35-6.35-9.3512.3
5-15.

Each output signal is 5 outl or 5 outZ! In each pin circuit that inputs
8b performs a predetermined voltage level conversion, and its output signal 5outl or 5out2 is input to each EOR gate 18c. At this time, each EOR gate 18c
In addition to the output signal 5outl or 5out2, an expected value test pattern Lll corresponding to the inputted output signal 5outl or 5out2, respectively, is input. This allows each pin circuit 35-2.35-3.35-5.
35-6.35-8.35-9゜35-11.35-1
2.35-14. Terminal output determination signals Sj 11 to 5j20 are output to the register circuit 36 from 35-15, respectively.

In 22, the terminal output judgment signals Sj 11 to 5j20 are set, for example, by input test patterns Al1, etc., so that the respective output signals 5outl and 5out2 are at a high level when the devices under test 41-1 to 41-5 are non-defective. Therefore, by setting the corresponding expected value test pattern Lll to a high level, the devices under test 41-1 to 4
If 1-5 is normal, it becomes a low level.

The flip-flops 36-2 .
36-3.36-5.36-6゜36-8.36-9.
36-11.36-1236-14.36-15 latches each terminal output determination signal 5jll to 5j20 at a predetermined timing based on the expected value check strobe Mll from the pattern generator 33. Each flip-flop 36-2.36-3.36-5°36-
6.36-8.36-9.36-11.36-12.3
6-14. By reading each output of 36-15 from the control unit 32 for each measurement item via the data bus Nil,
Test judgment is performed for each device under test '1141 1 to 41-5. At this time, the control unit 32 controls the flip-flops 36-2.36 based on the information on the number of parallel measurements and the predetermined number of terminals to be tested stored in the registers 37.38.
The output of -3 is determined to be test data for the device under test 31-1, and flip-flops 36-5, 36-6, flip-flops 36-8, 36-9, and flip-flops 3
6-11.36-12, and flip-flop 36-1
4. Even with the output of 36-15, each device under test 4
1-2, 413.41-4.41-5, and parallel measurement result processing is executed.

In addition, for tests related to the power supply of the devices under test 41-1 to 41-5, for example, the control unit 32
The output of the current measurement circuit provided in 34-5 is connected to the data bus Ni.
This is done by reading through l. In this way, a test judgment can be performed for each device under test 41-1 to 41-5, and a judgment is made as to whether it is a good product (PASS) or a defective product (FAIL).

This embodiment has the following advantages.

That is, in this embodiment, since the register circuit 36 is provided,
The terminal output determination signal Sj output from the pin card 35 can be individually stored in each of the flip-flops 36-1 to 36-n. Furthermore, since the test program stored in the memory 31 is provided with a write instruction for the number of parallel measurements and a predetermined number of terminals to be tested as test program header information, and registers 37 and 38 are provided, each write instruction causes the register 37 to be used for parallel measurement. A predetermined number of terminals to be tested can be stored in the register 38.

Therefore, it is possible to determine which of the devices under test 41-1 to 41-5 each terminal output determination signal Sj in the register circuit 36 belongs to based on the information in the registers 37 and 38, and registers for each measurement item can be determined. By reading the contents of the time 2836, a test determination can be made for each of the devices under test 41-1 to 41-5.

Therefore, within the range of the number of pins 2435-1 to 35-n, that is, the number of test pins n of the pin card 35, n≧ml(
ml and m2 can be set in any combination that satisfies the condition of (number of parallel measurement terminals) Xm2 (predetermined number of terminals to be tested). Therefore, with the semiconductor testing apparatus of this embodiment, it is possible to easily conduct an efficient test without waste.

Note that the present invention is not limited to the illustrated embodiment, and various modifications are possible. Examples of such modifications include the following.

(A) The semiconductor testing device of the above embodiment has a pin card 35.
It is also possible to change the configuration of the register circuit 36 and the like. For example, the configuration of the pin circuit illustrated in FIG. 3 may be changed for the pin card 35. Further, the pin card 35 may have a configuration in which each of the pin circuits 35-1 to 35-n is provided with another circuit, for example, a power supply circuit including a current measurement circuit. In that case, the switching of the switch 18e is increased and the switching is controlled by the control signal Sll, and each pin circuit 3
The functions of 5-1 to 35-0 may be configured to be switched to output the input signal Si, input the output signal 5outl or 1iSout2, or supply power. Further, in accordance with the change, the predetermined number m2 of terminals to be tested stored in the register 38 is also changed to, for example, four.

Furthermore, the pin card 35 is configured by providing an EOR gate L8c for outputting a terminal output determination signal Sj corresponding to the output signal 5out, an input driver circuit ¥418a and an output comparator 18b, but these are A configuration may be adopted in which each is provided individually. Further, as means for outputting the terminal output determination signal Sj, the EOR gate 1
A configuration other than using 8c may be used.

(B) In the above embodiment, the case where the number of parallel measurement m1 is 5 and the predetermined number of terminals to be tested m2 is 3 is explained.
The number of parallel measurements m1 and the predetermined number of terminals to be tested m2 can be changed in any combination within the range of mlXm2≦n. Accordingly, the contents of each write command provided in the memory 31 as test program header information are also changed as appropriate.

(C) In the above embodiment, the pattern generator 33
The output of the input test pattern A11, the output expected value test pattern L11, and the output expected value check strobe Mll may be set to be performed based on the information l: in the registers 37 and 38.

(D) In the above embodiment, the register circuit 36 and the register 37.3 are the first, second and third storage means, respectively.
Although a case has been described where 8 is configured with flip-flops, these may be configured using something other than flip-flops. Furthermore, means other than registers may be used as the first, second, and third storage means. Also,
Depending on the changes in the first, second, and third storage means, the method of outputting the expected value check strobe Mll and the control unit 32
The method of reading out the terminal output determination signal Sj may be configured using a method other than the above embodiment.

(E) Various changes can be made to the test methods exemplified in the above examples. For example, output signal 5Outl, 5o
Settings of logic levels of ut2, expected output value test pattern Lll, terminal output determination signal Sj, etc. can be changed as appropriate.

(Effects of the Invention) As explained in detail above, according to the present invention, the first
, second and third storage means are provided, and write commands for the number of parallel measurements and a predetermined number of terminals to be tested are provided in the memory as test program header information. Based on the information stored in the storage means, one of the terminal output determination signals stored in the first storage means outputted from each device under test can be determined and read out.

Therefore, in the semiconductor testing apparatus of this embodiment, the number of devices under test to be measured in parallel and the predetermined number of terminals to be tested can be arbitrarily set within a predetermined range. Tests on test equipment can be easily performed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the configuration of a semiconductor testing device showing an embodiment of the present invention, FIG. 2 is a block diagram of the configuration of a conventional semiconductor testing device, and FIG. 3 is a circuit block diagram of the pin circuit in FIG. 2. . 31...Memory, 32...Control unit, 33...Pattern generator, 35...Pin card, 36...
Register circuit, 37.38...Register, 41-1~
41-5...Device under test, Sll...Control signal, A
ll...Input test pattern, Sin...Input signal, Soυtl, 5out2-=-output signal, 5jll~
5j20...Terminal output judgment signal.

Claims (1)

[Scope of Claims] A memory that stores a test program for a device under test having a plurality of terminals under test; a control unit that outputs a predetermined control signal based on the test program; and a test pattern generated based on the control signal. a pattern generator that outputs a terminal output determination signal for each output signal based on an output signal of the device under test according to the test pattern, and a terminal output determination circuit that outputs a terminal output determination signal for each output signal, and In a semiconductor test device that determines the quality of a test device, a write command for the number of parallel measurement of the device under test and a write command for a predetermined number of test target terminals among the plurality of test target terminals are written in the memory as test program header information. a first storage means for storing each terminal output determination signal, and a second storage means for storing the number of parallel measurements of the device under test based on the write command for the number of parallel measurements; a third storage means for storing the predetermined number of terminals to be tested based on a write command for the number of terminals to be tested.