JP2005181060A - Inspection device and inspection method of ic - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inspection device and an inspection method of an IC applicable for mass production inspection, wherein the inspection time per IC is shortened and a large quantity of IC's are inspected in a short time. <P>SOLUTION: This inspection device of the IC comprises a host control device 1 and an inspection device body 10. The inside of the inspection device body 10 includes a device 2 for each pin for applying and measuring a signal individually, relative to each pin in the inspection IC, and is controlled from the host control device 1 by a control bus 6. Data in a condition setting/determination value memory 3 are distributed to a signal source of the device 2 for each pin and a determination circuit 4 via a route a and a route c; and a measured value from a measuring device of the device 2 for each pin is introduced to the determination circuit 4 via a route b, and is determined in the determination circuit 4, in reference to a specified value given from the route c. Each condition setting/determination value memory 3 outputs stored data by an order from a simultaneous memory selection bus 7. The result of the determination circuit 4 is connected to a base of a transistor 5 through a route d, and a collector is connected to a common simultaneous determination bus 8, to thereby constitute a wired NOR circuit. The circuit is controlled or referred to, via the simultaneous memory selection bus 7 and the simultaneous determination bus 8. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to inspection of electrical characteristics and the like performed before shipment of an IC (semiconductor integrated circuit), and more particularly to an IC inspection apparatus and inspection method with reduced inspection time.

  Generally, an IC is inspected for electrical characteristics before shipping. Although this inspection depends on the scale of the IC, the contents of several hundred items are usually executed in series, and if a defect occurs in any item, the IC is determined to be defective. FIG. 9 shows a schematic block diagram of the IC inspection system. In FIG. 9, 1 is a host control device that controls the IC inspection system, 10 is an inspection device body, 14 is an inspection board, and 13 is an IC to be inspected. In the inspection apparatus main body 10, each pin device 2 capable of separately applying a signal to and measuring each pin of the IC 13 to be inspected is built in, and from each pin device 2 through a measurement signal transmission path 15. It is connected to the inspection board 14 and finally reaches each pin of the IC 13 to be inspected through the pattern of the inspection board 14.

  The number of devices for each pin is prepared for the number of IC pins, and is currently 100 to 500 in a standard configuration. Each pin device 2 is controlled by the host controller 1 through the control bus 6. The host control device 1 is a computer and is a little away from the inspection device body 10. If a system having such a basic configuration is used, it is possible to inspect ICs having different functions by changing the program of the host controller 1. In addition, on the inspection board 14, other peripheral components of the IC to be inspected and relays for changing peripheral conditions are often mounted.

  Next, the contents of each pin device 2 will be described in detail with reference to the example of the principle diagram of the signal source / measuring device shown in FIG. In this example, a device for performing a direct current inspection on one pin of the IC 13 to be inspected is shown. In FIG. 10, 21 is a variable voltage source, 22 is a variable current source, 23 is an ammeter, 24 is a voltmeter, and 25 is an operation mode changeover switch.

  In the example shown in FIG. 10, the voltage source mode is selected. In this case, a predetermined voltage can be applied to pin 1 of IC 13 to be inspected, and the current flowing therethrough can be inspected. An example of the inspection includes a power supply current inspection. When the operation mode changeover switch 25 is switched to the other, the current source mode is selected. In this case, it is possible to inspect the voltage generated by applying a predetermined current to the pin 1 of the IC 13 to be inspected. An example of the inspection is an impedance inspection. Further, by opening the output switch 26, it is possible to have no influence on one pin of the IC 13 to be inspected. Each of the pin devices 2 is configured with the above-described functions.

  FIG. 11 is a block diagram showing a schematic configuration of a conventional IC inspection apparatus. In FIG. 11, 1 is a host control device, and 10 is an inspection device body. In the inspection apparatus main body 10, each pin apparatus 2 capable of separately applying a signal to and measuring each pin of the IC to be inspected is incorporated, and the number of each pin apparatus is prepared by the number of IC pins. Each pin device 2 is controlled by the host control device 1 through the control bus 6.

  Actually, as described in the IC inspection system shown in FIG. 9, the signal source and measuring device output of each pin device 2 are connected to the inspection board 14 via the measurement signal transmission path 15, and the pattern of the inspection board 14 is changed. This finally reaches each pin of the IC 13 to be inspected, but this route is omitted in FIG.

  In the conventional example of the IC inspection system having such a configuration, the host control device 1 performs control using the control bus 6 in order to control each pin device 2 as shown in FIG. This is generally performed via a control bus since the number of pin devices 2 is as large as 100 to 500.

  However, in order to set the condition of the signal source of each pin device 2 and to control the measuring device, the device must be sequentially operated from the 1-pin device to the N-pin device. The operation will be described with reference to FIG. As shown in FIG. 12, when one inspection item is divided along the time axis, the first is the condition setting, the second is the response waiting time waiting for the response of the IC to be inspected, the third is the measurement, and the fourth is the order of determination. It becomes.

  Here, paying attention to the first condition setting, it is necessary to carry out in order from the 1-pin device to the N-pin device until the setting of all pin conditions is completed. If attention is paid to the third measurement, as in the condition setting, the measurement from the 1-pin device to the N-pin device must be performed in order until the measurement of all pins is completed. Each of the setting time and measuring time of each pin is as short as several hundred μs. However, if 100 to 500, which is a few minutes of each pin device 2, is performed at once, the time for setting and measuring each time is about 40 ms. Necessary. Considering that the response waiting time of the IC to be inspected is short and within 5 ms, 90% or more of the inspection time of one item is spent for controlling each pin device 2. Although the inspection depends on the scale of the IC, there is a problem that a long inspection time is required because the contents of several hundred items are usually executed in series.

  The present invention is directed to solving the above-described problems of the prior art. A condition setting / determination value memory and a determination circuit are added to each pin device, and a simultaneous memory selection bus, It is an object of the present invention to provide an IC inspection apparatus and inspection method that reduce the inspection time using a determination bus.

  In order to achieve this object, an IC inspection apparatus according to the present invention is an IC inspection apparatus that continuously performs a plurality of inspections with different contents on an IC to be inspected. It is equipped with a simultaneous control means for setting the conditions of each pin device and a simultaneous control means for measuring each pin device, and each inspection item is inspected by both the simultaneous control means for setting conditions and the simultaneous control means for measurement. It is characterized by shortening time.

  Also, a host control device that controls the inspection system, a signal source provided for each pin of the IC to be inspected that is controlled via the control bus, a plurality of pin devices equipped with measuring instruments, and a signal source A condition setting / judgment value memory for setting conditions, a judgment circuit that outputs a judgment by comparing the standard value from the condition setting / judgment value memory with the measurement value of the measuring instrument, and ORing the outputs of the plurality of judgment circuits And a simultaneous memory selection bus that controls a plurality of condition setting / judgment value memories all at once, and a simultaneous determination bus that transmits the output of a logical sum, and the host control device controls the simultaneous memory selection bus and the simultaneous determination bus. , Characterized by reference.

  Also, a host control device that controls the inspection system, a signal source provided for each pin of the IC to be inspected that is controlled via the control bus, a plurality of pin devices equipped with measuring instruments, and a signal source A condition setting / judgment value memory for setting conditions, a judgment circuit that outputs a judgment by comparing the standard value from the condition setting / judgment value memory with the measurement value of the measuring instrument, and ORing the outputs of the plurality of judgment circuits Means, a simultaneous memory selection bus for simultaneously controlling a plurality of condition setting / determination value memories, a simultaneous determination bus for transmitting an output of logical sum, a simultaneous memory selection register for controlling the simultaneous memory selection bus, and a simultaneous determination bus And the simultaneous memory selection register and the simultaneous determination register are controlled and referred to by a host control device via a control bus.

  Further, the IC inspection method of the present invention is an IC inspection method for continuously executing a plurality of inspections having different contents with respect to the IC to be inspected, and for each pin provided for each pin of the IC to be inspected. The method comprises a condition setting process of the means and a measurement process of the inspection means for each pin, and the inspection time for each inspection item is shortened by both processes that simultaneously execute the condition setting process and the measurement process.

  In addition, the first step of setting the inspection execution by supervising the inspection system, and the individual inspection for each of the plurality of pin inspection means provided with the signal generation means and the measurement means for each pin of the IC to be inspected A second step for controlling the execution, a third step for setting the conditions of the signal generating means simultaneously by the storage means provided for each pin of the IC to be inspected, and a standard value obtained from the storage means This is a fourth step in which the comparison means provided for each pin of the IC to be inspected for comparing the measurement values obtained from the measurement means is used to determine all at once by means of taking a logical sum from the outputs of the plurality of comparison means. The setting and measurement of the plurality of pin inspection means in the third step and the fourth step are directly controlled and referred to in the first step.

  Also, the first step of setting the inspection execution by supervising the inspection system, and the plurality of pin inspection means and bus storage means provided with signal generation means and measurement means for each pin of the IC to be inspected The second step of controlling the execution of individual inspections, the third step of setting the conditions of the signal generating means all at once by the storage means provided for each pin of the IC to be inspected, and the storage means. A comparison means provided for each pin of the IC to be inspected for comparing the standard value measured with the measurement means and a means for taking a logical sum from the outputs of the plurality of comparison means, And the setting and measurement of the plurality of pin inspection means in the third step and the fourth step are controlled and referred to by the first step through the control by the second step. .

  According to the IC inspection apparatus and inspection method described above, the memory device (condition setting / determination value memory) and the determination circuit are added to the device for each pin provided for each pin of the IC to be inspected, and the simultaneous memory By using the selection bus and the simultaneous determination bus, the inspection time per IC can be shortened.

  As described above, according to the present invention, since the condition setting / determination value memory and the determination circuit are added to the device for each pin and controlled, the test time can be shortened by using the simultaneous memory selection bus and the simultaneous determination bus. Therefore, the inspection time per IC can be shortened, and therefore, it is effective to obtain a very large profit when applied to a mass production inspection in which a large amount of ICs are inspected.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of an IC inspection apparatus according to Embodiment 1 of the present invention. Here, components having substantially the same functions corresponding to the components described in FIG. 11 showing the conventional example are denoted by the same reference numerals, and the same applies to the following drawings.

  As shown in FIG. 1, the IC inspection apparatus includes a host control apparatus 1 and an inspection apparatus body 10. In the inspection apparatus main body 10, there are built in pin devices 2 that can individually apply signals to and measure each pin of the IC to be inspected, and the number of pin devices 2 is equal to the number of IC pins. The standard configuration is 100 to 500. Each pin device 2 is controlled by the host control device 1 through the control bus 6.

  Furthermore, a condition setting / determination value memory 3 and a determination circuit 4 are added to each pin device 2, and data in the condition setting / determination value memory 3 is routed to the signal source and determination circuit 4 of each pin device 2. distributed through a and path c. A measurement value is guided from the measuring device of each pin apparatus 2 to the determination circuit 4 through the path b, and the determination circuit 4 determines the standard value given through the path c. Each condition setting / determination value memory 3 outputs prestored data in the order of inspection items in accordance with a command from the simultaneous memory selection bus 7.

  The result output of the decision circuit 4 is connected to the base of the transistor 5 added to each pin device 2 through the path d. The collector of the transistor 5 is connected to a common simultaneous determination bus 8 and a pull-up resistor 9 is connected. That is, a wired NOR circuit as an output result of each determination circuit 4 is configured. The simultaneous memory selection bus 7 and the simultaneous determination bus 8 are respectively connected to the host controller 1 and can be directly controlled / referenced from the host controller 1. The host control device 1 is a computer and is located a little away from the inspection device main body 10. By changing the program of the host control device 1 using a system having such a basic configuration, it is possible to inspect ICs having different functions.

  Actually, as described in the above-described conventional IC inspection system shown in FIG. 10, the signal source of each pin device 2 and the output of the measuring device are connected to the inspection board 14 via the measurement signal transmission path 15, Although it finally reaches each pin of the IC 13 to be inspected through the pattern of the inspection board 14, this path is omitted in FIG.

  Next, the contents of the determination circuit of FIG. 1 will be described with reference to the circuit examples of FIGS.

  FIG. 2 is a block diagram showing a first example in which the configuration is implemented by a window comparator circuit as a determination circuit. As shown in FIG. 2, the voltage to be determined is connected to one of the inverting and non-inverting inputs of the first and second comparators 43 and 44 through the path b. The upper limit value data and the lower limit value data from the condition setting / judgment value memory 3 are digital-analog converted by the first D / A converter 41 and the second D / A converter 42 through the path c, and then the first and second comparators 43, respectively. , 44 is connected to the other inverting and non-inverting input.

  After the outputs of the first and second comparators 43 and 44 pass through the NAND gate 45, a determination output is obtained through the path d. In this case, if the measured value is within the standard value defined by the upper limit value data and the lower limit value data, a low (L) is output. If the output is low (L), the logic of the simultaneous determination bus becomes higher (H) than the wired NOR circuit constituted by the transistor 5 in the next stage, and a non-defective product is determined.

  FIG. 3 is a block diagram showing a second example in which the determination circuit is configured by an A / D converter and a logical comparator. As shown in FIG. 3, the determination target voltage is connected to the input of the A / D converter 46 through the path b. The determination value subjected to analog-digital conversion is registered in the first register 47. The upper limit value data and the lower limit value data from the condition setting / judgment value memory 3 are registered in the second register 50 and the third register 51 through the path c. The judged value is compared with the upper limit value data and the lower limit value data by the first and second logic comparators 48 and 49, and after passing through the NAND gate 45, a judgment output is obtained through the path d.

FIG. 4 is a block diagram illustrating a third example in which the configuration is implemented by a CPU such as an A / D converter and a one-chip microcomputer as a determination circuit.
As shown in FIG. 4, the determination target voltage is connected to the input of the A / D converter 46 through the path b. The analog-to-digital converted determination value is read by the CPU 52, and the upper limit value data and lower limit value data from the condition setting / determination value memory 3 are also read by the CPU 52 through the path c. The determined value is compared with upper limit value data and lower limit value data by the CPU 52, and a determination output is obtained through the path d.

  The difference between the first embodiment and the conventional example is that each pin device 2 shown in FIG. 1 has a condition setting / determination value memory 3 and a determination circuit 4. The inspection time can be reduced by controlling and referring to the simultaneous memory selection bus 7 and the simultaneous determination bus 8.

  The processing operation related to the inspection time of the IC to be inspected will be described with reference to FIG. When one inspection item is divided along the time axis, the first is the condition setting, the second is the response waiting time for waiting for the response of the IC to be inspected, the third is the measurement, and the fourth is the order of determination. Here, paying attention to the first condition setting, in the case of the conventional example, it was necessary to carry out in order from the 1-pin device to the N-pin device until the setting of all pin conditions was completed. In the case of 1, the condition setting of each pin device 2 can be performed in accordance with a command from the simultaneous memory selection bus 7 because data stored in advance by the condition setting / determination value memory 3 can be output simultaneously in the order of inspection items. Such time can be made the same as when only one pin is set even if the conditions are set for all pins.

  Further, when focusing on the third measurement, in the case of the conventional example, it was necessary to sequentially perform from the 1-pin device to the N-pin device until the measurement of all pins was completed. Since the measurement results of each pin device 2 are simultaneously determined by the determination circuit 4 and can be taken out as a logical sum of all pins by the simultaneous determination bus 8, the time required for measurement and determination can be reduced to one pin even if all pins are measured. It can be the same as the case only for it.

  Each condition setting time and measurement time of each pin is as short as several hundred μs, and even when 100 to 500 as the number of devices 2 for each pin are performed at once, the total condition setting time and measurement time is several. Since it is performed with 100 μs, the effect of shortening the inspection time is very high. Considering that the IC to be inspected has a long response waiting time of about 20 ms, the time spent on the control of each pin device 2 in one item of inspection time can be almost ignored. Although the inspection depends on the scale of the IC, the contents of several hundred items are usually executed in series. Even in such a case, most of the time is only the response waiting time of the IC to be inspected, so that highly efficient inspection can be performed.

  FIG. 6 is a block diagram showing a configuration of an IC inspection apparatus according to Embodiment 2 of the present invention. As shown in FIG. 6, the IC inspection apparatus includes a host control apparatus 1 and an inspection apparatus body 10. In the inspection apparatus main body 10, there are built in pin devices 2 that can individually apply signals to and measure each pin of the IC to be inspected, and the number of pin devices 2 is equal to the number of IC pins. The standard configuration is 100 to 500. Each pin device 2 is controlled by the host controller 1 through the control bus 6. A condition setting / determination value memory 3 and a determination circuit 4 are added to each pin device 2, and data in the condition setting / determination value memory 3 is routed to the signal source and determination circuit 4 of each pin device 2. distributed through c. A measurement value is guided from the measuring device of each pin apparatus 2 to the determination circuit 4 through the path b, and the determination circuit 4 determines the standard value given through the path c. Each condition setting / determination value memory 3 outputs prestored data in the order of inspection items in accordance with a command from the simultaneous memory selection bus 7.

  The result output of the decision circuit 4 is connected to the base of the transistor 5 added to each pin device 2 through the path d. The collector of the transistor 5 is connected to a common simultaneous determination bus 8 and connected to a pull-up resistor 9. That is, a wired NOR circuit as an output result of each determination circuit 4 is configured.

  The effect of shortening the inspection time is the same as in the first embodiment. The difference from the first embodiment is that the simultaneous memory selection bus 7 is connected to the control bus 6 via the simultaneous memory selection register 11, and the simultaneous determination bus 8 is also connected to the control bus 6 via the simultaneous determination register 12. There is in point. By adopting such a configuration, it is not necessary to provide the control terminals of the simultaneous memory selection bus 7 and the simultaneous determination bus 8 on the host controller 1 side, and the wiring of the simultaneous determination bus 8 in which the influence of stray capacitance is a concern is fixed. Therefore, stable operation is possible even when the host control device 1 and the inspection device main body 10 are a little apart. Since the host controller 1 controls only the control bus 6, it is necessary to set addresses including the simultaneous memory selection register 11 and the simultaneous determination register 12. A schematic configuration of this address is shown in FIG.

  FIG. 8 is a diagram showing a specific configuration of each pin device of the IC inspection device according to the third embodiment of the present invention, and a portion surrounded by a dotted line as shown in FIG. 8 is a device for each pin. 2. In FIG. 8, 21 is a variable voltage source, 21 is a variable current source, 23 is an ammeter, 24 is a voltmeter, and 25 is an operation mode changeover switch. In the example shown in FIG. 8, the operation mode changeover switch 25 is selected in one voltage source mode. In this case, a predetermined voltage can be applied to pin 1 of the IC 13 to be inspected to inspect the current flowing therethrough. An example of the inspection includes a power supply current inspection.

  When the operation mode changeover switch 25 is switched to the other, the current source mode is selected. In this case, it is possible to inspect the voltage generated by applying a predetermined current to the pin 1 of the IC 13 to be inspected. One example of the inspection is an impedance inspection. Further, by opening the output switch 26, it is possible to prevent any influence on the pin 1 of the IC 13 to be inspected.

  The third D / A converter 27 and the fourth D / A converter 28 can set the values of the variable voltage source 21 and the variable current source 22, respectively. The condition setting changeover switch 29 is used to set the conditions of the operation mode changeover switch 25, the output switch 26, the third D / A converter 27, and the fourth D / A converter 28 via the control bus 6, or in the condition setting / determination value memory 3. It is possible to switch whether to follow the condition setting contents.

  Further, a condition setting / determination value memory 3 and a determination circuit 4 are added, and output data of the condition setting / determination value memory 3 is distributed to the condition setting changeover switch 29 and the determination circuit 4 through the path a and the path c. The measured values from the ammeter 23 and the voltmeter 24 are led to the determination circuit 4 through the path b, and the determination circuit 4 determines the standard value given through the path c.

  Each condition setting / determination value memory 3 can output data stored in advance in the order of inspection items in accordance with a command from the simultaneous memory selection bus 7. The result output of the determination circuit 4 is connected to the base of the transistor 5 added to each pin device 2 through the path d, and the collector of the transistor 5 is connected to the common simultaneous determination bus 8. Each condition setting / determination value memory 3 needs to store data in the order of inspection items in advance, but in this case, it is performed via the control bus 6.

  As described above, a condition setting / determination value memory and a determination circuit can be added to each pin device, and control can be performed using the simultaneous memory selection bus and simultaneous determination bus to shorten the inspection time of the IC to be inspected. it can.

  In the IC inspection apparatus and inspection method according to the present invention, a condition setting / determination value memory and a determination circuit are added to each pin device, and control is performed using a simultaneous memory selection bus and a simultaneous determination bus. Therefore, the present invention is useful as an IC inspection apparatus and inspection method that shortens the inspection time by applying it to a mass production inspection in which a large amount of IC is inspected by shortening the inspection time.

The block diagram which shows the structure of the inspection apparatus of IC in Embodiment 1 of this invention. FIG. 3 is a block diagram showing a first example of a determination circuit in the first embodiment. FIG. 3 is a block diagram showing a second example of the determination circuit in the first embodiment. Block diagram showing a third example of the determination circuit according to the first embodiment Flow chart showing inspection time required for IC to be inspected in the first embodiment The block diagram which shows the structure of the inspection apparatus of IC in Embodiment 2 of this invention. The figure which shows the outline | summary structure of the address setting in this Embodiment 2. The figure which shows the specific structure of the inspection apparatus of IC in this Embodiment The block diagram which shows the outline in the inspection system of the conventional IC Diagram showing the principle of signal source / measuring instrument in each pin device Block diagram showing the configuration of a conventional IC inspection device Flow chart showing the inspection time required for a conventional IC to be inspected

Explanation of symbols

1 Host control device 2 Device for each pin 3 Condition setting / determination value memory 4 Judgment circuit 5 Transistor 6 Control bus 7 Simultaneous memory selection bus 8 Simultaneous determination bus 9 Pull-up resistor 10 Inspection device main body 11 Simultaneous memory selection register 12 Simultaneous determination register 13 IC to be inspected
14 Inspection board 15 Measurement signal transmission path 21 Variable voltage source 22 Variable current source 23 Ammeter 24 Voltmeter 25 Operation mode changeover switch 26 Output switch 27 3D / A converter 28 4D / A converter 29 Condition setting changeover switch 41 1D / A converter 42 2nd D / A converter 43 1st comparator 44 2nd comparator 45 NAND gate 46 A / D converter 47 1st register 48 1st logic comparator 49 2nd logic comparator 50 2nd register 51 3rd register 52 CPU

Claims (6)

  In an IC inspection apparatus for continuously executing a plurality of inspections having different contents with respect to an IC to be inspected, simultaneous control means for setting conditions of each pin device provided for each pin of the IC to be inspected, An IC inspection apparatus comprising: a simultaneous control unit for measuring each pin device, wherein the inspection time for each inspection item is shortened by both the simultaneous control unit for setting conditions and the simultaneous control unit for measurement.   A host control device that controls the inspection system, a signal source provided for each pin of the IC to be inspected that is controlled via the control bus, a plurality of pin devices equipped with measuring devices, and conditions for the signal source A condition setting / determination value memory for setting, a determination circuit for outputting a determination by comparing the standard value from the condition setting / determination value memory with the measurement value of the measuring device, and a logical sum from the outputs of the plurality of determination circuits A simultaneous memory selection bus for simultaneously controlling a plurality of the condition setting / determination value memories, and a simultaneous determination bus for transmitting the output of the logical sum, the simultaneous memory selection bus and the simultaneous determination bus The IC inspection device is controlled and referred to by the host control device.   A host control device that controls the inspection system, a signal source provided for each pin of the IC to be inspected that is controlled via the control bus, a plurality of pin devices equipped with measuring devices, and conditions for the signal source A condition setting / determination value memory for setting, a determination circuit for outputting a determination by comparing the standard value from the condition setting / determination value memory with the measurement value of the measuring device, and a logical sum from the outputs of the plurality of determination circuits A simultaneous memory selection bus for simultaneously controlling a plurality of the condition setting / determination value memories, a simultaneous determination bus for transmitting the output of the logical sum, and a simultaneous memory selection register for controlling the simultaneous memory selection bus And a simultaneous determination register that refers to the simultaneous determination bus, and controls and refers to the simultaneous memory selection register and the simultaneous determination register by the host controller via the control bus. Inspection of the IC, characterized in that.   In an IC inspection method for continuously executing a plurality of inspections having different contents with respect to an IC to be inspected, a condition setting step of each pin inspection means provided for each pin of the IC to be inspected, and each pin A method for inspecting an IC comprising: a measuring step of an inspection means, wherein the inspection time of each inspection item is shortened by both steps of performing both the condition setting step and the measuring step simultaneously.   The first step of setting the inspection execution by supervising the inspection system, and the individual inspection execution for the plurality of pin inspection means provided with the signal generation means and the measurement means for each pin of the IC to be inspected A second step of performing control, a third step of setting the conditions of the signal generating means simultaneously by a storage means provided for each pin of the IC to be inspected, and a standard value obtained from the storage means And a comparison means provided for each pin of the IC to be inspected for comparing measured values obtained from the measurement means with a means for taking a logical sum from the outputs of the plurality of comparison means. A method for inspecting an IC, wherein the setting and measurement of each of the plurality of pin inspection means in the third step and the fourth step are directly controlled and referred to in the first step. .   The first step of setting the inspection execution by supervising the inspection system, and each of the plurality of pin inspection means and bus storage means provided with signal generation means and measurement means for each pin of the IC to be inspected A second step of controlling the execution of the inspection, a third step of setting the condition of the signal generating means all at once by the storage means provided for each pin of the IC to be inspected, and the storage means Using the comparison means provided for each pin of the IC to be inspected for comparing the obtained standard value with the measurement value obtained from the measurement means, the determination is performed simultaneously by means for taking a logical sum from the outputs of the plurality of comparison means. The setting and measurement of the plurality of pin inspection means in the third step and the fourth step are performed by the first step through the control by the second step. IC inspection method characterized by control and reference .

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