JPH0587578U - LSI tester - Google Patents

Abstract

(57) [Summary] [Purpose] A multi-value output device can be inspected with high accuracy and at high speed. [Configuration] An expected value in which an analog-to-digital converter that converts a response signal output from an object to be inspected based on a test pattern into digital data and expected value data of a response signal that the analog-digital converter digitally converts are stored. Memory, a digital comparator for comparing the expected value data of the expected value memory and the digital data of the analog-digital converter, and the fail flag output when the comparison result of the digital comparator is fail, and the object to be inspected is detected. A fail flag judgment circuit for judging the defect of No. 1 is provided, and the quality judgment is performed in real time.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to an LSI tester capable of inspecting a multi-value output device used for driving a liquid crystal display (hereinafter, referred to as LCD) with high accuracy and high speed.

[0002]

[Prior Art]

 To drive the LCD, a device capable of outputting multiple output voltages (hereinafter referred to as an object to be measured, a DUT) is required. FIG. 3 is a waveform diagram showing an example of an output waveform that is output to the common in the case of 1/5 bias and 1/6 duty driving. When measuring such a DUT, the conventional LSI tester sets the expected value level in the comparator in advance and determines the output level output by the DUT according to this expected value level, or the output level output by the DUT. Was once converted into a digital signal, and the data was stored in the memory, and then judged.

[0003]

[Problems to be solved by the device]

 Such a conventional LSI tester has the following drawbacks. (1) In the method of setting the expected value level in the comparator in advance, there is a limit to the number of expected value levels that can be set. (2) In the method of converting the output level of the DUT to digital and storing the digital data in the memory, since all the digital data is stored in the memory and then the pass / fail judgment is performed, real-time determination cannot be performed.

The present invention has been made in view of such a point, and the response signal of the DUT is once digital-converted by an analog-digital converter (hereinafter, abbreviated as AD converter) and converted into digital data thereof. The quality of the DUT is directly determined based on this, and the object is to provide an LSI tester that can determine the quality of the DUT in real time over the entire rate.

[0005]

[Means for Solving the Problems]

 In order to achieve such an object, the present invention provides an analog-digital converter that converts a response signal output from an object to be inspected based on a test pattern into digital data, and a response that the analog-digital converter digitally converts. The expected value memory that stores the expected value data of the signal, the digital comparator that compares the expected value data of this expected value memory with the digital data of the analog-digital converter, and the comparison result of this digital comparator are A fail flag determination circuit that detects a fail flag output in the case of a failure and determines a defect of the inspected object is provided, and based on the fail flag output from the digital comparator, the inspected object described above is provided. The feature is that the quality judgment of is performed in real time.

[0006]

[Action]

 Each component of the present invention operates as follows. The AD converter digitally converts the response signal output from the DUT and outputs the digital data to a digital comparator. The expected value memory outputs expected value data to the digital comparator based on the address specified by the pattern address generator. The digital comparator compares the digital data input from the AD converter with the expected value data input from the expected value memory, and outputs the comparison result to the fail memory and the fail flag determination circuit.

[0007]

【Example】

An embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of the LSI tester of the present invention. In the figure, 1 is DUT, 2 are amplifiers, 3 a signal Conde _Lee conditioner converts the response signal input from DUT1 via the amplifier 2 to the signal level of the AD converter 4 outputs to the AD converter 4 .

[0008] AD converter 4, a response signal input from the signal Conde _Lee conditioner 3 digital conversion, and outputs the digital data to the digital window comparator 5. An expected value memory 6 outputs high-level expected value data that determines the upper limit range and low-level expected value data that determines the lower limit range to the digital window comparator 5 based on the address specified by the pattern address generator 7.

The digital window comparator 5 compares the expected value data input from the expected value memory 6 with the digital data input from the AD converter 4, and outputs the result to the fail memory 8. In the fail memory 8, the fail data output from the digital window comparator 5 is written in the address designated by the pattern address generator 7.

Reference numeral 9 denotes a fail flag determination circuit, which detects a fail flag signal output from the digital window comparator 5 when the comparison result of the digital window comparator 5 is fail and determines a DUT failure in real time. The data stored in the fail memory 8 is later collectively read by the CPU and is mainly used for debugging. The fail flag signal detected by the fail flag determination circuit 9 is sent to the DUT 1 in real time. It is used to judge the occurrence of fail.

Reference numeral 10 denotes a timing generator that outputs a timing clock that serves as an operation reference of the device, and outputs a rate clock to the pattern address generator 7 and a strobe clock to the AD converter 4. The pattern address generator 7 specifies an address to the expected value memory 6, the fail memory 8 and the pattern memory (not shown) based on the rate clock input from the timing generator 10. On the other hand, AD converter 4 on the basis of the strobe clock, converts the response signal inputted from the signal Conde _Lee cane Na 3 into digital data, and outputs the digital window comparator 5. The pattern memory stores an inspection pattern to be given to the DUT.

2A and 2B are operation explanatory views for explaining the operation of the LSI tester of the present invention. FIG. 2A is a response signal output from the DUT, and FIG. 2B is a digital signal output from the AD converter to the digital window comparator. Data, (C) is expected value data output from the expected value memory to the digital window comparator, and (D) is fail data output from the digital window comparator.

The AD converter 4 digitally converts the response signal of the DUT 1 according to the strobe clock of the timing generator 10, and outputs the converted digital data to the digital window comparator 5. At this time, the high level and low level expected value data are already input to the digital window comparator 5 from the expected value memory by the specification of the pattern address generator 7.

The digital window comparator 5 compares the digital data input from the AD converter 4 with the expected value data input from the expected value memory 6, and outputs the comparison result to the fail memory 8 and the fail flag determination circuit 9. To do. Since the "00", "04", and "08" data output by the AD converter 4 in order is within the standard value of the expected value data output from the expected value memory, the fail data is output as pass data. ..

However, subsequently, since the data “08” output from the AD converter 4 is out of the standard values “0D” and “0B” of the expected value data, the digital window comparator 5 It outputs the fail data and the fail flag signal. The fail flag determination circuit 9 detects the fail flag signal output from the digital window comparator 5 and determines the occurrence of a failure in the DUT 1.

[0016]

[Effect of the device]

 As described above in detail, in the LSI tester of the present invention, the response signal of the DUT is digitally converted by the AD converter, and the data is compared with the expected value data by the digital comparator in real time. Thus, multi-value output devices can be inspected with high accuracy and at high speed.

[Brief description of drawings]

FIG. 1 is a configuration block diagram showing an embodiment of an LSI tester of the present invention.

FIG. 2 is an operation explanatory view explaining an operation of the LSI tester of the present invention.

FIG. 3 is a waveform diagram showing an output waveform output from a device for driving an LCD.

[Explanation of symbols]

 4 AD converter 5 Digital window comparator 6 Expected value memory 9 Fail flag judgment circuit

Claims (1)

[Scope of utility model registration request] 1. An analog-digital converter for converting a response signal output from an object to be inspected based on a test pattern into digital data, and expected value data of the response signal digitally converted by the analog-digital converter are stored. An expected value memory, a digital comparator for comparing the expected value data of the expected value memory with the digital data of the analog-digital converter, and a fail flag output when the comparison result of the digital comparator is fail. An LSI tester characterized by providing a fail flag judgment circuit for judging a defect of the inspection object, and making a quality judgment of the inspection object in real time based on the fail flag output from the digital comparator. .