JPH02268520A - Successive approximation analog/digital conversion circuit - Google Patents

Abstract

PURPOSE:To facilitate the generation of a test pattern and to reduce the size of a test pattern itself by enabling a digital value inputted to a D/A conversion part in a test to be set at an arbitrary value, and issuing the output of a comparator to an outside. CONSTITUTION:A digital signal 4 sent from a successive approximation control circuit 3 is connected to the digital input of the D/A conversion part 1 via a buffer circuit 10, and the output from a data bus 9 is connected to the digital input of the D/A conversion part 1 via a buffer 11, and the output of the comparator 8 is connected to an analog input terminal 7 via a buffer 12. Therefore, it is possible to set the digital value inputted to the D/A conversion part 1 in the test at the arbitrary value, and to issue the output of the comparator 8 to the outside. In such a manner, the accuracy of A/D conversion can be accurately tested by setting the upper and lower limit values of a conversion value at the D/A conversion part 1 and testing the output value of the comparator at that time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a successive approximation type analog-to-digital conversion circuit, and more particularly to a successive approximation type analog-to-digital conversion circuit having a built-in test function in a one-chip microcomputer.

[Conventional technology]

Conventionally, such successive approximation type analog-to-digital conversion circuits (hereinafter referred to as A/D converters) have various test functions, one of which is a test of conversion accuracy. The conversion accuracy standard of this A/D converter is usually defined as an error from an ideal converted value at the time of A/D conversion.

Here, as an example, the conversion accuracy of an 8-bit A/D converter will be explained with reference to FIGS. 3(a) and 3(b).

FIGS. 3(a) and 3(b) are an ideal characteristic diagram and a characteristic diagram with an error, respectively, for explaining the conversion accuracy of a general A/D converter.

As shown in FIG. 3(a), this characteristic shows an ideal characteristic when the reference voltage of the A/D converter is 5.11V, and includes only the quantization error. However, in reality, there are also influences such as noise,
Since errors other than quantization errors also occur, the characteristics shown in FIG. 3(b) are often guaranteed. That is, the third
In figure (b), the error is ±1.5LSB (IL
SB=5. IIV1511=O, 0IV) is allowed. Therefore, when 0.03V is input as the analog input voltage, the converted value is 02H.

This means that either 03H or 04H is sufficient. The factors that determine the accuracy of such an A/D converter are mainly determined by the accuracy of the D/A converter, the accuracy of the comparator, and the accuracy of the sample-and-hold circuit.

FIG. 4 is a block diagram of a successive approximation type A/D converter showing an example of such a conventional converter.

As shown in FIG. 4, this A/D converter outputs an analog signal 5 using the reference voltage input from the reference voltage input terminal 2 and the digital signal 4 sent and output from the successive approximation control circuit 3. Part 1 and
A sample-and-hold circuit 6 that samples and holds the analog voltage input from the analog voltage input terminal 7, and an analog voltage 5 output from the D/A converter 1.
The comparator 8 has a comparator 8 that compares the voltage with an analog voltage supplied from a sample-and-hold circuit 6, and a successive approximation control circuit 3 that repeats output control of a digital signal based on the comparison result.

In particular, the successive approximation control circuit 3 uses as an initial value a value (8
If it is a bit A/D converter, 7FH) is sent as a digital signal 4 to the D/A converter 1, and the output of the D/A converter and the output of the sample-and-hold circuit 6 are compared. Here, if the output of the D/A converter 1 is smaller,
The most significant bit is set to "1", and conversely, if it is larger, it is set to "0". Thereafter, the second bit from the most significant bit is set to 0, and the third and subsequent bits from the most significant are set to 1, and comparison control is performed again. The above-described processing is repeated in order from the most significant bits, and finally a digital value corresponding to the analog voltage is obtained in the successive approximation control circuit 3. This finally converted digital value is output from the control circuit 3 to the data bus 9.

When testing the conversion accuracy of the A/D converter described above, increase the input voltage by O, OIV from O■ and sequentially test the A/D converter.
Conversion is performed, and the conversion accuracy is tested using an LSI tester or the like.

[Problem to be solved by the invention]

In the above-described conventional A/D converter, when testing its conversion accuracy, there are a plurality of conversion values (three in the example of FIG. 3(b)) even if they are within the standard. Normally, LSI testers compare the expected value stored in the LSI tester with the output from the LSI in order to determine whether the LSI is good or defective. Since there is only one type of expected value, it is not possible to directly compare the converted value of the A/D converter with the expected value of the LSI tester as described above. Therefore, in a single-chip microcontroller with a built-in A/D converter,
The result of the D conversion is transferred to the CPU, which determines whether the conversion result is within the standard, and outputs the result to the outside for determination by an LSI tester.

However, this discrimination method has the disadvantage that it is difficult to design a test pattern, and the test pattern itself is very long.

An object of the present invention is to provide an A/D converter that facilitates the creation of a test pattern and can shorten the test pattern itself when testing such A/D conversion accuracy.

[Means to solve the problem]

The A/D converter of the present invention includes a D/A converter that generates a first analog level based on a set digital value, and a sample that receives an analog voltage from an external terminal and outputs a second analog level. and hold circuit,
An A/D converter comprising a comparator that compares the first and second analog levels, and a control circuit that judges the output of the comparator and performs successive approximation control when generating the first analog level, The device includes means for setting a digital value input to the D/A converter to an arbitrary value during a test, and means for outputting the output of the comparator to the outside.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an A/D converter showing a first embodiment of the present invention.

As shown in FIG. 1, this embodiment is different from the conventional example shown in FIG. The output from the data bus 9 is connected to the digital input of the D/A converter 1 via the buffer 11, and the output from the comparator 8 is connected to the buffer 12. This is the point where it is connected to the analog input terminal 7 via. Another difference is that a test signal 13 is used as an output permission signal for these buffers 10, 11, and 12. Note that these buffers 10
．． 11 is only marked for 1 bit on the drawing, but
Actually, there are as many bits as the digital input value of the D/A converter 1.

Next, the operation of the above-mentioned A/D converter will be explained.

First, when the test signal 13 is "0", the fourth
It is equivalent to the circuit of the conventional A/D converter shown in the figure, and performs the same operation.

On the other hand, when testing the A/D converter, an analog voltage to be tested is applied to the analog input terminal 7 with the test signal 13 set to 0'', and sampled by the sub-and-hold circuit 6.Then, the test signal 1
3 to "1", give the upper and lower limits of the digital conversion value to the digital input of the D/A converter 1, and then check the output of the comparator 8 to see if the A/D conversion result is within the standard. Do a test.

For example, when comparing the upper limit value with the standard as shown in Figure 3(b) explained in the prior art, when 3X10-2V is applied as the analog input voltage, the digital conversion value is 05H at the D/A converter. Give to 1. However, A
In order for the /D converter to operate within a predetermined accuracy, the output of the comparator 8 at this time must be "1".

Similarly, regarding the lower limit value, when OIH is input as the input of the D/A converter 1, the output of the coverator 8 must be 0''.In other words, by testing the output of this comparator 8, the A/D The conversion accuracy of the converter can be tested.

FIG. 2 is a block diagram of an A/D converter showing a second embodiment of the present invention.

As shown in FIG. 2, this embodiment differs from the first embodiment described above in that the output of the comparator 8 is outputted to the outside as a separate terminal. This second embodiment has the advantage that the analog input voltage can be sampled while the test signal 13 remains at "1".

〔Effect of the invention〕

As explained above, the A/D converter of the present invention
By setting the upper and lower limits of the conversion value in the A converter and testing the output value of the comparator at that time, A
/D conversion accuracy can be accurately tested. Therefore, in the LSI tester, it is possible to determine whether a product is good or defective simply by comparing the output value of the comparator with the expected value of the LSI tester. In addition, when designing a test pattern, apply a predetermined analog voltage to the analog voltage input terminal,
All that is required is to output the comparator output at that time to the outside. Therefore, the test pattern can be easily created and the test pattern itself can be shortened.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an A/D converter showing a first embodiment of the present invention, and FIG. 2 is a block diagram of an A/D converter showing a second embodiment of the present invention.
A block diagram of the A/D converter, FIGS. 3(a) and 3(b) are an ideal characteristic diagram and a characteristic diagram when there is an error, respectively, to explain the conversion accuracy of a general A/D converter.
FIG. 4 is a block diagram of a conventional A/D converter. DESCRIPTION OF SYMBOLS 1...D/A converter, 2...Reference voltage input terminal, 3...Successive approximation control circuit, 4...Digital signal, 5...D/A converter output, 6... Sample and hold circuit, 7... Analog voltage input terminal, 8.
...Comparator, 9...Data bus, 10-12.
... Buffer, 13... Test signal, 14... Comparator output terminal.

Claims (1)

[Claims] a D/A converter that generates a first analog level based on a set digital value; a sample-and-hold circuit that inputs an analog voltage from an external terminal and outputs a second analog level; In a successive approximation type analog-to-digital conversion circuit having a comparator that compares a second analog level and a control circuit that performs successive approximation control by determining the output of the comparator when the first analog level is generated, The successive approximation type analog converter is characterized by having means for setting a digital value input to the D/A converter to an arbitrary value, and means for outputting the output of the comparator to the outside.
Digital conversion circuit.