JPH10268004A - Logic tester - Google Patents

Abstract

PROBLEM TO BE SOLVED: To add an optional writing function to a fail memory being prepared in a logic tester and to test an A/D or a D/A converter by storing the value of the A/D converter or the D/A converter to be tested at a conversion point and at the same time obtaining DC characteristics based on the stored value. SOLUTION: A pattern address generator 7 gives an address to a pattern memory part 8, thus outputting an expectation value being stored in advance and an instruction or data. The output of a counter 9 where a clock has been counted is converted into analog by an A/D converter 1 and is given to an A/D converter 2. The clock is inputted to the counter 9 repeatedly until the code of the output of the A/D converter matches the expectation value. When they match, a capture data enable signal is generated from a match circuit 4 and the value of an index counter at that point of time, namely the input value of the conversion point of the A/D converter 2, is written to a fail memory 5. An operation processing circuit 6 performs calculation based on the value stored in the fail memory 5, thus obtaining the DC characteristics of the A/D converter 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic tester for testing the quality of a DUT based on fail data obtained by comparing a response signal of a device under test (hereinafter referred to as "DUT") with an expected value, and more particularly to a fail data. The present invention relates to an improvement for realizing an inexpensive and high-speed logic tester by effectively using a fail memory for writing data.

[0002]

2. Description of the Related Art Recently, a mixed signal LSI represented by a microprocessor having an analog-to-digital converter (hereinafter, referred to as an AD converter) or a digital-to-analog converter (hereinafter, referred to as a DA converter) has been developed. A
A logic tester that can determine whether D / DA is good or bad has appeared.

In a conventional ordinary logic tester, when a failure occurs in a digital function test, an address value, an index counter value, fail pin information, and the like are stored in a fail memory.

Particularly, in a logic tester which measures a mixed signal LSI, when testing an AD converter, an AD converter output code is once stored in a capture memory, and then the output data is read from the capture memory. The readout is subjected to an appropriate operation to determine the quality of the AD converter.

[0005]

In a conventional logic tester for measuring a mixed signal LSI, a fail memory stores a failed address value, an index counter value, fail pin information, and the like. The output data of the converter could not be stored and stored with high accuracy. For this reason, apart from the fail memory, an expensive capture memory for storing and storing the output data of the AD converter with high accuracy is required, which is expensive as a logic tester and has a drawback that the processing speed is reduced. .

SUMMARY OF THE INVENTION In view of the foregoing, an object of the present invention is to provide an inexpensive and high-speed logic capable of testing an AD or DA converter by adding an arbitrary write function to a fail memory originally prepared in a logic tester. The realization of a tester.

[0007]

According to the present invention, there is provided an A / D converter or a D / A converter to be tested.
A logic tester for testing an A converter, wherein a value at a conversion point of the AD converter or DA converter under test is stored in a fail memory, and the AD converter or DA converter is operated based on the stored value. The converter is characterized in that it can determine the DC characteristics of the converter.

[0008]

The value at each conversion point of the AD converter or DA converter to be tested is stored in the fail memory. Thereafter, the AD converter or D
The DC characteristics of the A converter can be obtained.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings. FIG. 1 is a configuration diagram showing one embodiment of a logic tester according to the present invention. In the figure, 1 is a DA converter, 2 is D
UT, 3 is a comparator, 4 is a match circuit, 5 is a fail memory, 6 is an arithmetic processing circuit, 7 is a pattern address generator, 8 is a pattern memory unit, and 9 is a counter.

The DA converter 1 outputs an analog signal according to the number of clocks input. DUT2 is AD
The converter converts the output of the DA converter 1 into a digital signal. The comparator 3 binarizes the output (binary signal) of the AD converter 2 by comparing it with a predetermined threshold level in order to further improve the accuracy.

The match circuit 4 receives the output of the AD converter via the comparator 3 and the expected value given from the pattern memory unit 8, and outputs a match signal when the two match. This match signal is supplied to the fail memory 5 as a capture data enable (CDE) signal, and when the CDE is issued, the value of the index counter output from the pattern address generator 7 is stored in the fail memory 5.
Is written to.

The pattern address generator 7 issues an address to the pattern memory unit 8. The pattern memory unit 8 includes a memory unit and a formatter (not shown). In the memory unit, for each address, a clock signal and a control signal for the counter 9 (control signals for reset, up-count, down-count, etc.), an expected value given to the match circuit 4, a start command given to the AD converter 2 and an output Data for selecting the number of bits is stored in advance. The formatter has a function of shaping the waveform of the data output from the memory unit and outputting the data.

The operation in such a configuration will be described below. The pattern address generator 7 gives an address to the pattern memory unit 8 to output an expected value, instructions and data stored in advance. The expected value is supplied to the match circuit 4, and the instruction and data are supplied to the AD converter 2. The instructions and data are used for controlling the operation of the AD converter 2 and specifying the number of output bits.

A pattern address generator 7
Stores the number of clocks supplied to the counter 9 as an index counter, and outputs this to the fail memory 5.

The output of the counter 9 that has counted the clock is D
The analog signal is converted by the A converter 1 and supplied to the AD converter 2. It should be noted that a DA converter 1 having sufficient accuracy compared to the AD converter 2 is used.

A clock is repeatedly input to the counter 9 until the output code of the AD converter 2 matches the expected value code. When a match occurs, a capture data enable signal is issued from the match circuit 4, and the value of the index counter at that time is written into the fail memory 5. That is, the input value at the conversion point of the AD converter 2 (the input code of the DA converter 1 in this case) is written into the fail memory 5.

Thereafter, the same operation is repeated. That is, the operation of issuing the pattern address and writing the value of the index counter to the fail memory 5 every time the output of the AD converter matches the expected value is repeated from the 0 code of the AD converter 2 to the full code. As a result, the increment of the counter until it matches each expected value is accumulated in the fail memory 5.

Assuming that each value (step value) stored in the fail memory 5 is icode (n), when the AD converter 2 outputs 8 bits, the sum icfull of codes for a full code is as follows. icfull = Σicode (i) where Σ is an addition from i = 1 to 256

The value dutlsb of one LSB of the code is dutlsb = icfull / 255. The differential linearity error dnl (i) is represented by dnl (i) = [icode (i) −icode (i−1)] − dutlsb where i = 1 to 256.

The integral linearity error inl (i) is represented by inl (i) = Σicode (n) −i × dutlsb where i = 1 to 255.

The arithmetic processing circuit 6 performs the above-mentioned arithmetic operation, and
The DC characteristics of the converter 2 can be obtained. In addition, the time required for the above test is 10 μS conversion time of the DUT1.
Assuming that measurement is performed with 12-bit accuracy, the data read time is 20 mS, the conversion time is 4096 × 10 μS,
Since the operation time is 10 ms, the total time required for one test from 0 code to full code is 70 ms.

FIG. 2 is a block diagram of a main part of an embodiment constructed so that a zero level offset and a full code gain can be further obtained. The test procedure of the AD converter 2 will be described as follows.

The input of the DA converter 1 is set to zero (reset). The zero offset of the AD converter 2 is searched. That is, the switch 13 in FIG. 2 is connected to the AD converter 2 as shown in the figure, and a signal (SPMU) is given to the multiplier 11 and the adder 12 to change the value input to the AD converter 2. , The output code of the AD converter 2 is changed from 0 to 1
Or from 1 to all 0. The offset voltage at the zero point is obtained by measuring the input voltage of the AD converter 2 at that time by a DC voltage measurement module (not shown).

A full code is set in the DA converter 1. The full scale of the AD converter 2 is searched. That is, the signal SPM is supplied to the multiplier 11 and the adder 12 in FIG.
U is given as appropriate to change the value input to the AD converter 2,
The input voltage of the AD converter when the output code of the AD converter 2 transitions from full scale (FS) to FS-1 or from FS-1 to full scale is measured by a DC voltage measurement module (not shown). Find the full scale point.

While incrementing or decrementing the counter 9, a clock is sent to the counter 9 until the output of the AD converter matches the expected value. When they match, a capture data enable is issued from the match circuit 4, and the value of the index counter (the number of clocks applied to the counter) is written into the fail memory 5.

The above operation is repeated over all the codes of the AD converter 2. As a result, the increment (differential linearity) of the counter every time the output of the AD converter 2 increases by 1 bit is stored in the fail memory 5. By calculating this value in the arithmetic processing circuit 6, the DC characteristics of the AD converter 2 can be obtained. Also, the linearity of the integral can be determined.

On the other hand, a DA converter (referred to as a DA converter under test) 2a incorporated in the DUT can be tested according to the following procedure. In this test, a digital code is applied from a module (not shown) to the DA converter 2a under test, and its analog output is output from the DA converter 1 by the analog comparator 14 (specifically, the multiplier 11 and the adder 12). And the output via the switch 13). When the output of the comparator 14 is inverted, it is determined that they match.

The inputs of the DA converter 1 and the DA converter under test 2a are both set to zero code. The D / A converter under test 2a is searched for a zero offset. That is, a signal is appropriately supplied to the multiplier 11 and the adder 12, and the zero voltage of the DA converter 2a under test is combined with the output of the adder 12 via the switch 12 to obtain a zero offset.

A full code is set in the DA converter 2a and the DA converter 1 under test. Search full scale. That is, a full-scale code is given to the DA converter under test 2a, and a signal is appropriately given to the multiplier 11 and the adder 12, so that the full-scale voltage of the DA converter 2a under test matches the full scale of the DA converter 1. .

A predetermined code is set in the DA converter under test 2a to output an analog voltage, while the counter 9 at the input of the DA converter 1 is incremented or decremented. The output voltage of the comparator 2a is compared with the output of the DA converter 1 output via the adder 12, and the point at which the output of the comparator 14 is inverted is detected by the match circuit 4. When inverted, the value of the index counter is written in the fail memory 5.

By repeating the above, the DA converter under test 2
Measure for all codes of a. As a result, the increment of the counter 9 (differential linearity) is stored in the fail memory 5. By calculating this value in the arithmetic processing circuit 6, the DC characteristics of the DA converter 2a under test can be obtained. Also, the linearity of the integral can be determined.

It is to be noted that the above description of the present invention has been presented by way of illustration and example only, and of particular preferred embodiments. Therefore, the present invention is not limited to the above-described embodiments, and includes many more modifications without departing from the spirit thereof.
This includes deformation.

[0033]

As described above, according to the present invention, the following effects can be obtained. Conventionally, to measure an AD converter or a DA converter, an expensive option such as a capture memory is provided, or the code of the AD converter or the output voltage of the DA converter is statically read over a test time. Was. However, according to the present invention, an AD / DA converter test can be performed at low cost and at high speed by adding a function of writing an index counter value by effectively using a fail memory which is a basic component of a logic tester. A logic tester that can be implemented can be easily realized.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of a logic tester according to the present invention.

FIG. 2 is a main part configuration diagram of FIG. 1;

[Explanation of symbols]

 Reference Signs List 1 DA converter 2 AD converter 2a DA converter 3, 3a, 14 Comparator 4 Match circuit 5 Fail memory 6 Operation processing circuit 7 Pattern address generator 8 Pattern memory unit 9 Counter 11 Multiplier 12 Adder 13 Switch

Claims (4)

[Claims] 1. A logic tester for testing an AD converter or a DA converter under test, wherein a value at a conversion point of the AD converter or the DA converter under test is stored in a fail memory. And a logic tester characterized in that a DC characteristic of the AD converter or the DA converter can be obtained by calculation based on the stored value. 2. When the A / D converter is to be tested, the output of a D / A converter provided in advance is supplied to the A / D converter to be tested, and the D / A conversion for each output code of the A / D converter is performed. 2. The logic tester according to claim 1, wherein the value of the input code of the device is stored in a fail memory as the value of the conversion point. 3. When the D / A converter is to be tested, a comparator for comparing the output of the D / A converter provided in advance with the output of the D / A converter to be tested is provided. A fail memory in which the value of the input code of the provided D / A converter when the output of each input code of the target D / A converter matches the output of the provided D / A converter is used as the value of the conversion point. 2. The logic tester according to claim 1, wherein the logic tester is configured to store the data. 4. The logic tester according to claim 1, wherein the value of each conversion point stored in the fail memory is an increase or decrease from a previous value.