JP2002214305A - Ad converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an AD converter capable of easily evaluating monotonicity to improve the test efficiency and also performing an evaluation at a high-speed sampling rate even in an inexpensive evaluation system. SOLUTION: An analog signal is converted to an m-bit digital signal, and the output expectation value of the digital signal is generated according to the voltage level of the analog signal. The digital signal is compared with the output expectation value, and an error signal showing whether the difference between the both is ±2 or more or not is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an AD converter (analog-digital converter) equipped with a test circuit for testing the monotonicity of a converted digital signal.

[0002]

2. Description of the Related Art FIG. 4 is a conceptual diagram of an example of an AD converter evaluation system. As shown in the figure, the AD converter evaluation system 30 converts an analog signal Ain into an m-bit digital signal D <m−1: 0>.
D converter sample (DUT: Device Under Test)
A signal generator 34 for evaluating an analog signal Ain;
Controller 3 for controlling the operation of this evaluation system 30
6 is provided.

In the evaluation system 30, a controller 36
The signal generator 34 generates an analog signal Ain having a predetermined voltage level in accordance with the control signal input from the control circuit 30.
The analog signal Ain is supplied to the sample 32, and the m-bit digital signal D <m−
1: 0>. The converted digital signal D <m−
1: 0> is once fetched by the controller 36 and then processed to calculate characteristic values such as linearity error and distortion.

As a test method of the AD converter, various test methods are used in addition to the histogram method. However, the basic test setup is the same for all test methods. That is, as described above, the analog signal Ain is supplied to the sample 32, the converted digital signal D <m-1: 0> is once taken into the controller 36, and then processed inside the controller 36 according to each test method. Is performed.

[0005]

By the way, with the advance of the process and the circuit technology, the speed and the number of bits of the AD converter are also increasing. Therefore, in any case, the amount of data that must be processed in the controller 36 during the test increases, and the test time tends to be longer. When judging good or bad AD converters from characteristic values such as linearity error or distortion, the test time for bad products is also required as long as good products. Test efficiency is significantly reduced.

In recent years, it is not uncommon for analog circuits such as AD converters and digital circuits to be mixedly mounted, and for the above-described reasons, the ratio of test time of analog circuits to the total test time tends to increase. It is in.

[0007] Such a decrease in test efficiency raises the test cost, which results in an increase in chip price. Further, as the conversion rate (conversion clock) increases, the data (output of the sample 32) taken into the controller 36 also changes at a high speed. Therefore, a high-speed interface is adopted also for the input section of the controller 36. Must be performed, and an expensive evaluation system is required, which causes an increase in test cost.

An object of the present invention is to solve the problems based on the prior art, and to easily evaluate monotonicity.
An object of the present invention is to provide an AD converter that can improve test efficiency and can evaluate at a high sampling rate even in an inexpensive evaluation system.

[0009]

In order to achieve the above object, the present invention provides first means for converting an analog signal into an m-bit digital signal, and the digital signal according to a voltage level of the analog signal. A second means for generating the expected output value of the digital signal and comparing the digital signal with the expected output value and outputting an error signal indicating whether a difference between the digital signal and the expected output value is ± 2 or more. And an A / D converter characterized by comprising:

Here, the third means may further comprise: a difference between the digital signal and the expected output value is +1 or -1.
It is preferable to output a trigger signal indicating whether or not. The AD converter described above, further comprising: fourth means for generating an n (n> m) -bit digital signal; and fifth means for converting the n-bit digital signal into an analog signal. Preferably, the analog signal converted by the fifth means is supplied to the first means.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an AD converter according to the present invention will be described in detail based on a preferred embodiment shown in the accompanying drawings.

FIG. 1 is a schematic diagram showing the configuration of an embodiment of an AD converter according to the present invention. AD converter 10 shown in FIG.
Converts an analog signal Ain into an m-bit digital signal D <
m-1: 0> and includes an m-bit ADC (analog-digital converter) unit 12, an m-bit counter 14, a comparison circuit 16, and an AND gate 18. The counter 14, the comparison circuit 16, and the AND gate 18 constitute a test circuit of the ADC unit 12.

In the illustrated AD converter 10, first, the ADC unit 12 converts an analog signal Ain input from outside the AD converter 10 into an m-bit digital signal D <in synchronization with a clock signal (sampling clock) CLK. m-1: 0>. The converted digital signal D <m−1: 0> is supplied to the comparison circuit 16. The structure of the ADC unit 12 is not limited at all, and any conventionally known one can be used.

Subsequently, the counter 14 outputs the analog signal A
The count-up is performed in synchronization with the output signal from the AND gate 18 that receives the clock signal CLK synchronized with the voltage change of in and the trigger signal TRIG described below as inputs.
The count value is output as an expected output value CO <m−1: 0>. The expected output value CO <m−1: 0> is supplied to the comparison circuit 16 and is also output to the outside of the AD converter 10 in this embodiment.

The counter 14 outputs a reset signal RE
Initialized by SET, in the case of the present embodiment, the value of the expected output value CO <m−1: 0> is set to 0 (decimal number).

Finally, the comparison circuit 16 outputs the digital signal D
<M-1: 0> is compared with the expected output value CO <m-1: 0>, and a trigger signal TRIG and an error signal ERR are output. The trigger signal TRIG is set to AN as described above.
The signal is input to the D gate 18 and the AD converter 10
, And is used as a signal indicating a transition point of the digital signal D <m−1: 0>. The error signal ERR is output to the outside of the AD converter 10 and used as an error detection signal.

Here, the trigger signal TRIG includes a value of the digital signal D <m−1: 0> and an expected output value CO <m−
1: 0> indicates whether the difference from the value is +1. The error signal ERR indicates whether the difference is ± 2 or more. In the case of the present embodiment, the trigger signal TRIG is at a high level when the difference is +1 and at a low level otherwise. The error signal ERR has a difference of ±
When the difference is 2 or more, the level becomes high, and when the difference is within ± 1, the level becomes low.

By outputting the error signal ERR to the outside of the AD converter 10, the quality of the AD converter 10 can be easily determined. Also, the trigger signal T
Since RIG indicates the timing at which the digital signal D <m−1: 0> changes, the trigger signal TRIG is output to the outside, and data is taken in at the timing of the trigger signal TRIG which is relatively slower than the clock signal. AD converter 1 even if it is an inexpensive evaluation system
Pass / fail of 0 can be determined.

The number of bits of the digital signal D <m-1: 0> output from the ADC unit 12 is not limited at all. Further, the counter 14 outputs the reset signal RESE
By T, it may be set to a predetermined value instead of 0. Also, a trigger signal TRIG and an error signal ER
The polarity of R and the reset signal RESET is not limited at all, and may be changed as needed. In the present invention, the counter 14 is an up-counter, and the trigger signal TRIG output from the comparison circuit 16 is a digital signal D <m−
1: 0> and the expected output value CO <m−1: 0> indicate whether the difference is +1 or not.
And the trigger signal TRIG is D <m
The difference between the value of -1: 0> and the value of CO <m-1: 0> is -1.
May be indicated.

Next, the operation of the AD converter 10 will be described.

FIG. 2 is a timing chart of one embodiment showing the operation of the AD converter of the present invention. This timing chart shows the operation of the AD converter 10 when the ADC unit 12 has a monotonic failure. In the case of the present embodiment, the digital signal D <m−1: 0> = 3 (decimal number)
When the analog signal Ain having the voltage level corresponding to the input is input, the digital signal D <m−
It is assumed that 1: 0> = 4 (decimal number) is output.

As shown in the timing chart of the illustrated example, first, the reset signal RESET is set to the high level, and the AD converter 10 is reset.

As a result, the counter 14 is initialized,
The count value is set to 0 (decimal number), that is, the expected output value CO <m−1: 0> = 00... 000 (binary number). Also, the analog signal Ain is the digital signal D
<M−1: 0> = 0 (decimal number), and the ADC unit 12 outputs a digital signal D <
m-1: 0> = 00... 000 (binary number) is output. Note that the clock signal CLK is always input even during the reset period.

Subsequently, the reset signal RESET is set to the low level, and the reset of the AD converter 10 is released.

After the reset is released, a ramp whose voltage level changes so that the value of the converted digital signal D <m-1: 0> increases by one every four clocks of the clock signal CLK as the analog signal Ain. Waves are input. That is, as shown in the timing chart of FIG. 7, the analog signal Ain is converted into the digital signal D <m-1: 0> at the rising timing of the first, fifth, ninth,... = 0, 1, 2, ... (10
Base) voltage level.

In response, the ADC unit 12
The analog signal Ain is sampled at the first rising timing A of the clock signal CLK after the reset release, and the digital signal Din is sampled at the rising timing B of the clock signal CLK following the sampled clock signal CLK.
<M-1: 0> = 00 ... 000 (binary number) is output. Note that the digital signal D <m−
1: 0> = 00 ... 000 (binary number),
That state will be maintained.

Thereafter, similarly, the clock signal CLK
At each clock, a digital signal D <m-1: 0> corresponding to the voltage level of the analog signal Ain one clock before is output. That is, as shown in the timing chart of FIG. 11, the digital signals D <m−1: 0> are respectively set at the rising timings of the second, sixth, tenth,... <M-1:
0> = 00 ... 00000, 00 ... 001, 00 ... 010, ...
(Binary number).

Here, the digital signal D is output from the ADC unit 12 at the rising timing C of the clock signal CLK.
When <m−1: 0> = 00... 001 (binary number) is output, the comparator 16 outputs a digital signal D <m−1: 0.
> = 00... 001 (binary number) and the expected output value CO <m−
It is detected that the difference from 1: 0> = 00... 000 (binary number) is +1 and the trigger signal TRIG goes high at the same falling timing of the clock signal CLK.

When the trigger signal TRIG goes high, the counter 14 counts up at the next rising timing D of the clock signal CLK, and the output expected value C
O <m-1: 0> = 00... 001 (binary number).

Output expected value CO <m-1: 0> = 00... 0
01 (binary number), the comparison circuit 16
Digital signal D <m−1: 0> = 00... 001 (binary number) and expected output value CO <m−1: 0> = 00.
It is detected that the difference from (binary number) is 0, that is, both values are the same, and the trigger signal TRIG becomes low level at the falling timing E of the same clock signal CLK.

The digital signal D <m-1: 0> = 0
Trigger signal TRI when 0 ... 010 (binary number)
The operation of G is the same as above.

Here, the digital signal D is output from the ADC unit 12 at the rising timing G of the clock signal CLK.
When <m−1: 0> = 00... 100 (binary number) is output, the comparator 16 outputs a digital signal D <m−1: 0.
> = 00... 100 (binary number) and expected output value CO <m−
It is detected that the difference from 1: 0> = 00... 010 (binary number) is ± 2 or more, and the error signal ERR goes high at the same falling timing of the clock signal CLK.

By outputting a high level as the error signal ERR, it can be easily determined that this sample (evaluation chip) has no monotonicity. That is, since the error signal ERR is output to the outside of the AD converter 10, by monitoring the error signal ERR outside, the monotonicity of the AD converter can be reduced before a huge number of digital codes are processed by the controller. The determination can be made easily, thereby significantly improving the test efficiency.

In the example shown in the timing chart of FIG. 3, an example of a sample having no monotonicity has been described. However, in the case of a sample having no problem with monotonicity, the timings C, D, and E in FIG. Digital signal D <m−1: 0> shown in FIG.
= 00... 001 (binary number) is the same operation as the digital signal D <m which is the maximum value of the digital code.
It is repeated until -1: 0> = 11... 111 (binary number).

As described above, the trigger signal TRIG
Represents the transition point of the digital signal D <m−1: 0>, and thus the value of the output expected value CO <m−1: 0> output to the outside is changed by the timing of the trigger signal TRIG also output to the outside. In this case, the data acquisition rate to the controller can be reduced, and even if the evaluation system is inexpensive, the characteristic value of a sample whose conversion rate (frequency of the clock signal CLK) is high can be evaluated. It can be carried out. Also, the trigger signal TR
Only IG is taken into the controller and trigger signal TR
Similar characteristics can be evaluated by a method of calculating the expected output value by counting the number of IG inputs.

Next, another embodiment of the AD converter of the present invention will be described.

FIG. 3 is a schematic diagram showing the configuration of another embodiment of the AD converter of the present invention. Here, the AD converter 20 shown in the figure further includes a DAC (digital-analog converter) unit 22 of n (n> m) bits and an n-bit counter 24 as compared with the AD converter 10 shown in FIG. And the expected output value CO <m−1: 0>
Instead of digital signals Ain <n-1: 0> and D
The only difference is that <m-1: 0> is output to the outside.

The AD converter 20 internally generates a test analog signal and supplies it to the ADC unit 12. The m-bit ADC unit 12
, M-bit counter 14, comparison circuit 16, AN
D gate 18, n-bit DAC unit 22, n
And a bit counter 24. The counter 14, the comparison circuit 16, the AND gate 18, the DAC unit 22, and the counter 24 form a test circuit of the ADC unit 12.

In the illustrated AD converter 20, the counter 24 counts in synchronization with the clock signal CLK, and counts the counted value as a digital signal A <n-1: 0.
Output as>. This digital signal A <n-1: 0>
Are supplied to the DAC unit 22 and output to the outside of the AD converter 20. Note that the digital signal A <n−1: 0> is initialized by a reset signal RESET, and is set to, for example, 0 (decimal number).

Subsequently, the DAC unit 22 synchronizes with the clock signal (converted clock) CLK to
Is converted into an analog signal Ain. Analog signal Ain after conversion
Is supplied to the ADC unit 12. The structure of the DAC unit 22 is not limited at all, and any conventionally known one can be used. However, it is preferable that the DAC unit 22 has higher bit precision than the ADC unit 12.

In the illustrated AD converter 20, the counter 24 is initialized by the reset signal RESET.
For example, digital signal A <n-1: 0> = 0 (decimal number)
Is set to

After the reset is released, the value of the digital signal A <n-1: 0> output from the counter 24 increases by one in synchronization with the clock signal CLK. In the DAC unit 22, the counter 2 is synchronized with the clock signal CLK.
The digital signal A <n-1: 0> supplied from 4 is converted to an analog signal Ain. That is, an analog signal Ain whose voltage level increases as the value of the digital signal A <n−1: 0> increases one by one is generated.

The analog signal Ain generated by the DAC unit 24 is supplied to the ADC unit 12 to be tested, and the test is performed in the same manner as in the case of the AD converter 10 shown in FIG. Digital signal D <
By outputting the digital signal A <n−1: 0> to the outside, the digital signal A <n−1: 0> is output.
>, The voltage level of the analog signal Ain corresponding to the value of the digital signal D <m−1: 0> can be known.

In the examples shown in FIGS. 1 and 3, circuits and connections during normal operation, circuits for switching between normal operation and test operation, and the like are omitted for simplification of description.
Further, in the example of FIG. 1, the digital signal D <m during normal operation
-1: 0> may be output to the outside, or may be used in another internal circuit. In the example of FIG. 3, the analog signal Ain during the normal operation may be input from the outside, or may be supplied from another internal circuit.

The AD converter of the present invention is basically as described above. As described above, the AD converter according to the present invention has been described in detail. However, the present invention is not limited to the above-described embodiment, and various modifications and changes may be made without departing from the gist of the present invention. .

[0046]

As described in detail above, the AD of the present invention
The converter converts the analog signal into a digital signal, generates an expected output value of the digital signal according to the voltage level of the analog signal, compares the digital signal with the expected output value, and determines that the difference between the two is ± 2. An error signal indicating whether or not this is the case is output. Thus, according to the AD converter of the present invention, it is possible to easily evaluate the monotonicity only by monitoring the error signal. Therefore, the test cost can be reduced while the test efficiency can be improved. In addition, the AD of the present invention
According to the converter, by using the trigger signal, the sample can be evaluated at a high sampling rate even with an inexpensive evaluation system, so that the test cost can also be reduced.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of an embodiment of an AD converter according to the present invention.

FIG. 2 is a timing chart of an embodiment showing an operation of the AD converter of the present invention.

FIG. 3 is a schematic configuration diagram of another embodiment of the AD converter of the present invention.

FIG. 4 is a conceptual diagram illustrating a configuration of an example of an AD converter evaluation system.

[Explanation of symbols]

 10, 20 AD converter 12 ADC unit 14, 24 counter 16 Comparison circuit 18 AND gate 22 DAC unit 30 Evaluation system 32 Sample 34 Signal generator 36 Controller

Claims (3)

[Claims] A first means for converting an analog signal into an m-bit digital signal; and a second means for generating an expected output value of the digital signal according to a voltage level of the analog signal.
Means for comparing the digital signal with the expected output value and outputting an error signal indicating whether or not the difference between the digital signal and the expected output value is ± 2 or more. An AD converter characterized by the above-mentioned. 2. The apparatus according to claim 1, wherein said third means further outputs a trigger signal indicating whether a difference between said digital signal and said output expected value is +1 or -1. AD converter. 3. The AD converter according to claim 1, further comprising: a fourth means for generating an n (n> m) bit digital signal; and converting the n bit digital signal into an analog signal. Fifth means for converting the analog signal converted by the fifth means into the first signal.
The A / D converter according to claim 11, wherein the A / D converter is supplied to the means.