JP3265286B2 - A / D converter test equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates also relates to test equipment of the A / D converter (analog-digital converter), in particular A /
A / A which is built in the D converter and has a self-test function for detecting differential nonlinear characteristic errors and miscodes during conversion
About the test equipment D converter.

[0002]

2. Description of the Related Art In electronic systems such as data processing and communication technology, digital circuits are being used instead of analog circuits. Even in such a digital circuit, it is necessary to process an analog signal such as a video signal or an audio signal. In such a case,
An A / D converter is provided on the input side of the digital processing circuit, and converts an analog signal into a digital signal.

[0003] With the recent trend toward higher functionality and higher integration of LSIs, this type of A / D converter is often built in the same chip as the main digital circuit. .

Conventionally, the differential nonlinear characteristic error (DNLE) in the test items of the A / D converter and the miscode which is a coding error at the time of conversion are measured by a common test device due to the nature of the error. It is difficult to test A
This was performed by connecting a dedicated measuring device to the outside of the / D converter.

As described above, providing a dedicated test environment only for an A / D converter built in the same chip as a main digital circuit causes an increase in test time and cost.

As a solution to this, Japanese Patent Application Laid-Open No. 7-15425
The conventional A / D converter test device described in Japanese Patent Application Publication No. 8 (Document 1) includes a self-test device built in the A / D converter, and determines whether or not the A / D converter generates all the codes. Had been tested.

Referring to FIG. 6, which shows a block diagram of a conventional A / D converter test apparatus described in Document 1, this conventional A / D converter is shown.
The test device of the / D converter converts the voltage from 0 V to a predetermined voltage VV (V
Test signal source 300 that supplies an analog test signal VT that varies up to volts) and an n-bit test object that A / D converts the test signal VT and outputs an output code DN that is an n (positive integer) bit digital signal. Known A / D
A converter 20, an n-bit increment counter 1 for simply incrementing the count value at each rising edge of a comparison signal CO, which is an output of a comparison circuit 2 described later, and outputting an increment ID;
The digital signal D of the A / D converter 20 input to the input terminal
A comparison circuit 200 for comparing N with the increment ID of the increment counter 1 input to the second input terminal and outputting a comparison signal CO.

[0008] Next, with reference to FIG. 6, when the operation of the test equipment of the conventional A / D converter 20, first at the beginning of the test, the incremental counter 1 by the reset signal R
00 is reset, and the increment ID which is the count value is set to 00.
Initialize to 0 ... 0. The test signal source 300 supplies the test signal VT to the A / D converter 20. Test signal V
A / D as the voltage of T changes between 0 and VV
If the converter 20 is operating normally, it generates a corresponding output code DN. This output code DN is output from the comparison circuit 2
00 is compared with the increment ID output from the increment counter 100. The voltage of the test signal VT (hereinafter, the test signal VT
Is 0 V, the A / D converter 20 generates 000... 0 as the output code DN, and the increment ID is 000. The output code DN is equal to the increment ID, whereby the comparison circuit 200 outputs an H level (1 level) comparison signal CO corresponding to the match. As a result, the increment counter 100 increments by 1, and sets the increment ID to 000...

The voltage of the test signal VT increases, and the code next to the output code DN of the A / D converter 20, that is, 0
When the level corresponding to 00... 1 is reached, the A / D converter 20 outputs this code 000.
Generate as Under this condition, the output code DN becomes equal to the increment ID again, and the increment counter 100 increments the increment ID again. Thus, each time the increment ID of the increment counter 100 becomes equal to the newly generated output code DN of the A / D converter 20, the increment ID is incremented. Since both the output code DN and the increment ID have an n-bit width, the increment counter 100 causes the A / D converter 20 to generate all of the output codes DN except for the last one. Sometimes, increment IDs 111... 1 are generated.

When the output code DN of the A / D converter 20 matches the increment ID again, that is, the A / D converter 2
When 0 generates all of the output codes DN, the increment counter 100 counts the next one of 111...
As a result, the increment ID becomes 000... 1, and the carry bit CA appearing in the carry output is at the H level, that is, 1
And indicates the existence of an overflow condition.

As described above, it is possible to know that the A / D converter 20 has generated all the output codes DN by setting the carry bit CA, which is the carry output of the increment ID, to one level.

[0012]

The above-described conventional A / D
Test equipment of the converter, but the A / D converter can be detected whether or not to generate all of its code, differential non-linearity error of the determination function is not not have separately outside this determination However, there is a disadvantage that it is necessary to provide a complicated arithmetic unit for calculating an error from an output code.

An object of the present invention does not require any special test equipment to the external test equipment for simple test procedure capable of detecting the differential nonlinearity error and missing codes A / D converter
Is to provide.

[0014]

A test apparatus for an A / D converter according to a first aspect of the present invention converts an externally supplied test signal from analog to digital (hereinafter A / D) and converts the test signal according to the voltage of the test signal. A test of an n-bit A / D converter that outputs one of a set of output codes, which is an n (positive integer) bit digital signal, and a conversion synchronization pulse indicating that a conversion operation has been performed for each conversion operation. For this purpose, in an A / D converter test device built in the same LSI as the A / D converter, the initial value is set to n bits 00... 01 and the rise of a comparison signal which is an output of a comparison circuit described later. An increment counter that simply increases the count value and outputs an increment every time, an output code of the A / D converter input to a first input terminal and an increment of the increment counter input to a second input terminal. Compare both A comparison circuit that outputs a comparison signal when they coincide with each other, and receives the conversion synchronization pulse from the A / D converter, counts the number of the conversion synchronization pulses during two successive comparison signals, and counts the A. The number of conversion operations of the / D converter is obtained and the number of conversion operations is compared with a preset upper limit value and lower limit value of the number of conversion operations to determine whether a differential nonlinear characteristic error (DNLE) is within a predetermined standard range. and a determining DNLE judging circuit, said DNLE decision circuit
Has an initial value set in advance and the A / D converter
Receives the conversion synchronization pulse and counts this conversion synchronization pulse
Then, the number of conversion operations of the A / D converter 20, m (positive
Output the number of conversions of bits)
A / D conversion number for resetting the conversion number in response to supply
A counter and the comparison signal supplied from the comparison circuit.
Delay the signal for a predetermined time and output the delay comparison signal
A delay circuit supplied to the A / D conversion counter, pre Me Initial
A / D is set in response to the supply of the comparison signal.
Acquires and holds the conversion number of the conversion number counter (latch)
A latch circuit that outputs a latch signal of m bits, wherein
Sets the lower limit value of the preset standard range of the latch signal.
And the lower limit register m bits that previously said latch signal
M-bit upper limit that sets the upper limit value of the set standard range
Value register, comparing the latch signal with the lower limit value.
Within the standard that is not less than the lower limit of the latch signal or
Lower limit comparison signals corresponding to non-standard
A lower limit comparing circuit for outputting a signal,
Limit value and is less than the upper limit value of the latch signal.
Corresponds to within the standard or outside the standard that is higher than the upper limit
An upper limit comparing circuit for outputting a limit comparison signals for the lower
Receiving the comparison signal and the upper limit comparison signal,
One of the comparison signal and the upper limit comparison signal is out of the standard.
A pass indicates failure, and a pass indicates otherwise.
A determination circuit for outputting a determination signal .

According to a second aspect of the present invention, a test device for an A / D converter performs A / D conversion of a test signal, and outputs a digital signal of n (positive integer) bits according to the voltage of the test signal.
N-bit A / D that outputs one of the set of output codes and a conversion synchronization pulse indicating that a conversion operation has been performed for each conversion operation
The same L as this A / D converter is used for testing the converter.
In the test device of A / D converter built in SI,
The LSI operates with a second clock synchronized with a first clock for operating the A / D converter, and the bit width corresponding to the resolution is a predetermined number of bits larger than the bit width corresponding to the resolution of the A / D converter. A digital-to-analog (D / A) converter for generating the test signal such that the A / D converter outputs all the codes in order,
A clock generation circuit for generating the first and second clocks, and an initial value is set to 00... 01 of n bits, and the count value is simply increased at each rising of a comparison signal which is an output of a comparison circuit described later. An increment counter for outputting an increment; comparing the output code of the A / D converter input to a first input terminal with the increment of the increment counter input to a second input terminal; A comparison circuit that outputs the conversion synchronization pulse from the A / D converter and counts the number of conversion synchronization pulses in a period of two successive comparison signals after receiving the supply of the conversion synchronization pulse to count the number of conversion operations of the A / D converter Is calculated, and the number of conversion operations is compared with a predetermined upper limit value and lower limit value of the number of conversion operations, and the differential nonlinear characteristic error (DN
LE) for determining whether or not LE is within a predetermined standard range
E determination circuit , wherein the DNLE determination circuit has an initial value.
Is set in advance and the conversion synchronization path from the A / D converter is set.
The conversion synchronization pulse is counted by receiving the supply of
M (positive integer) which is the number of conversion operations of the / D converter 20
Output the number of bits converted and respond to the supply of the delay comparison signal described later.
A / D conversion number counter for resetting the number of conversions
A predetermined comparison signal supplied from the comparison circuit.
The A / D conversion is performed by delaying the time and outputting the delay comparison signal.
A delay circuit supplied to換数counter, set the pre Me Initial value
The number of A / D conversions in response to the supply of the comparison signal.
The conversion number of the counter is fetched and held (latched), and the
A latch circuit for outputting a latch signal of the
M bit to set the lower limit of the preset standard range of the signal
The lower limit register of the latch signal and a preset value of the latch signal.
M-bit upper limit register that sets the upper limit of the standard range
Data, the latch signal and the lower limit, and
Within the standard that is equal to or greater than the lower limit of the
Outputs the lower limit comparison signal corresponding to each non-standard
The lower limit comparison circuit, and the latch signal and the upper limit value.
Comparison and within the standard that is less than the upper limit value of the latch signal
Is the upper limit corresponding to each of the non-standards that are higher than the upper limit
An upper limit comparison circuit that outputs a comparison signal, and the lower limit comparison signal
And the lower limit comparison signal.
And either one of the upper limit comparison signal indicates out of the above standard
Pass / fail judgment signal indicating pass or fail in other cases
And a determination circuit for outputting a signal .

[0016]

[0017]

FIG. 1 is a block diagram showing an embodiment of the present invention. Referring to FIG. 1, an A / D converter test apparatus according to this embodiment shown in FIG. , A test signal source 30 for A / D converting the test signal VT, an output code DN which is a digital signal of n (positive integer) bits, and a conversion synchronization pulse LP indicating that the conversion operation has been performed for each conversion operation. A known A / D converter 20 that outputs a test target and an initial value of n bits 00... 01 and the count value thereof at each rising edge of a comparison signal CO output from a comparison circuit 2 described later Counter 1 that simply increments and outputs an increment ID, the output code DN of the A / D converter 20 input to the first input terminal and the second
A comparison circuit 2 for comparing the increment ID of an increment counter 1 input to an input terminal and outputting a comparison signal CO, and an A / D converter 2
Upon receiving the conversion synchronization pulse LP from 0, the number of conversion synchronization pulses LP between two successive comparison signals CO is counted, and the number of conversion operations of the A / D converter 20 is obtained. A DNLE determination circuit 10 that determines whether a differential nonlinear characteristic error (DNLE) is within a predetermined standard range by comparing with an upper limit value and a lower limit value.

The DNLE determination circuit 10 receives the supply of the conversion synchronization pulse LP from the A / D converter 20, sets the initial value in advance by a register 14 described later, counts the conversion synchronization pulse LP, and counts the conversion synchronization pulse LP. An A / D conversion number counter 11 for outputting a conversion number NC of m (positive integer) bits, which is the number of conversion operations of 20, and resetting the conversion number NC to 0 in response to the supply of a delay comparison signal DCO described later; A delay circuit 12 that delays a comparison signal CO supplied from the comparison circuit 2 by a predetermined time, outputs a delay comparison signal DCO, and supplies the delayed comparison signal DCO to the A / D conversion number counter 11, and a comparison signal CO whose initial value is preset by a register 14 Captures and holds the number of conversions NC of the A / D conversion number counter 11 in response to the supply of data (latch)
Latch circuit 13 for outputting an m-bit latch signal RS
And the lower limit L of m bits of the latch signal RS set in advance
L, an m-bit register 14 for setting an m-bit upper limit UL of a preset latch signal RS, and a lower limit LL of the latch signal RS by comparing the latch signal RS with a lower limit LL. Lower limit comparison signals C corresponding to values within the standard that is equal to or greater than the value LL / nonstandard that is less than the value LL
A comparison circuit 16 that outputs L and a comparison that compares the latch signal RS with the upper limit value UL and outputs an upper limit comparison signal CU that corresponds to a value within the standard that is less than the upper limit value UL and a value that is outside the standard that is equal to or greater than the upper limit value. The circuit 17 and the lower limit comparison signal CL
Circuit which receives the supply of the lower limit comparison signal CL and the upper limit comparison signal UL, and outputs a pass / fail determination signal TG indicating rejection if the one of the lower limit comparison signal CL and the upper limit comparison signal UL is out of specification and passing otherwise. 18.

Next, the operation of the present embodiment will be described with reference to FIG. 1. The test apparatus for an A / D converter according to the present embodiment includes a differential nonlinearity error of the A / D converter 20 and , For detecting a miscode. The test signal source 30 is a test signal V which is an analog input such that the A / D converter 20 outputs all the codes in order.
T is generated, and the voltage of the test signal VT is changed in synchronization with the conversion cycle of the A / D converter.

FIG. 2 is a graph showing the relationship between the time t and the test signal voltage VT when the A / D converter 20 of the test signal source 30 is tested.
Is the A / D converter 2 to be tested, as shown in FIG.
0 is the entire input voltage range to be converted (full scale range:
FSR) has an amplitude in a wider range than the A / D converter 20.
Is generated in such a manner that the n-bit output code DN changes in ascending order from the lowest code to the highest code. At this time, when the A / D converter 20 samples an analog voltage of an arbitrary test signal VT and determines a cycle for determining the output code DN as one conversion cycle T,
The voltage is changed every one conversion period T. As described above, the minimum value of the voltage change of the test signal VT, that is, the step value, is changed by the A / D converter 20 in the minimum step bit corresponding to the resolution, that is, in one least significant bit (1 LSB) unit. All output codes D
N, so that the resolution of the A / D converter 20 (1 L
It is necessary to set a value sufficiently smaller than SB).

In this embodiment, for convenience of explanation, FIG.
As shown in (B), the step value of the test signal VT is set to A
The input signal change is set to 1/3 (hereinafter abbreviated as 1 LSB / 3) of the input voltage change corresponding to 1 LSB change of the output code DN of the / D converter 20, and the test signal VT is changed by one step value every one conversion cycle T. It is assumed that the voltage increases. Assuming that the first voltage value of the test signal VT is A0, the test signal VT has A0, A1, A3,
... rises. Therefore, the value of the output code DN of the A / D converter 20 increases by 1 LSB every three conversion periods 3T. Therefore, each step value Aj (j =
0 to 28), the following relationship holds. Aj = A (j-1) + (1 LSB / 3) (1) For convenience of explanation, the output code DN of the A / D converter 20 to be tested is The number of bits n is 3 bits. Therefore, the FSR is 000 to 111. The required voltage range of the test signal VT of the test signal source 30 ranges from a voltage sufficiently lower than an input voltage corresponding to the minimum value 000 of the FSR (hereinafter referred to as a lower limit value) to an input voltage corresponding to a maximum value 111 (hereinafter referred to as an upper limit value). The voltage will be much higher.

The A / D converter 20 supplies, from the test signal source 30, a test signal VT whose voltage sequentially increases from the low voltage to the minimum step value substantially linearly with time t as shown in FIG. And converts it into a 3-bit output code DN every conversion period T.

Referring to FIG. 3 which is a time chart showing waveforms of various parts when the voltage Aj of the test signal VT is changed, first, the voltage of the test signal VT is A0, A1,.
.. Until the ASR reaches the lower limit corresponding to the minimum value 000 of the FSR, and the A / D converter 20 outputs the value of the output code DN (hereinafter, unless otherwise specified) at every conversion cycle.
N), and outputs a conversion synchronization pulse LP at the same time. Further, as time t elapses, the voltage of test signal VT increases, and when voltage A3 in the third step of test signal VT is supplied, F / A of A / D converter 20 is turned on.
If the value exceeds the lower limit of SR, the A / D converter 20 outputs 001 as the output code DN in a normal case. As described above, in this example, the voltage of the test signal VT increases by one step value each time the time t elapses one conversion cycle T (hereinafter, abbreviated as one conversion cycle T or the like), and thus the A / D conversion is performed. When the operation of the tester 20 is normal, the output code DN increases by 1 LSB at the time when the voltage A6 of the sixth step of the test signal VT is supplied, because the output code DN increases by three LSBs in three conversion cycles 3T. Becomes Thereafter, every three conversion periods 3T, A /
The output code DN of the D converter 20 is 011, 100, 1
01, 110, and 111.

The comparison circuit 2 is a 3-bit known digital comparison circuit in this example, and has a 3-bit output code DN supplied from the A / D converter 20 and a 3-bit output code DN supplied from the increment counter 1. (Hereinafter referred to as “incremental ID” unless otherwise specified), and when they match, the logical level of the comparison signal CO is H level, that is, one level (hereinafter referred to as “one level”) and a fixed width. A positive polarity pulse is generated and output, and when they do not match, a constant potential whose logical level is L level, that is, 0 level (hereinafter referred to as 0 level) is output as the comparison signal CO.

The increment counter 1 is a 3-bit counter in this example, and 001 is set as an initial value. When the comparison circuit 2 outputs a one-level comparison signal CO corresponding to the coincidence between the two input values, that is, the output code DN and the increment ID, the increment counter 1 outputs the comparison signal CO.
, The count value is simply increased at each rising transition to one level, and the increased count value is output as an increment ID. On the other hand, the increment counter 1 does not respond to the supply of the 0 level of the comparison signal CO corresponding to the mismatch of the comparison circuit 2, and therefore the increment ID does not change.

As described above, the test signal VT is increased, and the A / D converter 20 checks that the test signal VT
Output code DN in response to the increase of
To the uppermost code 111. If a conversion error occurs and one of the output codes DN is an erroneous code, that is, a mistake code, this output code DN is the output of the increment counter 1 corresponding to the immediately preceding output code DN at this time. Since this is different from the increment ID, the comparison circuit 2 outputs a comparison signal CO of 0 level corresponding to the mismatch. Therefore, as described above, the increment counter 1 does not respond at all, and the increment ID does not change.

As described above, when the corresponding output code DN is a different code or is not generated by the A / D converter 20 due to a miscode at the time of conversion, the increment counter 1 at that time is used. The value does not match the increment ID, and the comparator 2 outputs a 0 level corresponding to the mismatch.
As a result, the increment counter 1 stops counting and the increment I
D does not increment and remains at its original value. Therefore, the values of the increment IDs at the end of the test are all 1, that is, 1 in this example.
By checking whether or not it is 11, it is possible to know whether or not the normal operation without any miscode has occurred. Also,
If the increment ID at the end of the test is a value other than the above, it is possible to know the output code DN that caused the miscode.

Although not shown, the clock supplied to the A / D converter 20 and the clock supplied to the increment counter 1 are synchronized to ensure that the comparison circuit 2 performs the above-described comparison operation. , The A / D converter 20 and the increment counter 1 are always synchronized.

In the DNLE determination circuit 10, the delay circuit 12
Is the one-level comparison signal C corresponding to the match by the comparison circuit 2.
When O is output, the comparison signal CO is supplied for a predetermined time, that is, the A / D conversion number counter 11 by the latch circuit 13.
And outputs a one-level delay comparison signal DCO in the same manner as described above.

On the other hand, the A / D conversion number counter 11
Upon receiving the one-level conversion synchronization pulse LP output each time the / D converter 20 performs one conversion operation, the number of conversions NC, which is the count value, is increased at each rising transition of the conversion synchronization pulse LP. At this time, the initial value of the conversion number NC is the lower limit value LL set by the register 14, and
This conversion number NC is reset to 0 in response to the supply of the one-level delay comparison signal DCO. Here, for convenience of explanation, the lower limit value LL is set to 1, that is, 001 as described later. Therefore, the conversion number NC is the output code currently being output corresponding to an increase of 1 LSB from the immediately preceding output code DN, except when the output code DN of the A / D converter 20 changes from the first 000 to 001. This is the number of conversion operations of the A / D converter 20 required to change to DN (hereinafter referred to as 1 LSB change corresponding conversion number). If the standard range of the number of conversions corresponding to 1 LSB change is 2 ± 1 as described later, the required number of bits of the A / D conversion number counter 11 is 2 or more, but here it is 3 bits for convenience of explanation.

The latch circuit 13 includes a conversion counter 11
In this example, the comparison circuit 2 is constituted by a 3-bit shift register or the like, and the comparison circuit 2
Each time the level comparison signal CO is output, the value of the conversion number NC immediately before the reset, which is the output of the A / D conversion number counter 11, is captured and held (latched), and the corresponding latch signal RS is output. Therefore, the latch circuit 13 has the A / D
Except when the output code DN of the converter 20 changes from 000 to 001, the number of conversions corresponding to 1LSB change is held,
The corresponding latch signal RS will be output. Also,
When the output code DN changes from 000 to 001, the initial value 001 which is the set lower limit LL is held and the corresponding latch signal RS is output.

Here, the conversion number corresponding to 1LSB change, that is, the corresponding conversion number NC and the standard center value (ideal value) of the latch signal RS will be described. When the conversion operation of the A / D converter 20 is normal, that is, If there is no non-linear characteristic error (DNLE), the conversion operation 3
The number of conversions corresponding to one LSB change is three because the number of conversions changes by one LSB every time. On the other hand, A / D conversion number counter 11
The conversion number NC corresponding to the 1 LSB change conversion number 3 is 2
Becomes Therefore, the standard center value is 2, that is, 010. For convenience of description, the standard range of the conversion number NC corresponding to DNLE is set to the standard center value ± 1, that is, 1 (001) to 3 (01).
Assuming 1), the lower limit LL is 1 or 001, and the upper limit UL is 3 or 011.

The register 14 holds a preset 3-bit lower limit value LL, ie, 001 corresponding to 1 in this example.

The register 15 holds a preset 3-bit upper limit value UL, 011 corresponding to 3 in this example.

The comparison circuit 16 is a 3-bit digital comparison circuit that compares the latch signal RS with the lower limit value LL, and outputs a one-level lower limit comparison signal when the latch signal RS is less than the lower limit value LL. CL, and otherwise outputs a lower limit comparison signal CL of 0 level.

The comparison circuit 17 is a 3-bit digital comparison circuit that compares the latch signal RS with the upper limit value UL. When the latch signal RS is out of the standard that is equal to or higher than the upper limit value UL, the one-level upper limit comparison signal CU, and otherwise outputs a 0-level upper limit comparison signal CU.

The determination circuit 18 is provided with an OR circuit, and receives the supplied lower limit comparison signal CL and upper limit comparison signal CU.
If any one of them is a 1-level indicating non-standard, a 1-level pass / fail determination signal TG indicating rejection is output, and a 0-level pass / fail determination signal TG indicating pass is output otherwise.

Next, when the A / D converter 20 does not always operate normally, the voltage Aj of the test signal VT
The operation of the present embodiment will be described in detail again with reference to FIG. 3 which is a time chart showing the waveforms of the respective parts when is changed. As described above, first, the voltage of the test signal VT sequentially increases, and Until the lower limit corresponding to the minimum value 000 is reached, the A / D converter 20 outputs 00 as the output code DN.
Outputs 0. Further, when the voltage A3 in the third step of the test signal VT is supplied, the FS of the A / D converter 20 is increased.
When the value exceeds the lower limit of R, the A / D converter 20 outputs 001 (hereinafter referred to as an output code DN001 or the like) as the output code DN. The A / D converter 20 outputs a conversion synchronization pulse LP for each conversion operation.

The output code DN of the A / D converter 20 is 00
When the value changes from 0 to 001, the comparison circuit 2 sets the increment ID 001 corresponding to the initial value 001 output from the increment counter 1
And outputs the one-level comparison signal CO in response to a match between the output code DN001 and the output code DN001. In response to the rising transition of the comparison signal CO, the increment counter 1 increases the count value by 1, and outputs an increment ID010. Subsequently, when the output code DN changes from 001 to 010, the comparison circuit 2
Again outputs a one-level comparison signal CO corresponding to the match,
The increment counter 1 further increases the count value by 1, and outputs an increment ID 011.

As described above, when the output code DN of the A / D converter 20 increases by one, the increment ID corresponding to the count value of the increment counter 1 is repeated up to 111, and the comparison circuit 2 outputs the output code DN. Outputs a one-level comparison signal CO every time. As shown in FIG. 3, for convenience of explanation, the voltage A3 (hereinafter abbreviated as voltage A3 or the like) of the third step of the test signal VT, the voltage A7, the voltage A9,.
Output code DN is 1 at voltage A22 and voltage A26, respectively.
Shall increase. That is, the output code DN00
Between 1,010, between 010,011, ..., 110,1
The number of conversions corresponding to each 1 LSB change between 11 is 1, 3, 2,.
・ ・ 4.

As described above, in the A / D conversion number counter 11, the register 14 previously sets the lower limit value 1 as the initial value of the conversion number NC. When the comparison circuit 2 outputs the first one-level comparison signal CO corresponding to the match, that is,
When the A / D converter 20 outputs the output code DN001, the delay circuit 12 delays the first comparison signal CO by a predetermined delay time and outputs the first delay comparison signal DCO. In response to the supply of the first delay comparison signal DCO, the A / D conversion number counter 11 is reset to 0, and the A / D converter 20
Starts the count operation of the conversion synchronization pulse LP output by Each time the A / D converter 20 performs one conversion operation, the conversion synchronization pulse LP is supplied, and the A / D conversion number counter 11 counts up at each rising transition of the conversion synchronization pulse LP to increase the number of conversions NC. .

The latch circuit 13 has a lower limit value LL1 set in advance as an initial value, and when the comparator circuit 2 next outputs a one-level comparison signal CO corresponding to a match, that is,
When the A / D converter 20 outputs the output code DN010, the value of the conversion number NC is latched immediately before the reset, and
A corresponding latch signal RS is output. In this example, the output code DN001 is output at the voltage A3 of the test signal VT, and the next output code DN010 is output at the voltage A7 of the test signal VT. Therefore, the latch circuit 13 first outputs the output code DN001. First delay comparison signal D
The conversion number NC immediately before resetting by CO, that is, the initial value 1 (001) is latched, and then the output code DN01
The value of the conversion number NC immediately before being reset by the delay comparison signal DCO corresponding to 0 (3 (011)) (hereinafter the output code DN0
10 is abbreviated as NC3), and the corresponding latch signals RS1 and RS3 are output. Similarly, the conversion number NC1 corresponding to the next output code DN011,
... Latch the number of conversions NC4 corresponding to the output code DN111 and the corresponding latch signals RS1, ... RS
4 is output.

The comparison circuit 16 determines the lower limit value LL1 and the latch signal RS1, which is latched every time the comparison signal CO is output.
RS4 are sequentially compared with RS3, RS1,..., RS4, and when these latch signals are equal to or lower than the lower limit value LL1, that is, when the latch signal is 0, a 1-level lower limit comparison signal CL indicating nonstandard is output. In this case, since all the values are equal to or more than the lower limit value LL1, the level 0 is output as the value of the lower limit comparison signal CL.

The comparison circuit 17 determines the upper limit value UL3 and the latch signal RS1, which is latched for each output of the comparison signal CO.
RS4, RS1,..., And RS4 are sequentially compared.
The level upper limit comparison signal CU is output. In this case, since only the latch signal RS4 is equal to or higher than the upper limit value UL3, a one-level upper limit comparison signal CU is output, and the other latch signals RS4 are output.
Since 1, RS3, and RS1 are equal to or less than the upper limit value UL3, 0 level is output as the value of the upper limit comparison signal CU.

Therefore, as described above, the judgment circuit 18
Since an OR circuit is provided, and only the upper limit comparison signal CU corresponding to the latch signal RS4 is at one level indicating non-standard, the latch signal RS4, that is, DNLE only when the upper limit comparison signal CU corresponding to the output code DN111 is supplied. A 1-level pass / fail determination signal TG indicating rejection is output, and in other cases, that is, in the case of RS1, RS2, and RS3, a 0-level pass / fail determination signal TG indicating pass is output.

[0046] In D NLE determination of this embodiment, for testing against the initial value of the initial value i.e. A / D conversion counter 11 is initially set to a latch signal, A /
It is desirable that the initial value of the D-conversion number counter 11 be in a range between a lower limit value LL and an upper limit value UL. In this case, the lower limit register 14 and the upper limit register 1 which can change the set value are used.
5, the lower limit value LL of the register 14 was used as the initial value. The upper limit value UL may be used as the initial value,
Naturally, a value different from the lower limit value and the upper limit value may be used as the initial value.

Further, in the present embodiment, the determination of D NLE is made only as to whether or not it is within the standard. However, the value of the latch signal RS output from the latch circuit 13 is directly read to determine the D NLE. You may make it possible to know it.

Further, when an error code occurs, the value of the increment ID of the increment counter 2 may be directly read to determine which output code DN the error code has occurred.

FIG. 4 is a block diagram of a DNLE determination circuit 10A which characterizes the second embodiment of the present invention. For reference, the DNL of the present embodiment shown in FIG.
The DNLE of the E determination circuit 10A according to the first embodiment described above.
The difference from the judgment circuit 10 is that the lower limit and upper limit comparison circuit 1
Instead of 6 and 15, the latch signal RS and the lower limit set value LL
The lower limit comparison signal CL of 0 level when the comparison result is out of specification
B, and a lower limit comparator circuit 17A that outputs a 0-level upper limit comparison signal CUB when the comparison result between the latch signal RS and the upper limit set value UL is out of specification. , NAND circuit, and outputs a 1-level pass / fail judgment signal TG indicating rejection when one of the supplied lower limit comparison signal CLB and upper limit comparison signal CUB is 0 level indicating non-standard. And
In other cases, the pass / fail judgment signal T of 0 level indicating a pass.
It is provided with a determination circuit 18A that outputs G.

The operation of this embodiment is based on comparison signals CLB,
The first embodiment is the same as the first embodiment except that the polarity of the CUB is different. However, in a general LSI, as is well known, the NOR circuit and the NAND circuit are configured on the chip rather than the OR circuit and the AND circuit. In general, there is an advantage that designing and manufacturing are easy.

Next, referring to FIG. 5, which shows a third embodiment of the present invention in which components common to those of FIG. The present embodiment is different from the above-described first embodiment in that the A / D converter 20 is built in the LSI having the A / D converter 20 to be tested instead of the external test signal source 30. And operates at a clock CK1 synchronized with the operation clock CK2 of the A / D converter 20. The resolution is higher than the resolution (accuracy) of the A / D converter 20, that is, the bit width is larger by a predetermined number of bits, for example, 2 bits, and the A / D converter 20 A digital-to-analog converter (D / A converter) 40 that generates a test signal VT that is an analog input that outputs all codes in order.
And a clock generation circuit 50 for generating clocks CK1 and CK2.

In this embodiment, a D / A converter as a test signal source is built in the same LSI as the A / D converter to be tested, so that an external test signal source becomes unnecessary and the same clock generator is used. Since each operation clock is supplied from, it is easy to synchronize the change of the test signal voltage, and if the environment such as power supply and signal input / output necessary for the actual operation of the LSI is provided, complete self test can be performed. There is an advantage that it becomes.

[0053]

As described above, according to the present invention, the test equipment of the A / D converter of the present invention, 00 ... 0 n-bit initial values
An increment counter that simply increments the count value at each rise of the comparison signal and outputs an increment; a comparison circuit that compares the output code with the increment and outputs a comparison signal when the two coincide with each other; The number of conversion synchronization pulses during the period of the two comparison signals is counted to determine the number of conversion operations of the A / D converter. The number of conversion operations is compared with a preset upper limit value and lower limit value, and the differential nonlinear characteristic error ( DNLE) is included in a predetermined standard range, so that the differential nonlinear characteristic error (DNLE) can be obtained by merely controlling the voltage of the test signal VT of the A / D converter.
And an error code can be tested, and the test procedure can be simplified.

The DNLE determination has the effect that the determination of the test result is facilitated by making the determination signal binary, so that the test time can be shortened and the cost associated with the test can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a test device for an A / D converter according to the present invention.

FIG. 2 is a characteristic diagram showing output characteristics of the test signal source of FIG.

3 is a flowchart showing an example of our <br/> Keru operation test equipment of the A / D converter of this embodiment.

FIG. 4 is a block diagram showing a DNLE determination circuit which characterizes a second embodiment of the A / D converter test apparatus of the present invention.

FIG. 5 is a block diagram showing a third embodiment of the test device of the A / D converter according to the present invention.

FIG. 6 is a block diagram illustrating an example of a conventional A / D converter test apparatus.

[Explanation of symbols]

 1,100 Increment counter 2,16,17,200,16A, 17A Comparison circuit 10 DNLE judgment circuit 11 A / D conversion number counter 12 Delay circuit 13 Latch circuit 14,15 Register 18,18A Judgment circuit 20 A / D converter 30,300 test signal source

Claims (4)

(57) [Claims] A test signal supplied from outside is converted from analog to digital (hereinafter, A / D), and a set of output codes of a set of n (positive integer) bit digital signals is generated in accordance with the voltage of the test signal. An A / D built in the same LSI as this A / D converter to test an n-bit A / D converter that outputs one and a conversion synchronization pulse indicating that a conversion operation has been performed for each conversion operation In the test apparatus for the converter, an increment counter that sets the initial value to n bits 00... 01 and simply increases the count value at each rising edge of a comparison signal output from a comparison circuit described later and outputs an increment; A comparison circuit that compares the output code of the A / D converter input to one input terminal with the increment of the increment counter input to a second input terminal, and outputs a comparison signal when the two coincide with each other; D Upon receiving the supply of the conversion synchronization pulse from the converter, the number of the conversion synchronization pulses in the period of the two successive comparison signals is counted to determine the number of conversion operations of the A / D converter, and the number of conversion operations is determined in advance. The differential nonlinear characteristic error (DN) is compared with the set upper limit value and lower limit value of the number of conversion operations.
LE) for determining whether or not LE is within a predetermined standard range
An E decision circuit , wherein the DNLE decision circuit sets an initial value in advance and the A
Receiving the conversion synchronization pulse from the / D converter
The conversion synchronization pulse is counted and the conversion of the A / D converter 20 is performed.
Outputs the number of conversions of m (positive integer) bits, which is the number of operations
The conversion number is reset in response to the supply of a delay comparison signal described later.
An A / D conversion number counter to be set, and a comparison signal supplied from the comparison circuit for a predetermined time.
Output the delay comparison signal and delay the A / D conversion number
A delay circuit supplied to the counter, set the pre Me initial value before in response to the supply of the comparison signal
The conversion number of the A / D conversion number counter is captured and held.
(Latch) latch circuit that outputs an m-bit latch signal
Path and the lower limit of a preset standard range of the latch signal.
And an upper limit value of a predetermined range of the latch signal.
An upper limit register of m bits to be determined, comparing the latch signal with the lower limit,
Within the specification that is equal to or greater than the lower limit or less than the lower limit
Output the lower limit comparison signal corresponding to each
Limit comparison circuit, compares the latch signal with the upper limit value,
Within the specification that is less than the upper limit value or more than the upper limit value
Output the upper limit comparison signal corresponding to each
Come receiving a limit comparator circuit, the lower limit comparison signal and the supply of the upper comparison signal
One of the lower limit comparison signal and the upper limit comparison signal is
Fail to indicate out of specification or pass in other cases
Test apparatus of the A / D converter, characterized in Rukoto a judging circuit for outputting a pass or fail judgment signal indicating that. 2. The lower limit comparison circuit and the upper limit comparison circuit respectively output the lower limit comparison signal and the upper limit comparison signal of a logic 1 level when the respective lower limit comparison signals are out of the standard. and one test device of the a / D converter of claim 1, characterized in that it comprises an oR circuit for outputting the pass or fail judgment signal of a logic level 1 when the logic level 1 of the upper comparison signal. 3. The lower limit comparison circuit and the upper limit comparison circuit respectively output the lower limit comparison signal and the upper limit comparison signal at a logical 0 level when the respective lower limit comparison signals are out of the standard. and test device of the a / D converter according to claim 1, further comprising a N the aND circuit for outputting the pass or fail judgment signal of a logic level 1 when any one of the logic level 0 of the upper comparison signal. 4. An A / D conversion of a test signal and a conversion operation for each one of a set of output codes which are n (positive integer) bit digital signals according to a voltage of the test signal. An A / D converter test device built in the same LSI as this A / D converter to test an n-bit A / D converter that outputs a conversion synchronization pulse indicating: Operated by a second clock synchronized with the first clock for operation of the A / D converter, the bit width corresponding to the resolution is higher by a predetermined number of bits than the bit width corresponding to the resolution of the A / D converter, and A digital-to-analog (D / A) converter for generating the test signal so that the A / D converter sequentially outputs all the codes, a clock generation circuit for generating the first and second clocks, , An increment counter that sets the initial value to n bits 00... 01 and simply increments the count value at each rising edge of a comparison signal, which is an output of a comparison circuit described later, and outputs an increment, and an input to a first input terminal. A comparison circuit that compares the output code of the A / D converter with the increment of the increment counter input to the second input terminal, and outputs a comparison signal when the two coincide with each other; and the conversion from the A / D converter. The number of conversion synchronization pulses during the period of two successive comparison signals receiving the supply of the synchronization pulse is counted to determine the number of conversion operations of the A / D converter, and the number of conversion operations is set in advance to the upper limit of the number of conversion operations. A DNLE determination circuit that determines whether the differential nonlinear characteristic error (DNLE) is within a predetermined standard range by comparing the value with the lower limit value , wherein the DNLE determination circuit has an initial value set in advance and the A
Receiving the conversion synchronization pulse from the / D converter
The conversion synchronization pulse is counted and the conversion of the A / D converter 20 is performed.
Outputs the number of conversions of m (positive integer) bits, which is the number of operations
The conversion number is reset in response to the supply of a delay comparison signal described later.
An A / D conversion number counter to be set, and a comparison signal supplied from the comparison circuit for a predetermined time.
Output the delay comparison signal and delay the A / D conversion number
A delay circuit supplied to the counter, set the pre Me initial value before in response to the supply of the comparison signal
The conversion number of the A / D conversion number counter is captured and held.
(Latch) latch circuit that outputs an m-bit latch signal
Path and the lower limit of a preset standard range of the latch signal.
And an upper limit value of a predetermined range of the latch signal.
An upper limit register of m bits to be determined, comparing the latch signal with the lower limit,
Within the specification that is equal to or greater than the lower limit or less than the lower limit
Output the lower limit comparison signal corresponding to each
Limit comparison circuit, compares the latch signal with the upper limit value,
Within the specification that is less than the upper limit value or more than the upper limit value
Output the upper limit comparison signal corresponding to each
Come receiving a limit comparator circuit, the lower limit comparison signal and the supply of the upper comparison signal
One of the lower limit comparison signal and the upper limit comparison signal is
Fail to indicate out of specification or pass in other cases
Test apparatus of the A / D converter, characterized in Rukoto a judging circuit for outputting a pass or fail judgment signal indicating that.