JP4525706B2 - A / D conversion circuit test method - Google Patents

Description

The present invention relates to test methods of the A / D converter for converting the analog voltage signal into numerical data.

  Conventionally, as a typical A / D conversion circuit, a double integration type shown in FIG. 5, a successive approximation type shown in FIG. 6A, a parallel type shown in FIG. Non-patent document 1).

  Among these, as shown in FIG. 5, the double integration type A / D conversion circuit 101 includes an integration circuit 110 mainly composed of an operational amplifier, and a capacitor C constituting the integration circuit 110 is replaced with A After charging (integrating the input voltage Vin) for a predetermined time set by the input voltage Vin to be / D converted, the input voltage Vin is switched to the reference voltage Vref to discharge at a constant discharge rate. Further, the comparison circuit 112 detects the timing at which the output of the integration circuit 110 exceeds a preset threshold voltage (for example, 0 V) by this discharge.

  Then, the switch control circuit 114 controls the operation of the counter 116 based on the output of the comparison circuit 112 and the switching timing of the applied voltage to the integration circuit 110, and the input voltage Vin is applied to the integration circuit 110. A count value obtained by counting the charge period and a count value obtained by counting the discharge period from when the reference voltage Vref is applied to the integration circuit 110 until the output of the comparison circuit 112 is switched are obtained. Then, A / D conversion data is obtained from the ratio between these two count values.

  That is, the charging voltage of the capacitor C is an average value of the input voltage Vin during the charging period, and the length of the discharging period is proportional to the charging voltage, so that the A / D conversion data of the input voltage Vin is calculated from the ratio of these count values. Is obtained. In the case of the double integration type A / D conversion circuit 101, the length obtained by adding the discharge period required when the maximum value of the input voltage Vin is applied and a certain charge period is one A / D conversion. (The lower limit value of the sampling period).

  Next, as shown in FIG. 6A, the successive approximation A / D conversion circuit 102 includes a resistor ladder 120 in which resistors are connected in a ladder shape, and a switch unit 122 that switches the connection state of the resistor ladder 120. A comparison circuit 124 that compares the comparison voltage Vref and the input voltage Vin with each other as a comparison voltage Vref is provided as a divided voltage of the voltage divider circuit formed by the resistance ladder 120 depending on the on / off state of the switch unit 122.

  In the successive approximation A / D converter circuit 102 configured as described above, the switch unit 122 is set so that 1/2 of the full scale becomes the comparison voltage Vref (1), and the first comparison is executed. When the input voltage Vin is larger than the voltage Vref (1), the switch unit 122 is set so that 1/4 of the full scale becomes the new comparison voltage Vref (2), and the second comparison is executed. On the other hand, when the comparison voltage Vref is larger than the input voltage Vin, the switch unit is set so that a value obtained by adding 1/4 of the full scale to the current comparison voltage Vref (1) becomes a new comparison voltage Vref (2). 122 is set and the second comparison is executed.

  Thereafter, when the input voltage Vin is larger than the comparison voltage Vref (k) in the k-th comparison result, a new value obtained by adding 1 / 2k + 1 of the full scale to the previous comparison voltage Vref (k-1) is new. The switch unit 122 is set so that the comparison voltage Vref (k + 1) becomes the same and the (k + 1) th comparison is executed. When the comparison voltage Vref (k) is larger than the input voltage Vin, the current comparison voltage Vref (k) is full. The switch unit 122 is set so that the sum of 1 / 2k + 1 of the scale becomes the new comparison voltage Vref (k + 1), and the (k + 1) th comparison is executed.

Finally, numerical data corresponding to the state of the switch unit 122 (position where the switch is closed) is output as A / D conversion data.
That is, in the successive approximation A / D conversion circuit 102, it is necessary to repeat the comparison operation as many times as the number of bits representing A / D conversion data. Further, since the time required for setting the switch unit 122 and the time from when the input is set by the comparison circuit 124 to when the output is determined is the comparison time required for one comparison operation, this Multiplying the comparison time by the number of repetitions of the comparison operation is the time required for one A / D conversion (the lower limit value of the sampling period).

  Next, as shown in FIG. 6B, when the A / D conversion data is represented by m bits, the parallel A / D conversion circuit 103 sets the full scale (input range of the input voltage Vin) to n = 2m or the like. A voltage dividing unit 130 that generates a divided comparison voltage, and a comparison unit 132 that includes n comparison circuits CM1 to CMn that respectively compare the comparison voltage at each voltage dividing point of the voltage dividing unit 130 with the input voltage Vin. I have.

In this parallel A / D conversion circuit 103, based on the outputs of the comparison circuits CM1 to CMn constituting the comparison unit 132, numerical data corresponding to the position of the comparison circuit with the matching voltage is output as A / D conversion data. To do. That is, in the parallel A / D conversion circuit 103, the time from when the input voltage Vin is set to the comparison circuits CM1 to CMn until the output is determined is the time required for one A / D conversion (the lower limit of the sampling period) Value) and operates at high speed.
CQ Publisher, Basic Knowledge of Computer Terminology, [online] [Search April 11, 2005], Internet <URL: http://www.cqpub.co.jp/try/kijidb/yougo/ju.htm>

  Incidentally, each of these conventional A / D conversion circuits 101 to 103 includes a comparison circuit that receives the input voltage Vin, and when the A / D conversion circuits 101 to 103 are tested, It must be verified that it operates normally in the entire voltage range of the input voltage Vin.

  Specifically, when the A / D conversion circuits 101 to 103 output m-bit A / D conversion data, the input voltage Vin is changed stepwise by 1/2 m of its full scale, and each time A / D conversion circuits 101 to 103 output A / D conversion data. It is necessary to repeat the procedure of checking whether or not the magnitude of the input voltage Vin given to the D conversion circuits 101 to 103 matches the magnitude of the A / D conversion data obtained from the A / D conversion circuits 101 to 103. .

  Therefore, as the A / D conversion circuits 101 to 103 have higher resolution (the number of bits m is increased), the number of voltage steps 2m to be tested increases exponentially. Therefore, in order to test the A / D conversion circuits 101 to 103, there is a problem that an extremely high-precision and expensive evaluation device that changes the voltage with a resolution higher than that of the A / D conversion circuits 101 to 103 is required. was there.

  In particular, in the double integration type A / D conversion circuit 101 and the successive approximation type A / D conversion circuit 102, the time required for one A / D conversion (the lower limit value of the sampling period) is large as described above. When the number of tests (the number of voltage steps to be tested) is increased due to high resolution (multi-bit), the time required for the test becomes enormous.

  The parallel A / D conversion circuit 103 can operate at high speed, but each time the A / D conversion data is increased by 1 bit for high resolution (multi-bit), the number of comparison circuits is doubled. As a result, the circuit scale of the entire A / D conversion circuit 103 is approximately doubled, which is not suitable for high resolution.

  In addition, today, A / D conversion circuits are one of the important circuits that are essential in large-scale LSIs (system LSIs), and as the performance of system products increases, the A / D conversion circuits are more highly resolved ( Multi-bit). As a result, the ratio of the test time of the A / D conversion circuit to the test time of the entire LSI becomes high, and the labor and cost required for the test of the A / D conversion circuit hinder the productivity and cost reduction of the LSI. There was also a problem that was a major factor.

The present invention aims to to solve the above problems, to provide test methods for A / D converting circuit for realizing a high resolution (multibit) short and low-cost testing of the A / D converter circuit And

In order to achieve the above object, the invention according to claim 1 is characterized in that a ring delay circuit formed by connecting delay units for delaying a pulse signal by a delay time corresponding to an input voltage in a plurality of stages, and a preset value. A latch that counts the number of times that the pulse signal circulates the ring delay circuit during the measured time, and latches the output of each delay unit that constitutes the ring delay circuit at the end of the measurement time. The pulse position in the ring delay circuit is specified, numerical data corresponding to the pulse position is output as lower-order data of A / D conversion data, and the output of the lap counter is latched at the end of the measurement time Te and a coding circuit for outputting as the upper data of the a / D conversion data a / D converter (pulse using a so-called ring delay line A rolled-type A / D converter circuit) test method, the measurement time or by supplying the AD conversion circuit and configured to short the test mode setting value than the actual mode setting value set at the time of actual use based on the a / D conversion data obtained by, good for the ring delay circuit, characterized in that to determine the failure.

Here, assuming that the delay time in each delay unit constituting the ring delay circuit is Td and the threshold voltage for inverting the output level of the delay unit is Vth, the delay time Td is expressed by equation (1). However, A and α (= 1.4 to 1.8) are constants depending on the semiconductor process.

（１）式から明らかなように、入力電圧Ｖｉｎが大きいほど、遅延時間Ｔｄが短くなる。

As is clear from the equation (1), the delay time Td is shortened as the input voltage Vin is increased.

  Also, assuming that A / D conversion data (the number of delay unit stages through which the pulse signal has passed) is DT and the measurement time (sampling period) is TS (= 1 / fs), the A / D conversion data DT is expressed by equation (2) expressed.

（２）式から明らかなように、Ａ／Ｄ変換データＤＴは、測定時間ＴＳが長いほど大きな値となり、換言すれば、同じ入力電圧Ｖｉｎをより多くの電圧ステップ数で表すことになるため、Ａ／Ｄ変換の分解能が向上する。

As apparent from the equation (2), the A / D conversion data DT has a larger value as the measurement time TS is longer. In other words, the same input voltage Vin is expressed by a larger number of voltage steps. The resolution of A / D conversion is improved.

  For this reason, in the pulse delay type A / D conversion circuit, the resolution of A / D conversion data decreases even when the measurement time is changed to a test mode setting value (during test) shorter than the actual mode setting value (during actual use). By just doing (the number of bits is reduced), A / D conversion is not disabled, and A / D conversion can always be executed normally.

That is, in the present invention, the test of the A / D conversion circuit is performed in a state where the measurement time is shortened and the resolution of the A / D conversion data is lowered compared with the actual use. For this reason, an inexpensive evaluation apparatus that generates a test input voltage can be used, and the test can be performed at a low cost .

Further, in the pulse delay type A / D converter circuit that includes a number of turns counter and-ring delay circuit, instead of the circulation-number counter ring delay circuit, a pulse delay circuit comprising a plurality of stages connected in cascade delay units When the number of bits of the A / D conversion data is constant compared to the pulse delay type A / D conversion circuit used, a delay unit that constitutes a ring delay circuit every time the number of bits of the circulation counter is increased by 1 bit The number of delay units can be reduced to ½, and the number of delay units can be significantly reduced as compared with the pulse delay circuit. In addition, the test mode setting value, which is the measurement time during the test, only needs to be long enough for the pulse signal to make one round of the ring delay circuit.

Therefore, according to the present invention, all of the delay units constituting the-ring delay circuit, not only it can be tested in a state of lowering the resolution of the A / D conversion data, the time required for testing of one delay unit Since both the (test mode setting value) and the number of delay units that require testing are small, the time required for testing can be greatly reduced.

According to a second aspect of the present invention, in the method for testing an A / D conversion circuit according to the first aspect , the frequency counter is operated by a test clock different from the clock from the ring delay circuit. It is characterized by judging whether the frequency counter is good or bad.

In this case, since the circulation counter can be tested independently without depending on the operation of the ring delay circuit, it is possible to easily and reliably determine whether the circulation counter is good or bad.
According to a third aspect of the present invention, in the A / D conversion circuit testing method according to the first or second aspect of the present invention, the flip-flops constituting the circuit counter and the encoding circuit are connected in series. Based on the A / D conversion data acquired by operating the A / D conversion circuit by setting the value of the flip-flop to a desired value from the outside by the scan path, and the encoding counter It is characterized by judging whether the circuit is good or bad.

In this case, the output of the ring delay circuit or the circulation counter can be taken out via the scan path, or the input of the encoding circuit can be set via the scan path. Since the encoding circuits can be tested independently without depending on other operations, the test can be easily and reliably performed .

Reference examples and embodiments of the present invention will be described below with reference to the drawings.
[Reference example]
FIG. 1 is an overall configuration diagram of an A / D conversion circuit 1 as a reference example .

As shown in FIG. 1, the A / D conversion circuit 1 cascades M (= 2 ^{p + q} , p and q are positive integers) stages of delay units DU that output an input pulse Pin after being delayed by a predetermined delay time. The arrival position of the input pulse Pin in the pulse delay circuit 10 is detected (latched) at the rising timing of the sampling clock CKS and the pulse delay circuit 10 configured by the connection, and the detection result is represented by the input pulse Pin It is composed of a latch & encoder 12 as an encoding circuit that converts and outputs digital data DT of a predetermined bit representing the number of stages from which the delay unit DU has passed.

Each delay unit DU constituting the pulse delay circuit 10 is composed of a gate circuit such as an inverter. As shown in FIG. 1B, the i × 2 ^p +1 stage (where i = 1, 2,... The delay unit DU of (N−1, N = 2 ^q ) is configured as a two-input OR circuit that receives the output of the preceding delay unit DU and the input pulse Pin, and the other delay unit has one input. Is configured as a buffer circuit.

In the figure, the numerical values indicated by (1), (2),... Indicate the number of stages of the delay unit DU, and in the following, the kth delay unit is indicated by DU (k). Each group of 2 ^p consecutive delay units DU starting from the first-stage delay unit DU (1) or the two-input delay unit DU (i × 2 ^p +1) is represented as a delay block Bi (i = 0). ~ N-1).

Further, an input voltage Vin to be A / D converted is applied as a drive voltage to each delay unit DU via the buffer 14 and the like. Accordingly, the delay time of each delay unit DU is a time corresponding to the voltage level of the input voltage Vin, and the input pulse Pin in the pulse delay circuit 10 within one cycle of the sampling clock CKS, that is, the sampling cycle (measurement time) TS. The number of delay units DU through which is passed is proportional to the voltage level of the input voltage Vin.

  In the A / D conversion circuit 1 configured as described above, the input pulse Pin is supplied only to the first-stage delay unit DU (1), and the sampling that rises when the sampling period TS elapses after the input pulse Pin is input. When the clock CKS is supplied, the latch & encoder 32 outputs digital data DT representing the voltage level of the input voltage Vin.

  Here, FIG. 2 shows an output change of each delay unit DU when the input pulse Pin is transmitted in the pulse delay circuit 10, and in FIG. 2A, when the input voltage Vin is different, FIG. Shows a case where the sampling periods (measurement times) TS are different.

  As shown in FIG. 2A, when the sampling period TS is constant, the delay time of the input pulse Pin in each delay unit DU is shortened when the input voltage Vin is increased. Since the number of stages of delay units DU through which the input pulse Pin passes in the pulse delay circuit 10 increases and the input voltage Vin decreases, the delay time of the input pulse Pin in each delay unit DU increases. The number of stages of the delay unit DU through which the input pulse Pin passes in the pulse delay circuit 10 during TS is reduced.

  That is, when the sampling period TS is constant, the output (digital data DT) from the latch & encoder 12 changes according to the voltage level of the input voltage Vin, and the digital data DT uses the input voltage Vin as A. / D converted numeric data.

  Further, as shown in FIG. 2B, even if the input voltage Vin is the same, that is, the delay time of the delay unit DU is the same, if the sampling period TS is shortened, the input pulse Pin in the pulse delay circuit 10 during that time. The number of stages of the delay unit DU through which the input pulse Pin passes and the number of stages of the delay unit DU through which the input pulse Pin passes in the pulse delay circuit 10 increases during the sampling period TS.

  In other words, the output (digital data DT) from the latch & encoder 12 encodes the input voltage Vin with a larger number of bits (number of voltage steps) as the sampling period TS becomes longer. The resolution of the digital data DT is improved.

Here, a procedure for testing whether the A / D conversion circuit 1 configured as above is good or bad will be described below.
However, the sampling cycle TS set at the time of actual use is referred to as an actual mode set value TSr, and the mode in which the A / D conversion circuit 1 is operated with the actual mode set value TSr is referred to as an actual mode. The sampling period TS set during the test is referred to as a test mode set value TSt, and a mode in which the A / D conversion circuit 1 is operated with the test mode set value TSt is referred to as a test mode.

The actual mode setting value TSr is set to a time required for the input pulse Pin to pass through all the delay units DU constituting the pulse delay circuit 10 when, for example, the maximum value of the input voltage Vin is applied, The test mode set value TSt is, for example, the time required for the input pulse Pin to pass through all the delay units DU (that is, 2 ^k stages) constituting one block when the maximum value of the input voltage Vin is applied. Is set.

  In the test of the A / D conversion circuit 1, a test voltage generated by a separately prepared evaluation device is supplied to the A / D conversion circuit 1 as the input voltage Vin, and the A / D conversion circuit is used in the test mode. 1 is activated.

At this time, the input pulse Pin is supplied not only to the first-stage delay unit DU (1) but also to all the two-input delay units DU (i × 2 ^p +1).
Then, the digital data DT obtained as the output of the latch & encoder 12 is divided into N pieces of data for each p bit corresponding to each delay block Bi, and the N pieces of p bit data are all sent to the evaluation device. If it matches the magnitude of the test voltage generated (or if it falls within a predetermined expected value width with respect to the magnitude of the test voltage), the A / D conversion circuit 1 at that test voltage Is determined to be good.

This test is repeated for all voltage steps in 2 ^p stages indicated by p-bit data, and the test is completed.
As described above, in the A / D conversion circuit 1 of the present reference example , as the delay unit DU constituting the pulse delay circuit 10, the output of the delay unit DU at the preceding stage or the input directly applied from outside at regular intervals. A two-input delay unit DU having the pulse Pin as an input is inserted, and an input pulse Pin can be input from a position where the two-input delay unit DU is inserted.
When the test of the A / D conversion circuit 1 is performed, the input pulse Pin is simultaneously input to all of the first-stage delay unit DU (1) and the two-input delay unit DU (i × 2 ^p +1), and sampling is performed. The A / D conversion circuit 1 is operated in a test mode in which the cycle TS is shorter than that in the actual mode.

Therefore, according to the A / D conversion circuit 1 of this reference example , the pulse delay circuit 10 and the latch & encoder 12 can be tested for each of the delay blocks B _{0 to} B _N−1 , and each delay Since the tests of the blocks B _{0 to} B _N-1 are performed in parallel, the time required for the test can be greatly reduced as compared with the conventional apparatus.

As a result, in the system LSI incorporating the A / D conversion circuit 1 of this reference example , the test time can be greatly shortened, and the productivity and cost reduction of the system LSI can be achieved.

Note that the evaluation apparatus that generates the test voltage (input voltage Vin) for the test changes the test voltage with at least a resolution higher than the resolution of the A / D conversion data of the A / D conversion circuit 1 to be tested. Need to be able to When attempting to test in the actual mode (same conditions as in actual use), the resolution of the A / D converter circuit 1 becomes a size (1/2 ^{p + q} ) determined by the number of bits p + q of the digital data DT. In addition, an expensive evaluation device is required.

On the other hand, the resolution of the A / D conversion circuit 1 in the test mode is a size (1/2 ^p ) determined by the number of bits p of the delay block Bi, which is significantly lower than the actual mode. Therefore, an inexpensive evaluation apparatus can be used, and the cost required for the test can be reduced.

For example, A / D conversion circuit 1, to convert the input voltage Vin to the 20-bit digital data DT, a pulse delay circuit 10 by a delay unit DU of 2 ²⁰ (approximately 1 million) are configured, each delay It is assumed that the block Bi is composed of 2 ¹⁰ (about 1000, ie, p = q = 10) delay units DU, the actual mode set value TSr is 1 ms, and the test mode set value TSt is 1 μs. Think about the case.

In this case, in the test mode, the time required for one A / D conversion is 1/1000 (= TSt / TSr) in the actual mode, and the number of A / D conversion repetitions required for the test is Since only the number of delay units DU constituting the delay block Bi is required, that is, 2 ¹⁰ times, the total voltage step 2 ²⁰ is about 1/1000 (1/2 ¹⁰ ) as compared with the case where each of the voltage steps 2 ²⁰ is individually tested. Therefore, the entire test time is shortened to about 1/1 million (= 1/1000 × 1/1000).

In this case, an evaluation device having a resolution of the order of 1 μV (1/2 ²⁰ ) is required when testing in the real mode, but 1 mV (1) when testing in the test mode. / 2 ¹⁰ ) An evaluation device having a resolution of the order may be used, that is, an evaluation device having a resolution 1000 times coarser can be used.

Note that if the test mode set value TSt is further shortened (for example, 1/10000 or 1 / 100,000 of the actual mode set value), the resolution of the evaluation apparatus can be made coarser, and 1 in the test mode can be obtained. The time required for each A / D change and thus the time required for the entire test can be further reduced.
[ First Embodiment ]
Next, a first embodiment of the present invention will be described.

FIG. 3 is an overall configuration diagram of the A / D conversion circuit 3 of the present embodiment.
As shown in FIG. 3, the A / D conversion circuit 3 delays an input pulse Pin by a predetermined delay time and outputs 2 ^a delay units DU (a is an integer of about 3 to 10) in a ring shape. By connecting, the ring delay circuit 30 configured as a ring delay line (RDL) capable of circulating the input pulse Pin and the arrival of the input pulse Pin in the ring delay circuit 30 at the rising timing of the sampling clock CKS A latch & encoder 32 that detects (latches) the position, converts the detection result into a-bit digital data indicating the number of stages from the top of the delay unit DU through which the input pulse Pin has passed, and outputs the data I have.

  In the ring delay circuit 30, the first-stage delay unit DU is configured by an AND gate having one input terminal as a starting terminal, and the other input terminal of the first-stage delay unit DU and the last-stage delay unit DU. A ring shape is formed by connecting the output terminal of the unit DU. Further, an input voltage Vin to be A / D converted is applied as a drive voltage to each delay unit DU via the buffer 34 and the like.

  The A / D conversion circuit 3 also includes a b-bit counter 36 that counts according to the operation clock, the output (circulation clock) of the final stage delay unit DU constituting the ring delay circuit 30, or a test supplied from the outside. An OR circuit 35 that supplies any one of the clocks CKT to the counter 36 as an operation clock, and a latch circuit 38 that latches the count value of the counter 36 at the rising timing of the sampling clock CKS.

In the present embodiment, the counter 36 corresponds to a circulation counter, the latch & encoder 32 and the latch circuit 38 correspond to an encoding circuit, and the OR circuit 35 corresponds to a test clock supply circuit.
In the A / D conversion circuit 3 configured as described above, in actual use, the counter 36 is supplied with the circulation clock from the ring delay circuit 30 as an operation clock, and the circulation of the input pulse Pin in the ring delay circuit 30 is performed. Count the number of times.

  The A / D conversion circuit 3 to which the input pulse Pin and the sampling clock CKS that rises when the sampling period TS has elapsed after the input of the input pulse Pin is input to the a bit output from the latch & encoder 32. A + b bits of digital data DT in which the lower bit data representing the voltage level of the input voltage Vin and the b bit count value output from the latch circuit 38 as the upper bit data representing the voltage level of the input voltage Vin are used. Is output.

  In addition, in the A / D conversion circuit 3 to which the test clock CKT is supplied without receiving the input pulse Pin, the counter 36 operates independently regardless of the operation of the ring delay circuit 30.

Here, a procedure for testing whether the A / D conversion circuit 3 configured as above is good or bad will be described below.
However, the sampling period TS set in actual use is called the actual mode set value TSr, and the mode in which the A / D conversion circuit 3 is operated with the actual mode set value TSr is called the actual mode. The sampling period TS set during the test is referred to as a test mode set value TSt, and the mode in which the A / D conversion circuit 3 is operated at the test mode set value TSt is referred to as a test mode.

  Note that the actual mode set value TSr is set to, for example, the time required for the value of the counter 36 to reach the maximum value (the value immediately before overflowing) when the maximum value of the input voltage Vin is applied. The set value TSt is set to a time required for the input pulse Pin to pass through all the delay units DU constituting the ring delay circuit 30 (that is, to make one round of the RDL) when the input voltage Vin is applied.

  In the test of the A / D conversion circuit 3, a test voltage generated by a separately prepared evaluation device is supplied to the A / D conversion circuit 3 as the input voltage Vin, and the A / D conversion circuit is used in the test mode. 3 is operated.

  That is, the input pulse Pin and the sampling clock CKS that rises after the test mode set value (sampling period) TSt has elapsed after the input of the input pulse Pin and the input pulse Pin are input to the first-stage delay unit DU (1). 3 is supplied.

  As a result, if the a-bit lower-order bit data obtained as the output of the latch & encoder 32 matches the magnitude of the test voltage generated by the evaluation device (or predetermined for the magnitude of the test voltage). In the expected value range), the operation of the A / D conversion circuit 3 at the test voltage is determined to be good.

This test is repeated for all voltage steps in the ^2a stage indicated by the a-bit lower bit data. As a result, the operations of the ring delay circuit 30 and the latch & encoder 32 are confirmed.

  Next, the input voltage Vin and the input pulse Pin are turned off, the counter 36 is operated by inputting the test clock CKT, and the sampling clock CKS is input every time the test clock CKT is input, whereby the counter 36 is input. Is output to the latch circuit 38.

As a result, if the b-bit upper bit data obtained as the output of the latch circuit 38 matches the number of input test clocks CKT, the operation of the counter 36 and the latch circuit 38 with the count value is good. Judge. Then, this test is repeated for all the count values of the counter 36 (that is, 2 ^b times), and the test is completed.

  As described above, in the A / D conversion circuit 3 of the present embodiment, the delay unit in which the input pulse Pin passes within the sampling period TS by using a combination of the ring delay circuit 30 and the counter 36 instead of the pulse delay circuit 10. The number of stages of DUs is specified, and the counter 36 can be operated without depending on the ring delay circuit 30 by an external test clock CKT.

  Therefore, according to the A / D conversion circuit 3 of the present embodiment, the ring delay circuit 30 and the latch & encoder 32, the counter 36 and the latch circuit 38 can be individually tested. Reliability can be improved.

Further, in the ring delay circuit 30, the number of delay units DU that require individual tests and the time required for one A / D conversion in the test mode (that is, the test mode set value TSt) are used as reference examples. Compared to the above, the time required for testing can be further shortened, and an inexpensive evaluation device with lower resolution can be used, which greatly reduces the cost required for testing. be able to.

Specifically, if the number of bits of the digital data DT is the same as that of the reference example , the number of delay units DU can be reduced to ½ each time the number of bits of the counter 36 is increased by one bit.

In this embodiment, the input pulse Pin is input only at the first stage. However, as in the case of the reference example , the input pulse Pin can be input from a plurality of locations using the two-input delay unit DU. You may comprise.
[Second Embodiment]
Next, a second embodiment will be described.

FIG. 4 is an overall configuration diagram of the A / D conversion circuit 3a of the present embodiment.
The A / D conversion circuit 3a of the present embodiment differs from the A / D conversion circuit 3 of the first embodiment only in part of the configurations of the latch & encoder 32, the counter 26, and the latch circuit 38. This difference will be mainly described.

  That is, in the A / D conversion circuit 3a, a flip-flop circuit provided for latching the output of the ring delay circuit 30 in the latch & encoder 32a, and a flip-flop provided for latching the output of the counter 36a in the latch circuit 38a. The flip-flop circuits provided for the counting operation in the counter circuit and the counter 36a are all connected in series, so that a so-called scan path is provided.

And these latch and encoder 32a, the latch circuit 38a, the counter 36a in accordance with the mode designation signal TN to specify either a normal mode or a test mode, the normal mode, the latch and encoder 32 in the first embodiment, the latch The circuit 38 and the counter 36 operate in exactly the same way. On the other hand, in the test mode, the data of the flip-flop circuit forming the scan path is shifted bit by bit according to the sampling clock CKS. That is, by supplying serial input data SSI to the scan path, the value of each flip-flop circuit is arbitrarily set from the outside, or the value of each flip-flop circuit is read as serial output data SSO via the scan path. Have been able to.

Here, a procedure for testing whether the A / D conversion circuit 3a configured as above is good or bad will be described below.
First, arbitrary values are set in the flip-flop circuits of the latch & encoder 32a and the latch circuit 38a via the scan path, and the set values and the digital data DT that is the output of the latch & encoder 32a and the latch circuit 38a are set. By comparing, the operations of the latch & encoder 32a and the latch circuit 38a are confirmed.

Thereafter, the same test as in the first embodiment is performed.
That is, in the A / D conversion circuit 3a of this embodiment, the scan path is provided, so that the latch & encoder 32a and the latch circuit 38a can be tested independently without depending on the operations of the ring delay circuit 30 and the counter 36a. Therefore, the reliability of the test can be further improved.

  In this embodiment, the scan path is used to set a value in the latch & encoder 32a and the latch circuit 38a. However, the scan path is used to read the value obtained by latching the output of the ring delay circuit 30 or the counter 36a. It may be used to test the counter 36a without using a test clock.

  Further, in order to test whether the combinational circuit constituting the counter 36a is good or bad, a general scan test, that is, after setting predetermined data in the scan path, actual use for one clock (actual mode operation) is performed. It is obvious that a test method in which the result (combination circuit operation result data) is read again in the scan path and compared with the expected value is effective.

The whole block diagram of the A / D conversion circuit of a reference example . Explanatory drawing which shows operation | movement of an A / D conversion circuit. 1 is an overall configuration diagram of an A / D conversion circuit according to a first embodiment . The whole block diagram of the A / D conversion circuit of 2nd Embodiment . Explanatory drawing which shows the structure of the conventional A / D conversion circuit. Explanatory drawing which shows the structure of the conventional A / D conversion circuit.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1, 3, 3a ... A / D conversion circuit, 10 ... Pulse delay circuit, 12, 32, 32a ... Latch & encoder, 26, 36, 36a ... Counter, 30 ... Ring delay circuit, 35 ... Logical sum circuit, 38, 38a ... Latch circuit, Bi ... Delay block, DU ... Delay unit.

Claims (3)

A ring delay circuit in which a delay unit that delays a pulse signal with a delay time according to an input voltage is connected in a ring form, and the pulse signal circulates around the ring delay circuit during a preset measurement time Rotation counter for counting the number of times, and by latching the output of each delay unit that constitutes the ring delay circuit at the end of the measurement time, the pulse position in the ring delay circuit is specified and the pulse position is supported And an encoding circuit for outputting the numerical data as lower data of the A / D conversion data and latching the output of the circulation counter at the end of the measurement time and outputting it as the upper data of the A / D conversion data. A test method for an A / D converter circuit,
The ring delay circuit is based on A / D conversion data acquired by operating the AD converter circuit by setting the measurement time to a test mode set value shorter than the actual mode set value set in actual use. A method for testing an A / D conversion circuit, characterized by determining whether the product is good or bad.   2. The A / D converter circuit according to claim 1, wherein the circuit counter is judged to be good or bad by operating the circuit counter with a test clock different from the clock from the ring delay circuit. Test method. The A / D conversion circuit is operated by setting the value of the flip-flop to a desired value from the outside by a scan path formed by serially connecting the flip-flops constituting the circulation counter and the encoding circuit. 3. The A / D conversion circuit according to claim 1, wherein whether or not the circulation counter and the encoding circuit are good or bad is determined based on the A / D conversion data acquired in this way. Test method.

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