TWI760191B - Time-to-digital converter - Google Patents

Abstract

A time-to-digital converter, characterized in that the start and end of a timing event are sampled by the buffer delay module to obtain a wide dynamic range. Then the edge detector is used as a bridge to detect a delayed start with a close lag from the stop signal and send it to the Vernier Delay Module for higher rate sampling in order to obtain higher resolution and moderate dynamic range. The entire structure is monitored by a PVT detector to resist the influence of process, voltage, and temperature changes to obtain the required resolution.

Description

time to digital converter

The present invention relates to a time-to-digital converter, and more particularly, to a time-to-digital converter capable of improving environmental interference and having high resolution and wide dynamic range.

With the development of integrated circuits, the sensing information obtained by the sensor is converted into the form of digital code, which can be widely used. Among them, for the time measurement system, the time-to-digital converter (TDC) can represent the sensing information by the time width, and count the time width through the oscillator, so as to convert the sensing information into digital output.

A time-to-digital converter (TDC) is a device used to measure the time interval between two events and convert this analog information into digital code. The input time interval of events is limited by the dynamic range and resolution of the TDC. Therefore, in today's applications (such as radar ranging, time-of-flight, etc.), TDCs with high resolution and wide dynamic range are required.

Traditional time-to-digital converters (TDCs) are buffer delay modules based on digital delay cells with limited propagation delay. In contrast, another time-to-digital converter (TDC) is the vernier delay module, which has good propagation delay but limited dynamic range.

In addition, both the buffer delay module and the vernier delay module are affected by PVT changes. In the related art, time-to-digital conversion requires designing the delay amount of each delay element with high precision. For example, due to process differences or differences in temperature or power supply voltage, the delay amount of the delay elements at all levels varies or varies, so that the time-to-digital conversion is affected by the PVT relation and the required resolution cannot be obtained. Therefore, how to effectively improve the above problems has become a key technology of time-to-digital converters.

The object of the present invention is to provide a time-to-digital converter (TDC) with resistance to PVT variation, using a two-stage system architecture, where the first stage is a buffered delay line to obtain a wide dynamic range, and then an edge detector is used to convert the Delayed start and stop signals are provided to the second-stage vernier delay line for higher resolution, and the entire architecture is monitored by a PVT detector to resist process, voltage, temperature (PVT) variations.

In order to solve the above problem, the present invention is a converter that converts the time difference between the transition timings of the start signal and the stop signal into a digital value, and is characterized in that it includes: a buffer delay module for starting and ending the start signal and the stop signal. sampling and measuring the time difference between the edges of the start signal and the stop signal; an edge detector is used as a bridge to detect the delay start signal in the buffer delay module, the delay between the delay start signal and the stop signal The time is relatively short; the vernier delay module accepts the delay start signal output by the aforementioned edge detector for sampling and measurement at a higher rate. The encoder is used to convert the digital codes of the aforementioned buffer delay module and the vernier delay module into digital codes, so as to be encoded into a format commensurate with the subsequent processing represented by the binary value; and the PVT compensator inputs the clock signal with In monitoring the elements used for delay in the aforementioned buffer delay module, edge detector and vernier delay module, the elements used for delay are made resistant to the influences caused by process, voltage and temperature changes.

A technical feature of the present invention is the use of a two-stage system architecture, where the first stage is a buffered delay line to obtain a wide dynamic range, then delayed start and stop signals are provided to the second stage vernier delay line through an edge detector, To achieve higher resolution, and the entire architecture is monitored by a PVT detector to resist process, voltage, temperature (PVT) variations, it is a high-resolution time-to-digital converter design with an anti-PVT variation mechanism.

In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only Embodiments of some, but not all, of the present invention. However, for the description of the present disclosure, if it is determined that the detailed description makes the embodiments of the present disclosure unclear, the detailed description may be omitted. Portions irrelevant to the description are omitted in order to specifically describe the present disclosure, and the same reference numerals refer to the same elements throughout the specification.

In the embodiments, the same or similar elements will be given the same or similar reference numerals, and repeated descriptions thereof will be omitted. In addition, the features of the different exemplary embodiments may be combined with each other without conflict, and simple equivalent changes and modifications made in accordance with the present specification or the scope of the claims are still within the scope of the present patent.

Please refer to FIG. 1 , which is a block diagram of the time-to-digital converter of the present invention. The time-to-digital converter 100 receives the start signal start and the stop signal stop, and has the function of measuring the time difference (phase difference) of the two signal edges, which is a method of converting the time difference of the transition timing of the start signal start and the stop signal stop into a digital value. converter. The core of the time-to-digital converter 100 includes a buffer delay module 200 , an edge detector 300 and a vernier delay module 400 . The time-to-digital converter 100 also includes an encoder 500 and a PVT compensator 600 .

The start signal start and the stop signal stop are the start and end of the timing event, the event is sampled by the buffer delay module 200, and the time difference between the edges of the start signal start and the stop signal stop is measured; then the edge detector 300 as a bridge will detect a delayed start signal with a close lag to the stop signal stop and send it to the vernier delay module 400 for higher rate sampling for higher resolution and moderate dynamic range . The encoder 500 is used for converting the digital codes of the buffer delay module 200 and the vernier delay module 400 into digital codes.

The core of the time-to-digital converter 100 uses a two-stage system architecture, wherein the first stage is the buffer delay module 200, with the buffer delay module 200 having a lower resolution and a higher dynamic range, sampling to obtain wide dynamic range, then the delayed start signal start and stop signal stop are provided to the vernier delay module 400 in the second stage through the edge detector 300, and the vernier delay module 400 has higher resolution and lower dynamic range to achieve higher resolution.

The input of the PVT compensator 600 is the clock signal clk, where in the illustrated example the PVT compensator 600 generates a 4-bit PVT code Cin[3:0] for automatically adjusting the core (buffer delay) of the time-to-digital converter 100 PVT variation of delay elements in module 200, edge detector 300, and vernier delay module 400).

The buffer delay module 200 will generate a digital code of the sampling timing. In the embodiment of this case, it is assumed that the digital code is a 31-bit thermometer code Q[30:0]. Finally, the encoder 500 converts the 31-bit thermometer code into 5 Bits E[7:3], to encode into a format commensurate with subsequent processing represented by binary values. Likewise, in the vernier delay module 400, the encoder 500 converts the 7-bit thermometer code V[6:0] to E[2:0] to encode into a format commensurate with subsequent processing represented by binary values .

As shown in FIG. 2 , it is a schematic diagram of the buffer delay module 200 of the present invention. The start signal start and the stop signal stop are the start and end of a timing event, and the event is sampled by the buffer delay module 200 . The buffer delay module 200 includes a buffer delay line formed by a multi-stage delay unit 211 connected in series 210 , and a flip-flop 220 corresponding to each stage of the delay unit 211 . The start signal start is applied to the buffer delay line 210 formed by a plurality of delay units 211 connected in series, wherein the outputs (startd1~dm) of each stage of the delay unit 211 are used as the data input to the corresponding flip-flop 220 of the stage, and the stop signal stop is fed to the clock (clk) input of the flip-flop 220 . After each step, the time difference between the rising edges of the start signal start and the stop signal stop decreases until the start signal start (startdi+1) leads the stop signal stop, the output of the flip-flop 220 (Q[0]~Q [N-1]) changes from "1" to '0', as shown in Figure 3.

If each delay unit 211 has a delay value of T1, and the number of delay units 211=N, then the dynamic range DR=N×T1. In this case example, the values considered in this work are T1=28.7ps and N=31, so DR=890ps.

The edge detector 300 is used to detect the delay start signal in the buffer delay module 200, and the delay time between the delay start signal and the stop signal is relatively short. For example, in FIG. 3, the start signal startdi is the signal closest to the stop signal stop. The delay start signal (startdi) will be sent to the vernier delay module 400 for further sampling.

The schematic diagram of the edge detector 300 is shown in FIG. 4 , the edge detector 300 includes a plurality of NOR gates 320 corresponding to the flip-flops 220 of the buffer delay module 200 , and the plurality of NOR gates The output of the NOR gate 320 is connected to an OR gate 330 . One input of each inversion gate 320 passes through a delay unit 310 with a T1 delay, and inputs the inverted Q signal given by the corresponding flip-flop 220 of this stage, and the other input is the output signal Q of the flip-flop 220 of the next stage. This happens only when both inputs are "0", or the OR gate 330 outputs "1", that is, when the delayed start signal (startdi) causes the stop signal stop. Wherein v-start is the output signal of the edge detector 300 , and v-stop is the signal delayed by T1 of the delay unit 310 “stop signal stop”.

As shown in FIG. 5 , it is a schematic diagram of the cursor delay module 400 of the present invention. The vernier delay module 400 includes an upper delay line 410 formed by a multi-stage upper delay unit 411 connected in series, and a lower delay line 420 corresponding to the upper delay line 410 and connected in series by the multi-stage lower delay unit 421, and the corresponding The flip-flops 430 of the delay cells 411, 421 on each stage. The v-start signal output by the edge detector 300 is a given input of the upper delay line 410 , wherein the output of each stage of the upper delay unit 411 is provided to the data input of the flip-flop 430 . The v-stop signal of the edge detector 300 is a given input to the lower delay line 420, where the output of each stage lower delay cell 421 is provided to flip-flop 430 as a clock signal (clk). The vernier delay module 400 propagation delay time value T is the time difference between the propagation of the upper delay chain 410 in the structure "T2-T3" and the delay elements (411, 421) in the lower delay line 420 (T = T2 - T3 ), where T2 and T3 are the propagation delay values of each of the upper delay units 411 and 421 on the upper delay line 410 and the lower delay line 420, respectively, and upper T2>T3 is applied.

Small changes in process, voltage and temperature changes will have a great impact on the delay of the aforementioned buffering delay units 211 , 310 , 411 , and 421 . Therefore, this delay is used as a reference signal to control the PVT variation of the core of the TDC 100 (buffer delay module 200 , edge detector 300 and vernier delay module 400 ). As shown in FIG. 6 , the PVT compensator 600 is composed of a buffer delay chain 610 formed by connecting a plurality of delay units 611 in series, and a negative edge flip-flop 620 corresponding to each stage of the delay unit 611 . The input to the PVT compensator 600 is the clock signal clk, so the clock signal clk is the input to the buffer delay chain 610 and is also used for the negative edge flip-flop 620. The clock signal clk is output (clkd1 ~ clkdm) through the delay unit 611 of each stage as the data input to the corresponding negative edge flip-flop 620 of the stage, and the clock signal clk is directly sent to each negative edge trigger clock (clk) input to the controller 620.

The periodic clock signal clk is delayed by the buffer delay chain 610, wherein the propagation delay value of each delay unit 611 is T4, and each delay unit 611 delays the clock signal clk by T4. In practice, a total of m delay units 611 are used to generate clkd1, clkd2, .. clkdm signals. Notably, it is assumed that m=36 in the embodiment. The corresponding negative edge flip-flops 620 are triggered by the falling edge of the initial clock signal clk, and the m delayed pulse sequences are latched by the corresponding negative edge flip-flops 620. The negative edge flip-flops 620 latch the m delayed pulses. For pulse trains P[0]~P[m], these negative edge flip-flops 620 are triggered by the falling edge of the original "clk".

Through comprehensive simulation sampling, as shown in FIG. 7 , it is found that the 19th, 22nd, 26th, 29th and 34th stages of the buffer delay chain 610 in the PVT compensator 600 are obtained in the buffer delay module 200 and the vernier delay module 400 The optimal threshold (Threshold) for resisting PVT changes (see Table 1 below), the output of the corresponding negative edge flip-flop 620 is from the inverted Q, and then the PVT code Cin[3:0] is provided to the buffer delay module 200, edge The detector 300 and the vernier delay module 400, and the buffer delay module 200 generate a set of Q[31:0] generations code, the vernier delay module 400 generates another set of codes V[6:0], and the Q[31:0] codes and the codes V[6:0] are sent to the encoder 500 to obtain the final output code E[7 :0].

The simulation time-to-digital converter 100 with inverse PVT variation design in this case is implemented using TSMC mixed-signal/RF 1P9M low-power 90nm CMOS process. As shown in Figure 7, the output signals of clkd19, clkd22, clkd26, clkd29 and clkd34 were seen in all processes, voltage (V) and temperature changes. It is observed in Figure 7 that at the negative edge of the clock signal clk, it distinguishes between slow, slow-fast, typical, fast-slow and fast signals by using these clkd19, clkd22, clkd26, clkd29 and clkd34 signals. These signals are provided to corresponding negative edge flip-flops 620 to generate outputs P19, P22, P26, P29, P34. But in practice, we only need four control signals to control the delay in the delay unit of the core. Therefore, the five signal codes (P19, P22, P26, P29, P34) are converted into four signal codes Cin[3:0] by the encoder 500, and the codes generated by the analog PVT compensator 600 are shown in the following table.

It is well known that the delay of the delay cell depends on the current discharge in the first stage. Therefore, the delay of the delay unit is maintained through these control signals Cin[3:0]. Its working method is to generate a 1111 code when a slow signal is generated, so the current discharge is high, and when a slow signal is generated, a 1110 code is generated, The delay of current discharge is small compared to the previous stage. But the signal is slow-fast and therefore compensated for this delay by the delay unit. The same goes for other signals, whereby the PVT variation of the delay cells at the core of the time-to-digital converter 100 can be reduced.

In addition, the delay unit 611 in the buffer delay chain 610 is different from the delay units 211 , 411 and 421 in the buffer delay module 200 and the vernier delay module 400 . The delay unit 611 in the PVT compensator 600 is shown in FIG. 8 . Except for the CMOS buffer gate composed of NMOS transistors Mn701, Mn702 and PMOS transistors Mp701, Mp702. A transistor Mn703 is connected in series with the NMOS transistors Mn701 and Mn702, and because the transistor Mn703 is always on, the transistor Mn703 is used as a resistor; a transistor Mn704 is controlled by the CMOS buffer gate, and the source and drain of the transistor Mn704 A short circuit, through transistor Mn704 acts as a capacitor, and then an RC delay is formed by transistors Mn703 and Mn704.

In implementation, referring to FIG. 2 and FIG. 5 again, the delay unit 211 of the buffer delay module 200, the delay unit 310 of the edge detector 300, and the upper delay units 411 and 421 of the vernier delay module 400 are determined by Cin[3 :0] control, Cin[3:0] is coupled directly to the output of the PVT compensator 600, so the delay will be adjusted automatically.

The schematic diagram of the delay units 211 , 310 , 411 and 421 in the buffer delay module 200 , the edge detector 300 and the vernier delay module 400 at the core of the time-to-digital converter 100 is shown in FIG. 9 . A CMOS buffer gate composed of Mn2 and PMOS transistors Mp1 and Mp2, wherein the CMOS buffer gate is connected in series with a transistor Mn7 as a resistor, because the transistor Mn7 is always on; there are four transistors Mn3, Mn4, Mn5 and Mn6 respectively It is connected in parallel with the transistor Mn7, and the four transistors Mn3, Mn4, Mn5 and Mn6 are controlled by Cin[3:0] (Cin[0], Cin[1], Cin[2], Cin[3]) respectively, The generated PVT code Cin[3:0] is used to adjust the current sink capability of the delay units 211 , 310 , 411 , and 421 . The entire time-to-digital converter 100 core is monitored by the PVT compensator 600, In order to resist the delay variation of the delay units 211 , 310 , 411 and 421 caused by the process, voltage and temperature (PVT).

The TDC 100 of the present case has a resolution of 5.4ps, a delay variation of 2ps, and a dynamic range of 890ps by simulating the TDC 100 condition with an inverse PVT variation design as described above.

The technical feature of the present invention is to use a two-stage system architecture, where the first stage is a buffered delay line to obtain a wide dynamic range, and then delayed start and stop signals are provided to the second stage vernier delay line through an edge detector, For higher resolution, the entire architecture is monitored by PVT detectors to resist process, voltage, temperature (PVT) variations.

However, the above are only preferred embodiments of the present invention, and should not limit the scope of the present invention, that is, any simple equivalent changes and modifications made according to the scope of the patent application of the present invention and the contents of the description of the invention, All still fall within the scope of the patent of the present invention.

100: Time to Digitizer

200: Buffer delay module

210: Buffer Delay Line

211: Delay unit

220: Trigger

300: Edge Detector

310: Delay unit

320: anti-OR gate

330: or gate

400: Cursor delay module

410: up delay line

411: Upper delay unit

420: Lower delay line

421: Lower delay unit

430: Trigger

500: Encoder

600: PVT compensator

610: Buffered Delay Chain

611: Delay unit

620: negative edge trigger

Mn701, Mn702: NMOS transistor

Mp701, Mp702: PMOS transistors

Mn703, Mn704: Transistor

Mn1, Mn2: NMOS transistor

Mp1, Mp2: PMOS transistors

Mn3, Mn4, Mn5, Mn6, Mn7: transistors

FIG. 1 is a schematic block diagram of the time-to-digital converter of the present invention. FIG. 2 is a schematic diagram of the buffer delay module of the present invention. FIG. 3 is a timing diagram of the buffer delay module. FIG. 4 is a schematic diagram of the edge detector of the present invention. FIG. 5 is a schematic diagram of the cursor delay module of the present invention. FIG. 6 is a schematic diagram of the PVT compensator of the present invention. FIG. 7 is a schematic diagram of a comprehensive simulation of the PVT compensator in this case. FIG. 8 is a schematic diagram of a delay unit of a PVT compensator. FIG. 9 is a schematic diagram of the delay unit of the buffer delay module, the edge detector and the vernier delay module.

100: Time to Digitizer

200: Buffer delay module

300: Edge Detector

400: Cursor delay module

500: Encoder

600: PVT compensator

Claims (9)

A time-to-digital converter is a converter that converts the time difference between the transition timings of a start signal and a stop signal into a digital value, and is characterized in that it comprises: a buffer delay module, which performs the start and end of the start signal and the stop signal. The end of the sampling, and the time difference between the edges of the start signal and the stop signal is measured, and the digital code of the sampling timing is generated; the edge detector is used as a bridge to detect the delay start signal in the buffer delay module. The edge The detector detects and outputs the start signal closest to the stop signal as the delay start signal, and the delayed stop signal as the delay stop signal; the vernier delay module receives the output of the edge detector. The delay start signal is used for sampling and measurement at a higher rate, and the digital code of the sampling timing is generated; the encoder is used to convert the digital code of the buffer delay module and the vernier delay module into digital code; and PVT compensator , its input clock signal generates PVT code, which is used to monitor the components used for delay in the aforementioned buffer delay module, the aforementioned edge detector and the aforementioned vernier delay module, and resist the slight variation of process, voltage and temperature variation. The time-to-digital converter of claim 1, wherein the buffer delay module comprises a buffer delay line formed by a multi-stage delay unit connected in series, and a flip-flop corresponding to each stage of the delay unit; the aforementioned A start signal is applied to the buffer delay line, each stage of the delay cell outputs as the data input of the corresponding flip-flop, and the aforementioned stop signal is fed to the clock input of the flip-flop. The time-to-digital converter of claim 1, wherein the edge detector Including a plurality of inverting OR gates corresponding to the aforementioned flip-flops of the buffer delay module, and the outputs of these inverting OR gates are connected to an OR gate; one input of each inverting OR gate is given by the corresponding aforementioned flip-flop. The output inversion signal is input through a delay unit, and the other input is the output signal of the next stage flip-flop; thereby detecting and outputting the start signal closest to the stop signal as the delay start signal, and the delayed start signal The stop signal serves as the aforementioned delayed stop signal. The time-to-digital converter of claim 1, wherein the vernier delay module comprises an upper delay line formed by a multi-stage upper delay unit connected in series, and a multi-stage lower delay line corresponding to the upper delay line A lower delay line connected in series, and a flip-flop corresponding to the aforementioned delay unit of each stage; wherein the given input of the upper delay line is the aforementioned delay start signal, and the output of the aforementioned upper delay unit of each stage is provided to the corresponding aforementioned aforementioned delay unit The data input of the flip-flop; the given input of the lower delay line is the aforementioned delay stop signal, and the output of the aforementioned lower delay unit of each stage is provided as a clock signal to the corresponding aforementioned flip-flop. The time-to-digital converter of claim 4, wherein the propagation delay time value of the upper delay unit is greater than the propagation delay time value of the lower delay unit. The time-to-digital converter of claim 1, wherein the PVT compensator is composed of a buffer delay chain formed by connecting a plurality of delay units in series, and a negative edge flip-flop corresponding to each stage of the delay unit ; The aforementioned clock signal is the input of the buffer delay chain, the output of the delay unit of each stage is used as the data input of the corresponding negative edge flip-flop of this stage, and the aforementioned clock signal is directly sent to each of the negative edges Clock input for flip-flop. The time-to-digital converter of claim 6, wherein the delay elements of those stages of the buffer delay chain in the aforementioned PVT compensator are taken between the buffer delay module and the vernier by full-scale simulation sampling. The delay module obtains the best threshold for the best PVT change, and then uses the best The threshold logic is transcoded to obtain the desired aforementioned PVT code. The time-to-digital converter of claim 6, wherein the delay element of the PVT compensator is an RC delay. The time-to-digital converter of claim 7, wherein the PVT code generated by the PVT compensator is used to adjust the current sinking capability of the delay element in the buffer delay module and the vernier delay module to Resistant to delay variations due to process, voltage, and temperature.

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