JPS5863229A - Testing device for analog-digital converter - Google Patents

Testing device for analog-digital converter

Info

Publication number
JPS5863229A
JPS5863229A JP16300981A JP16300981A JPS5863229A JP S5863229 A JPS5863229 A JP S5863229A JP 16300981 A JP16300981 A JP 16300981A JP 16300981 A JP16300981 A JP 16300981A JP S5863229 A JPS5863229 A JP S5863229A
Authority
JP
Japan
Prior art keywords
converter
output
digital
circuit
analog
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16300981A
Other languages
Japanese (ja)
Inventor
Hideyuki Tsujimura
秀之 辻村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP16300981A priority Critical patent/JPS5863229A/en
Publication of JPS5863229A publication Critical patent/JPS5863229A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10Calibration or testing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Testing Electric Properties And Detecting Electric Faults (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To perform a test for numbers of items in a short time, by obtaining with high accuracy the threshold value to the digital output code of an A/D converter and storing the data of obtained threshold value. CONSTITUTION:An A/D converter C to be tested receives the digital signal of a counter A which counts the clocks and digitizes the analog output signal given from a D/A converter B having a larger number of bits than the converter C. This digital signal is fed to a comparator E directly or via a temporary storage circuit D. The comparator E delivers an output every time the output code of the converter C varies. The output codes of both the counter A and the converter C of that moment are stored in the storage circuits M1 and M2. Thus the circuit M1 stores with high accuracy the threshold value to the changing point of the converter C. A processor CPU reads and processes the codes stored in the circuits M1 and M2. In such a way, the various functions of the converter C can be tested with high accuracy and at a high speed.

Description

【発明の詳細な説明】 本発明はアナログディジタル変換器の試験装置に関する
ものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a testing device for analog-to-digital converters.

従来、アナログ、ディジタル変換器(以下〜Φ変換器)
の測定項目の中の誤差(直線性誤差、ビ、ト抜け、利得
誤差、等)項目に対してこれらを共通の試験器で行うの
は誤差の性質上困難であり、各側だ項目に対して専用の
試験装置で行っていた。
Conventional, analog and digital converters (hereinafter referred to as Φ converters)
Due to the nature of the errors, it is difficult to use a common tester to measure errors (linearity errors, bits and toes, gain errors, etc.) in the measurement items. This was done using a dedicated testing device.

又、測定方法も、アナログ入力としである決められた値
を入力し、そのディジタル出方を規格値と比較する事で
定性的に利足全行い、加速試験等定量的にデータの比較
を行うという事がむずかしかった。又、汎用試験器に於
て、A/D変換器のアナログ入力のレベルを低レベルに
して測定すると、レベルを設定する時間と変換後判定す
るのに時間がかかり、非常に長い時間の測定となった。
In addition, the measurement method is to input a certain value as an analog input and compare the digital output with the standard value to perform all tests qualitatively, and quantitatively compare data such as accelerated tests. That was difficult. In addition, when measuring with a general-purpose tester at a low analog input level of the A/D converter, it takes time to set the level and to make a judgment after conversion, resulting in a very long measurement time. became.

本発明の目的は、このような従来の欠点を解決し次アナ
ログディジタル変換器の試験装置を提供することにある
SUMMARY OF THE INVENTION An object of the present invention is to provide a testing device for analog-to-digital converters that overcomes these conventional drawbacks.

本発明の特徴は、アナログディジタル変換器の試験を行
なう試験装置において、任意のディジタル信号を発生す
るディジタル信号発生部と、このディジタル信号に対応
したアナログ信号を出方するアナログ信号発生部と、被
測定アナログディジタル変換器のディジタル出方信号の
変化点を検出する検出部と、この検出部の検出信号によ
り前記のディジタル信号とディジタル出力信号とを記憶
する記憶部と、この記憶部の内容に依存して被測定アナ
ログディジタル変換器の良否を判定する判定部とを含む
アナログディジタル変換器の試験装置にある。例えば、
計数回路の出方をディジタル・アナログ変換器(以下D
/A変換器と略す。)のディジタル入力及び記憶回路M
lの入力にそれぞれ接続し、前記D/A変換器のアナロ
グ出方を供試アナログ・ディジタル変換器(以下A/D
変換器と略す。)のアナログ信号源とする手段と、前記
A/D変換器の出力を記憶回路M2の入力と、前記A/
D変換器のディジタル出カコー)”k−19的に記憶す
る為の一時記憶回路の入力及び比較回路の一方の入力に
接続し、前記一時記憶回路の出力を前記比較回路の他方
の入力に接続し、前記一時記憶回路と前記比較回路の構
成により、前記砂質換器のディジタル出方コードの変化
を検出する手段に於騒て、前記比較回路の前記2人力の
値が異なった時変化する出力を前記記憶回路Ml及びM
!の書込み入力及び前記一時記憶回路のクロック入力に
接続し、前記記憶回路Ml及びM2の出方を処理回路入
力に接続し、前記一時記憶回路と前記比較回路により、
前記A/D変換器のディジタル出力コードの変化を検出
し、前記計数回路の出力及び前記A/D変換器のディジ
タル出力コードを記憶し、前記記憶回路M1及びM2の
出方を処理回路で処理する事t−特徴とするアナログ・
ディジタル変換器の試験装置である。
A feature of the present invention is that a test device for testing an analog-to-digital converter includes a digital signal generation section that generates an arbitrary digital signal, an analog signal generation section that outputs an analog signal corresponding to the digital signal, and a A detection section that detects a change point in the digital output signal of the measurement analog-to-digital converter, a storage section that stores the digital signal and the digital output signal based on the detection signal of this detection section, and a storage section that depends on the contents of this storage section. The present invention provides an analog-to-digital converter testing device including a determining section for determining the acceptability of the analog-to-digital converter under test. for example,
The output of the counting circuit is converted to a digital-to-analog converter (hereinafter referred to as D).
/A converter. ) digital input and storage circuit M
The analog output of the D/A converter is connected to the input of the D/A converter under test (hereinafter referred to as A/D
Abbreviated as converter. ), the output of the A/D converter is input to the memory circuit M2, and the A/D converter output is input to the memory circuit M2;
The digital output of the D converter is connected to the input of a temporary storage circuit for storage in a digital manner and one input of the comparison circuit, and the output of the temporary storage circuit is connected to the other input of the comparison circuit. However, due to the configuration of the temporary storage circuit and the comparison circuit, the means for detecting a change in the digital output code of the sand exchanger changes when the values of the two manual forces of the comparison circuit are different. The outputs are sent to the memory circuits Ml and M
! is connected to the write input of the memory circuit and the clock input of the temporary memory circuit, the outputs of the memory circuits Ml and M2 are connected to the processing circuit input, and the temporary memory circuit and the comparator circuit:
Detecting a change in the digital output code of the A/D converter, storing the output of the counting circuit and the digital output code of the A/D converter, and processing the outputs of the storage circuits M1 and M2 in a processing circuit. Things to do - Features of analog
This is a test device for digital converters.

本発明によれば、A/D変換器のディジタル出力コード
に対するしきい値を高精度で求め、データを記憶する事
により、前述の従来の欠点を克服する事が出来る。
According to the present invention, the above-mentioned conventional drawbacks can be overcome by determining the threshold value for the digital output code of the A/D converter with high precision and storing the data.

以下、図面を用いて本発明の一実施例について説明する
An embodiment of the present invention will be described below with reference to the drawings.

本発明の一実施例の構成を第1図に示す、第1図より計
数回路Aの出力C6UTK% D/A変換変換器量ィジ
タル入力DA■N及び記憶回路Mtの入力DIIをそれ
ぞれ接続し、D/Af換器Bのアナログ出力DAouT
kA/D変換器Cのアナログ信号源とし、A/D変換変
換器量力ADouTt記憶回路M2の入力DI2とA/
D変換変換器量ィジタル出力コードを一時的に記憶する
為の一時記憶回路りの入力LAI N及び比較回路Eの
一方の入力CMB I Nに接続し、一時記憶回路りの
出力LAoutを比較回路Eの他方の入力CMA I 
N [接続し、一時記憶回路りと比較回路Eの構成によ
り、A/DKA器Cのディジタル出力コードの変化を検
出し、比較回路Eの2人力CMAIN、CMBINの値
が異なった時変化する出力CMOUTt’記憶回路Ml
及びM2の書込み入力MWIN1及びMW□N2及び一
時記憶回路りのクロック入力CLINに接続し、記憶回
路R41及びM2の出力それぞれり。□及びり。2を処
理回路CPUに接続し、一時記憶回路りと比較回路Eに
より、A/D変換変換器量ィジタル出力コードの変化を
検出し、計数回路Aの出方CoUT及びA/D変換器の
ディジタル出方コードヲ紀憶し、記憶回路Ml及びM2
の出方を処理回路CPUで処理する事を特徴としている
The configuration of an embodiment of the present invention is shown in FIG. 1. From FIG. /Af converter B analog output DAoutT
The analog signal source for the A/D converter C is input DI2 and the input DI2 of the A/D converter quantity ADouTt storage circuit M2.
The output LAout of the temporary storage circuit is connected to the input LAIN of a temporary storage circuit for temporarily storing the digital output code of the D-conversion converter and one input CMB IN of the comparison circuit E. Other input CMA I
N [The configuration of the temporary memory circuit and the comparator circuit E detects changes in the digital output code of the A/DKA device C, and outputs the output that changes when the values of the two manual CMAIN and CMBIN of the comparator circuit E are different. CMOUTt'Memory circuit Ml
and the write inputs MWIN1 and MW□N2 of M2 and the clock input CLIN of the temporary storage circuit, and the outputs of the storage circuits R41 and M2, respectively. □Andri. 2 is connected to the processing circuit CPU, and the temporary storage circuit and comparison circuit E detect changes in the A/D converter digital output code, and the output code CoUT of the counting circuit A and the digital output code of the A/D converter are detected. memory circuits Ml and M2
The feature is that the processing circuit CPU processes the output.

次に動作原理を説明する。A/D変換変換器量ット数よ
り大きなビット数をもったD/A変換変換器量ィジタル
人力DAINK:D/A変換器Bのすべてのディジタル
コードが得られる計数回路Aの出力Cout’を接続す
る。そして、D/A変換変換器量ナログ出力DAout
変換器Cのアナログ入力ADINの信号源とする。
Next, the operating principle will be explained. D/A converter quantity digital manual DAINK with bit number larger than A/D converter quantity bit count: Connect output Cout' of counting circuit A from which all digital codes of D/A converter B can be obtained. . Then, the D/A converter analog output DAout
Let it be the signal source of the analog input ADIN of converter C.

又、計数回路Aはクロ、り入力CIN より入力される
クロ、りにより+1づつカウントアツプする。ものとす
る、最初スタート状態から始めるものとする。初期条件
として、計数回路Aの出力Coutは0コードによって
、D/A変換変換器量力DAOUTもOV、又A/D変
換器Cの出力ADOUTも0コードとし、一時記憶回路
りの内容も0コードとし、さらに記憶回路M1及びM2
のアドレスも共に0コードとする。
Further, the counting circuit A counts up by +1 according to the clock input from the clock input CIN. Let us start from the starting state. As an initial condition, the output Cout of the counting circuit A is set to 0 code, the D/A converter quantity output DAOUT is also set to OV, the output ADOUT of the A/D converter C is also set to 0 code, and the contents of the temporary storage circuit are also set to 0 code. Furthermore, memory circuits M1 and M2
Both addresses are also 0 code.

今、計数回路Nのクロック人力CINにクロ。Now, clock CIN of counting circuit N is clocked manually.

りが入力されると計数回路入出力C0UTはカウントア
ツプされていく。即ちD/4変換変換器用力DAOut
であるアナログレベルが上がっていく。
When the value is input, the count circuit input/output C0UT is counted up. That is, the D/4 conversion converter power DAOut
The analog level is rising.

しかしA/D変換変換器用力ADOUTはOから1のコ
ードになる為のしきい値電圧が入力されなければ変化し
ないので、他の回路は何の変化も起さ彦い。次に第2図
の様に、At発のパルスが入力された時、A/D変換変
換器用力ADOUTがOから1のコードに変化したとす
ると、A1発のクロ、りに対する計数回路への出力co
u’rがOから1になるしきい値レベルとなる。
However, since the A/D converter power ADOUT does not change unless the threshold voltage for changing the code from O to 1 is input, no change occurs in the other circuits. Next, as shown in Figure 2, when the pulse from At is input, the A/D conversion converter power ADOUT changes from O to 1 code. output co
This is the threshold level where u'r changes from O to 1.

出力ADOU?が1のコードになり、比較回路Eの入力
CMB!Nに入力され、一時記憶回路りの出力LAOU
tと比較されると、入力値が異なる為、比較回路Eの出
力CMOU’rが変化する。するとこの変化が記憶回路
M′l及びM2の書き込み入力#lNl及rJF MW
IN2に入力され・計数回路人の出力Cou tの内容
を記憶回路Mlに書き込み、又A/D変換器Cの出力A
Doutの内容(1のコード)t−記憶回路M2に書込
む事になる。さらに比較回路Eの出力CMooTは一時
記憶回路りのクロック人力CL、Nに入力され、一時記
憶回路D[はA/D変換変換器用力ADOUTの内容1
のコードが記憶される事になる。すると比較回路Eの入
力CM&INは1のコードが入り、入力CMBINは1
のコードである為CMOUTは又もとにもどる。この時
記憶回路M1及びM2のアドレスt+1する。これでA
/D変換変換器用力AD、 uiが変化した時の処理を
示した。この動作を繰返して行う事により、A/D変換
変換器用力ADQυTコードすべてを記憶回路M2に記
憶し、さらにそれぞれのコードに対するしきい値を記憶
回路Mlに記憶される事になる。
Output ADOU? becomes a code of 1, and the input CMB of comparator circuit E! N, and the output LAOU of the temporary storage circuit
When compared with t, since the input values are different, the output CMOU'r of the comparison circuit E changes. Then, this change causes the write inputs #lNl and rJF MW of the memory circuits M'l and M2.
The contents of the output Cout of the counting circuit input to IN2 are written to the memory circuit Ml, and the output A of the A/D converter C is
The contents of Dout (code of 1) will be written to the t-memory circuit M2. Further, the output CMooT of the comparator circuit E is input to the clock input CL and N of the temporary memory circuit, and the temporary memory circuit D [is the content 1 of the A/D converter output ADOUT.
The code will be memorized. Then, the input CM&IN of the comparison circuit E receives a code of 1, and the input CMBIN becomes 1.
Since this is the code, CMOUT returns to its original state. At this time, the address of memory circuits M1 and M2 is t+1. Now A
/D conversion The processing when the converter power AD, ui changes is shown. By repeating this operation, all the A/D converter power ADQυT codes are stored in the memory circuit M2, and the threshold values for each code are also stored in the memory circuit M1.

又、しきい値レベルは次の様にして求まる。今D/A変
換器Bのフルスケール電圧tvytrLvとすると、D
/人変換器Bの1ビット当りの電圧は、D/A変換器B
のビット。数iNビットとすると(但しNは整数)Vν
υLL/2NVとなる。従って前述の例で示した様にA
/D変換変換器用力ADOU’rがOから1のコードに
なるしきい値は、(クロックA1発の計数回路A となる。従って、Nの値を大きくすれば精度は上がる事
になる。又、記憶回路Ml、M2のアドレスとデータの
関係は前述の限りではない。
Further, the threshold level is determined as follows. Now, if the full-scale voltage of D/A converter B is tvytrLv, then D
The voltage per bit of D/A converter B is
A bit of. Assuming a number iN bits (where N is an integer), Vν
It becomes υLL/2NV. Therefore, as shown in the previous example, A
The threshold value at which the /D conversion converter power ADOU'r changes from O to 1 code is (counting circuit A with clock A1. Therefore, increasing the value of N will increase the accuracy. , the relationships between the addresses and data of the memory circuits M1 and M2 are not limited to those described above.

例えば測定項目中で直線性誤差を求める項目がある。こ
れは、A/D変換器の出力コードがあるコードから次の
コードに変化する時の入力電圧の変化で、本発明の回路
では記憶回路M11Z)任意のアドレス’iADDMと
すると(但しM[Oi含む正の整数)この例ではADD
M −ADDM−、のデータの値より求める事が出来る
For example, among the measurement items, there is an item that requires linearity error. This is the change in input voltage when the output code of the A/D converter changes from one code to the next. positive integer) in this example ADD
It can be determined from the data value of M-ADDM-.

又、と、ト抜けといわれる測定項目がある。こればA/
D変換器のアナログ入力に対して一般にコードは+1づ
つ発生するが、不良ではあるべきコードが存在しない場
合がある。この検出も記憶回路M2の内容を順々に読み
出して行けば発見出来る。
Also, there is a measurement item called "to-missing". Koreba A/
Generally, codes are generated in increments of +1 for the analog input of the D converter, but in some cases, a code that should be present may not exist due to a defect. This detection can also be discovered by sequentially reading out the contents of the memory circuit M2.

本発明の構成の試験itでは、A/D変換器ののすべて
のコードに対するしきい値がわかっている為、処理回路
の処理により従来の様に測定項目別に試験機の必要性が
なくなる。又、加速試験等に於ても、コード及びしきい
値がわかっている為、行う前のデータと行ってからのデ
ータの比較が出来、変動に対しても十分評価できる様に
なる。さらにデータ処理に対しても、A/D変換後必要
に応じて記憶回路M1及びA12の内容を読み出して必
要な処理を行えるし、又高速処理回路を用いる事により
、A/D変換器のコードの変化点から次の変化点の間処
理を行う事も可能であり、この方法は測定時間を短縮出
来る。
In the test IT configured according to the present invention, since the threshold values for all codes of the A/D converter are known, the processing by the processing circuit eliminates the need for test equipment for each measurement item as in the past. Also, in accelerated tests, etc., since the code and threshold value are known, it is possible to compare the data before and after the test, making it possible to adequately evaluate fluctuations. Furthermore, for data processing, the contents of the memory circuits M1 and A12 can be read out as needed after A/D conversion and necessary processing can be performed, and by using a high-speed processing circuit, the A/D converter code It is also possible to perform processing from one change point to the next change point, and this method can shorten the measurement time.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の構成を示すブロック図、第
2図は計数回路のクロックパルスと〜Φ変換器の出力コ
ードとの関係を示す図、である。 なお図において、 A・・・・・・計数回路% CIN・・・・・・クロ、
り入力端子、cott’r・・・・・・計数回路の出力
、B・・・・・・D/A変換器、DA!N・・・・・・
ディジタル入力端子、DAOUT ”””アナログ出力
端子、C・・・・・・供試A/D変換器、ADIN・・
・・・・アナログ入力端子% ADOUT・・・・・・
ディジタル出力端子、 I)・・・・・・一時記憶回路
、LA!N・・・・・・入力端子% L&□ U T・
・・・・・出力端子、CL■N・・・・・・クロ、り入
力端子、E・・・・・・比較回路、CMA!N CMB
IN・・・入力端子%CMOUT・・・・・・出力端子
、Ml、M2・・・・・・記憶回路% DII、 DI
2  ・・・・・入力端子% DOI。 ])02・・・・・出力端子、MW!N1.MW!N2
.、・、、−書込み入力端子、CP U 、、、 、、
、処理回路、CPU■NI CPUxN2・・・・・・
入力端子’ AI、A2・・・・・・クロ、り入力数、
ADOUT・・・・・・A/D変換器の出力コード、で
ある。 (
FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a diagram showing the relationship between the clock pulse of the counting circuit and the output code of the ~Φ converter. In the figure, A... Counting circuit % CIN... Black,
input terminal, cott'r...output of counting circuit, B...D/A converter, DA! N...
Digital input terminal, DAOUT """ Analog output terminal, C... Test A/D converter, ADIN...
...Analog input terminal% ADOUT...
Digital output terminal, I)...Temporary memory circuit, LA! N...Input terminal% L&□ UT・
...output terminal, CL■N...black input terminal, E...comparison circuit, CMA! N CMB
IN...Input terminal %CMOUT...Output terminal, Ml, M2...Memory circuit% DII, DI
2...Input terminal% DOI. ])02...Output terminal, MW! N1. MW! N2
.. , , , - write input terminal, CPU , , , , ,
, processing circuit, CPU■NI CPUxN2...
Input terminal' AI, A2... Black, number of inputs,
ADOUT: Output code of the A/D converter. (

Claims (1)

【特許請求の範囲】[Claims] アナログディジタル変換器の試験を行なう試験装置にお
いて、任意のディジタル信号を発生するディジタル信号
発生部と、該ディジタル信号に対応したアナログ信号を
出力するアナログ信号発生部と、被測定アナログディジ
タル変換器のディジタル出力信号の変化点を検出する検
出部と、該検出部の検出信号により前記ディジタル信号
と前記ディジタル出力信号とを記憶する記憶部と、該記
憶部の内容に依存して前記被測定アナログディジタル変
換器の良否を判定する判定部とを含むことを特徴とする
アナログディジタル変換器の試験器
A test device that tests analog-to-digital converters includes a digital signal generation section that generates an arbitrary digital signal, an analog signal generation section that outputs an analog signal corresponding to the digital signal, and a digital signal generation section that outputs an analog signal corresponding to the digital signal. a detection unit that detects a change point of an output signal; a storage unit that stores the digital signal and the digital output signal according to the detection signal of the detection unit; and a storage unit that stores the digital signal and the digital output signal depending on the contents of the storage unit. A tester for an analog-to-digital converter, characterized in that it includes a determination section for determining the quality of the converter.
JP16300981A 1981-10-13 1981-10-13 Testing device for analog-digital converter Pending JPS5863229A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16300981A JPS5863229A (en) 1981-10-13 1981-10-13 Testing device for analog-digital converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16300981A JPS5863229A (en) 1981-10-13 1981-10-13 Testing device for analog-digital converter

Publications (1)

Publication Number Publication Date
JPS5863229A true JPS5863229A (en) 1983-04-15

Family

ID=15765456

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16300981A Pending JPS5863229A (en) 1981-10-13 1981-10-13 Testing device for analog-digital converter

Country Status (1)

Country Link
JP (1) JPS5863229A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61181222A (en) * 1985-02-06 1986-08-13 Yokogawa Hewlett Packard Ltd Measuring device for analog-digital converter
CN110580845A (en) * 2019-10-21 2019-12-17 西安与或电子科技有限公司 Virtual instrument embedded in comprehensive teaching experiment platform

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61181222A (en) * 1985-02-06 1986-08-13 Yokogawa Hewlett Packard Ltd Measuring device for analog-digital converter
CN110580845A (en) * 2019-10-21 2019-12-17 西安与或电子科技有限公司 Virtual instrument embedded in comprehensive teaching experiment platform

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