JP2610824B2 - Logic circuit measuring device with high impedance function element - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a logic circuit measuring device provided with a high impedance functional element.

<Prior Art> In a characteristic test of a logic circuit having a high impedance element such as a so-called three-state element, in addition to an output “H” state and an “L” state, a high impedance state (hereinafter, referred to as “H” state) Hi-Z ”state).

By the way, in a characteristic test of a general logic circuit in which an output state is in two states of “H” state and “L” state, a third
A measuring device as schematically shown in the figure is used. In the figure, 10 is the logic circuit to be measured, 20 is the tester section, and 30 is the CAE (Com
puter Aided Engineering).

The tester unit 20 includes two comparators 21 and 22 to which an output signal of the logic circuit under test 10 is given, and the comparators 21 and 22 have threshold levels VH and VL corresponding to the output level of the logic circuit under test 10. (“H” state>VH>VL> “L” state). The output signals of comparators 21 and 22 are
Given to.

The CAE 30 is programmed with the configuration of the logic circuit under test 10, and the logic circuit 10 under test is input to predetermined input data.
Outputs a reference data pattern which is the same data pattern as when the device operates normally, and supplies the same to the tester section 20.

The CPU 23 of the tester unit 20 compares the reference data pattern given from the CAE 30 with the measured data pattern obtained by actual measurement via the comparators 21 and 22. If the measured data pattern matches the reference data pattern, the logic circuit under test 10 is determined to be non-defective, while if the two patterns do not match, the logic circuit under test 10 is determined to be defective. I do.

<Problems to be Solved by the Invention> However, when the conventional measuring device as described above is used to measure a logic circuit having a high impedance element, the following problems occur.

The measuring apparatus shown in FIG. 3 determines the quality of the logic circuit under test 10 based on whether the output signals of the comparators 21 and 22 are both in the "H" state or the "L" state. On the other hand, when measuring a logic circuit equipped with a high-impedance function element, even if a pull-up resistor and pull-down resistor are connected to the output terminal and the output level in the “Hi-Z” state is set, this output level Takes an intermediate value between the "H" state and the "L" state. Therefore, one of the comparators 21 and 22 is set to “H”.
State, the other is in the "L" state, and depending on the measuring device, it cannot be determined whether the measured logic circuit is normal or not.

In CAE30 described in FIG. 3, “Hi-Z”
The output data pattern indicating the state is irregular. Therefore, when measuring a logic circuit having a high impedance function element, the output data pattern of the CAE 30 cannot be used as it is.

On the other hand, apart from the measuring device shown in FIG. 3, there has also been proposed a device for measuring a logic circuit having a high impedance function element. However, there is a problem that such a device is extremely expensive due to its complicated configuration.

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above problems, and provides a measurement apparatus having a relatively simple configuration capable of performing a characteristic test of a logic circuit having a high impedance function element. It is intended to be.

<Means for Solving the Problems> In order to achieve the above object, the present invention has the following features.

That is, the present invention relates to a measurement device for a logic circuit including a high-impedance functional element whose output impedance is changed to a high-impedance state by an impedance control data pattern Y. And a tester section.

The arithmetic processing unit has a configuration of the logic circuit to be measured as a program, performs an arithmetic processing on an input data pattern based on the program, and outputs a data pattern X similar to an output of a normal logic circuit to be measured. . The data in the high impedance state included in the data pattern X is output as undefined data.

The data pattern conversion unit converts the data pattern X given from the arithmetic processing unit and the impedance control data pattern Y into A = X · Y + 0 · and A ′ = X · Y +
Convert to 1. Thereby, the data pattern X,
The indefinite data included in X 'is replaced by the impedance control data pattern Y or and output as converted data patterns A and A'.

The tester section is supplied with an output signal of the logic circuit under test, and has threshold levels VH1, VL1, VH2, VL2 (VH1) determined in relation to the output level of the logic circuit under test.
1>VL1>VH2> VL2). And, in a first measurement, the threshold level
It is determined whether or not the measured data pattern C of the comparing means having VH1 and VL1 matches the converted data pattern A. Subsequently, in the second measurement, it is determined whether or not the measurement data pattern C ', which is the output of the comparing means having the threshold levels VH2 and VL1, matches the conversion data pattern A'. The pass / fail of the logic circuit to be measured is determined by such two measurements.

<Embodiment> FIG. 1 is a block diagram schematically showing a configuration of an embodiment of the present invention.

In the figure, reference numeral 40 denotes a measured logic circuit having a three-state element as a high impedance function element. However, in the logic circuit under test 40 shown in the figure, only three-state elements are extracted and shown. Measured logic circuit
In 40, T1 is an input terminal, T2 is an output terminal, and T3 is an impedance control terminal. When the impedance control terminal T3 is in the "L" state, the output impedance of the logic circuit 40 is in the "H" state.

Reference numeral 50 denotes a CAE as an arithmetic processing unit. CAE50 is
The configuration of the logic circuit under test 40 is provided as a program, and the input data pattern is arithmetically processed based on the program to output the same data pattern X as that of a normal logic circuit under test. The data in the high impedance state included in the data pattern X is output as undefined data.

Reference numeral 60 denotes a CPU as a data pattern conversion unit. CPU60
Is obtained by dividing the data pattern X given from the CAE 50 and the impedance control data pattern Y by A = X · Y + 0.
And A ′ = X · Y + 1 ·, and replaces the indefinite data included in the data patterns A and A ′ with the impedance control data pattern Y or output as the converted data patterns A and A ′.

Reference numeral 70 denotes a tester unit, to which an output signal of the measured logic circuit 40 is supplied. A pull-up resistor R1 and a pull-down resistor R2 are connected to an input terminal connected to the output terminal of the measured logic circuit 40. These resistors R1, R2
Is provided to specify the output level of the measured logic circuit 40 when it is in the “Hi-Z” state. The output signal of the measured logic circuit 40 is provided as one input of the comparators 71 and 72. The comparator 71 is set with threshold levels VH1 and VH2 that are alternatively selected by the switch SW1. On the other hand, the comparator 72 is set to the threshold levels VL1 and VL2 that are alternatively selected by the switch SW2. These threshold levels are set as follows in relation to the output levels ("H" state, "L" state, and "Hi-Z" state) of the measured logic circuit 40.

"H"state>VH1>VL1>"Hi-Z"state>VH2>VL2>
"L" state Measurement data pattern C, which is the output of comparators 71 and 72,
C ′ is given to the CPU 73. The CPU 73 compares the measured data patterns C and C 'with the converted data patterns B and B' given from the CPU 60, thereby obtaining the logic circuit to be measured.
Judge the quality of 40.

Next, the operation of the embodiment having the above-described configuration will be described with reference to FIG.

As shown in FIG. 2A, from the logic circuit 40 to be measured,
It is assumed that a signal pattern that changes from "H" state to "L" state to "Hi-Z" state is output. At this time, a data pattern Y for impedance control as shown in FIG. 2B is input to the impedance control terminal T3.

The tester 70 repeats the measurement twice for the signal pattern given from the logic circuit 40 to be measured.

In the first measurement. Switches SW1 and SW2 of tester 70
Is connected to the contact a side. Therefore, the threshold level VH1 is set in the comparator 71, and the threshold level VL1 is set in the comparator 72. Therefore, the comparators 71 and 72 output the measurement pattern C of "100" as shown in FIG. 2 (c).

In the second measurement, the switches SW1 and SW2 are connected to the contact b side, and the threshold level VH2 is set in the comparator 71, and the threshold level VL2 is set in the comparator 72, respectively. Therefore, the comparators 71 and 72 output the measurement data pattern C 'of "101" as shown in FIG. 2 (d).

On the other hand, the CAE 50 is provided with the same input data as the input provided to the logic circuit under measurement 40, so that “10 *”
The data pattern indicated by is output. here,
Shows indefinite data based on the “Hi-Z” state.

The CPU 60 reads the data pattern “10 *” from the CAE 50,
And an impedance control data pattern Y “110”. Then, these data patterns are converted into A = X · Y + 0 · in the first measurement, and are converted into A ′ = X · Y + 1 · in the second measurement.

As a result, in the case of the first measurement, the indefinite data * of the data pattern X "10 *" is replaced by the CPU 60 with the impedance control data pattern Y "0" at that time. Through such replacement processing, “100” is output from the CPU 60 as the converted data pattern A.

On the other hand, in the case of the second measurement, the indeterminate data * included in the output data pattern X “10 *” is replaced by the CPU 60 with the impedance control data pattern “1” at that time. As a result, "10
1 "is output.

The CPU 73 of the tester unit 70 determines the comparators 71 and 7 based on the first measurement.
It is determined whether the measured data pattern C obtained from the step 2 matches the converted data pattern A given from the CPU 60. For example, in the example shown in FIG. 2, the measurement data pattern obtained by the first measurement is “100”, and C
Since the conversion data pattern A given from the PU 60 is “100”, both data patterns match.

If the measurement data pattern C matches the conversion data pattern B as a result of the first measurement, the CPU 73 then
By the second measurement, it is determined whether or not the prescribed data pattern C 'provided from the comparators 71 and 72 matches the converted data pattern A' provided from the CPU 60. In the example shown in FIG. 2, the measured data pattern C 'is "101" and the converted data pattern A' is "101", so that the two data patterns match.

As a result of the first and second measurements, a measurement data pattern C,
If C ′ matches the conversion data patterns A and A ′,
Since the measured logic circuit 40 operates normally, in this case, the CPU 73 determines that the measured logic circuit 40 is non-defective.

On the other hand, for example, if the measurement data pattern C obtained by the first measurement is “110”, this measurement data pattern C does not match the conversion data pattern A “100”. This means that the measured logic circuit 40 is not operating normally. Therefore, in this case, the CPU 73 determines that the measured logic circuit 40 is defective. As described above, if the measured data patterns C and C 'obtained by the first or second measurement do not match the converted data patterns A and A', the measured logic circuit 40 is determined to be defective. You.

<Effect of the Invention> As described above, in the first and second measurements, the measurement apparatus according to the present invention sets two measurement data patterns by appropriately setting a plurality of threshold levels of the comparison means included in the tester section. While obtaining C and C ', the conversion data patterns A and A' are obtained by appropriately converting and replacing the indefinite data in the output data pattern of the arithmetic processing unit. The conformity / mismatch with the patterns A and A 'is determined, and the quality of the logic circuit to be measured is determined.

As described above, the measuring device according to the present invention can perform a characteristic test of a logic circuit including a high impedance function element with a relatively simple configuration. In addition, the apparatus of the present invention is in the "H" state and the "L" state as shown in FIG.
By slightly modifying the configuration of the measuring device that determines only the state, a characteristic test of a logic circuit having a high impedance functional element can be performed, which is very practical.

[Brief description of the drawings]

FIG. 1 is a block diagram schematically showing the configuration of an embodiment of the present invention, FIG. 2 is an operation waveform diagram of the device shown in FIG. 1, and FIG. 3 is a schematic diagram showing the configuration of a conventional measuring device. It is a block diagram. 40 ... Logic circuit to be measured, 50 ... CAE, 60 ... CPU, 70 ...
Tester section.

Claims (1)

(57) [Claims] A configuration of a logic circuit to be measured is programmed, and input data is arithmetically processed based on the program to obtain data in a high impedance state similar to the output of a normal logic circuit to be measured. An arithmetic processing unit that outputs a data pattern X including indefinite data; a data pattern X provided from the arithmetic processing unit; and a data pattern Y for controlling the impedance of the logic circuit to be measured, where A = X · Y + O · A ′ = X · Y + 1 ·
And a threshold level VH1, VL1, VH2, VL2 (VH1>VL1>VH2> which is given an output signal of the logic circuit under test and which is determined in relation to an output level of the logic circuit under test. V
L2) to determine whether the measured data pattern C output from the comparing means having the threshold levels VH1 and VL1 matches the conversion data pattern A in the first measurement. Discriminating, and further, in the second measurement, discriminating whether or not the measured data pattern C 'output from the comparing means having the threshold levels VH2 and VL2 matches the converted data pattern A'. And a tester for judging the quality of the logic circuit to be measured.