JP2658377B2 - Waveform display device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform display device that reproduces and displays a waveform based on discretely sampled waveform data, and more particularly, to aliasing in an automatic setting mode. (Aliasing) detection.

<Conventional technology> For example, when measuring and displaying a repetitive signal with a digital oscilloscope, the vertical axis sensitivity (V /
div), the horizontal time axis sensitivity (T / div), the trigger level, and the like are not properly set, and the screen may become unobservable as shown in FIG.

Therefore, as shown in FIG. 8, automatic setting is performed so that the input waveform is displayed for several cycles near the center of the waveform display area of the display screen.

Here, the vertical axis sensitivity can be set to an optimum value by sequentially switching the voltage sensitivity and the offset.

On the other hand, the horizontal time axis sensitivity can be set to an optimum value by sequentially switching the time sensitivity. However, if aliasing is not detected, there is a possibility that an input waveform is displayed with an incorrect time axis sensitivity as shown in FIG. In FIG. 9, a solid line A indicates an input waveform, a circle indicates a sample point, and a broken line B indicates a display waveform in which aliasing occurs. Such aliasing reduces the input waveform to the frequency f _i
And then, when the frequency of the sample clock was set to f _s, 2 ·
occur in the case of f _i> f _s.

Conventionally, whether or not such aliasing has occurred has been detected based on the relationship between the trigger level, the data at the trigger point, and the data immediately before the trigger point, as described below.

For example, as shown in FIG. 10, the frequency is 5 Hz and the amplitude is ± 2
Sample rate 100 for waveform data of V sine wave input signal
It is assumed that the data is captured at 0 sps (1000 samplings per second) and displayed as waveform data of 1000 points for five periods as shown in FIG. Note that the trigger level is 0 V and the rising trigger point is the 500th point. FIG. 12 is an enlarged view of a rectangular portion showing the vicinity of the trigger point in FIG. In FIG. 12, assuming that the next data that crosses the trigger level 0V is the trigger point, the data P before that falls below the trigger level.

In contrast, the waveform data of a sine wave input signal with a frequency of 995 Hz and an amplitude of ± 2 V as shown in Fig. 13 is captured at a sample rate of 1000 sps (1000 samplings per second), and the waveform data of 1000 points is 5 periods. When displaying minutes,
As shown in FIG. 14, the display waveform is similar to that of FIG. In this case, the presence or absence of the occurrence of aliasing can be detected based on whether or not the trigger point and the immediately preceding data cross the trigger level. The probability that the trigger point and the immediately preceding data cross the trigger level is 5/1000 = 1/200 because the rising edge of the waveform crosses the trigger level five times. Then, the probability of measuring n times and crossing all n times is (1 /
200) ⁿ , the probability of failing the aliasing detection is reduced.

Incidentally, the trigger point is determined by the trigger level.
The level of the data P immediately before the trigger point is determined from the output data of the A / D converter that samples the input waveform.

For this reason, as shown in FIG.
If the A / D converter is off by 0V, it may be determined that aliasing has occurred but has not occurred, or conversely, that aliasing has occurred but has not occurred. is there.

That is, in detecting the aliasing as in the related art, the set trigger level must match the output data level of the A / D converter.

<Problems to be Solved by the Invention> However, in order to match the trigger level set in this way with the output data level of the A / D converter, a high-precision circuit must be configured, and component costs are reduced. Get higher.

 Also, considerable man-hours are required for circuit adjustment.

In addition, there is a possibility that aliasing detection may be erroneously performed due to aging.

The present invention focuses on such a point, and its purpose is to identify with high probability whether or not aliasing has occurred even when there is a difference between the set trigger level and the output data of the A / D converter. It is to provide a waveform display device.

<Means for Solving the Problems> A waveform display device according to the present invention is a waveform display device that reproduces and displays a waveform based on waveform data discretely sampled by an A / D converter. The voltage and the voltage of the waveform data immediately before the trigger point are larger than the maximum allowable voltage difference between the output data level of the A / D converter and the trigger level around the output data level of the A / D converter. Aliasing detection means is provided for detecting whether or not aliasing has occurred based on whether or not the value falls within an aliasing detection level range set to a large value.

<Operation> In the aliasing detection according to the present invention, the voltage of the waveform data at the trigger point and the voltage of the waveform data immediately before the trigger point are determined based on the output data level of the A / D converter. This is performed based on whether or not the difference falls within a set level range that is larger than the difference between the output data level and the trigger level.

As a result, even if the output data level of the A / D converter is different from the trigger level, the probability that the aliasing detection fails will be reduced.

<Example> Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is an explanatory diagram showing the configuration of an embodiment of the present invention. In the figure, an input signal is applied to a trigger circuit 1 and an A / D converter 2. A trigger level, a trigger delay time, and the like are set in the trigger circuit 1 from an arithmetic control unit (CPU) 3. Output data of the A / D converter 2 is stored in the data memory 4. Note that the range of the A / D converter 2 is set by the arithmetic control unit 3. The waveform data stored in the data memory 4 is read out and displayed on a display unit 5 including a display such as a CRT. The keyboard 6 sets measurement conditions, memory conditions, display conditions, and the like in the arithmetic control unit 3. The RAM 7 is used as a system memory. A control program is stored in the ROM 8, and a part thereof includes aliasing detection range data larger than a maximum allowable value of a difference between a trigger level set by the trigger circuit 1 and an output data level of the A / D converter 2. Is stored.

In such a configuration, the trigger circuit 1 outputs a control signal to the A / D converter 2 when the trigger condition is satisfied and one frame of waveform data to be displayed is stored in the data memory 4, and the data memory The writing of the waveform data to No. 4 is stopped. Then, the waveform data for one frame stored in the data memory 4 is displayed on the display unit 5.

On the other hand, the arithmetic control unit 3 captures the waveform data stored in the data memory 4 and detects whether or not aliasing has occurred based on the trigger data set by the trigger circuit 1 and the aliasing detection range data stored in the ROM 8. .

FIG. 2 is a flowchart showing the flow of the entire operation of the apparatus shown in FIG. That is, when the automatic setting key provided on the keyboard 6 is pressed, the voltage sensitivity is set to the maximum range in step (1). After measuring one frame at an arbitrary sample rate (step (2)), it is determined whether the set range and the offset are optimal (step (3)). If they are not optimal, the range, offset and trigger level are changed so as to be in an optimal state (step (4)). When the set range and offset are optimally set, the sample rate is set to the minimum speed (step (5)), and one frame is measured (step (6)). Subsequently, it is determined whether the waveform displayed in one frame is equal to or less than five periods (step (7)). If it is not less than 5 cycles, set the sample rate to 1 until 5 cycles
Speed up step by step (step (8)). When the display waveform becomes five cycles or less, the aliasing is determined (step (9)). Then, it is determined whether or not aliasing has occurred (step (10)). If aliasing has occurred, the sample rate is increased by one step until aliasing does not occur (step (8)), and the automatic setting operation ends when aliasing does not occur.

FIG. 3 shows a step (9) in the flowchart of FIG.
5 is a flowchart showing a flow of an aliasing determination operation in the embodiment. From the measured waveform data of one frame stored in the data memory 4 in step (1), reads out the data D _t of the trigger point (step (2)) of data D _P of the previous trigger point Read (step (3)). Then, based on the trigger level voltage T set by the trigger circuit 1 [V] and read from ROM8 aliasing detection range voltage ± A [V], the data D _t of the trigger points, (T-A) ≦ D t It is determined whether a condition represented by ≤ (T + A) is satisfied (step (4)). If this condition is not satisfied, it is determined that aliasing has occurred (step (5)). On the other hand, if the condition of step (4) is satisfied, it is determined whether or not the condition represented by (T−A) ≦ D _p ≦ (T + A) is satisfied for the data DP _immediately before the trigger point. Is determined (step (6)). If this condition is not satisfied, it is determined that aliasing has occurred (step (5)). On the other hand, when the condition of step (6) is also satisfied, such a series of operations is repeated a plurality of times n (step (7)). If the condition of step (6) is satisfied even after the execution of n times, it is determined that aliasing has not occurred.

FIG. 4 is an operation explanatory diagram in a case where aliasing does not occur in the operation of the flowchart of FIG. Trigger level voltage T set by trigger circuit 1
[V] is internally converted to the output data level voltage T [V] of the A / D converter 2 and handled. That is, in FIG. 4, the solid line indicates the trigger level T set by the trigger circuit 1.
[V], and a broken line indicates a trigger level T [V] at the conversion output of the A / D converter 23. And the upper limit T
The value + A and the lower limit value TA are expressed in terms of the output data level of the A / D converter 23. Here, the aliasing detection range voltage ± A is set to be larger than the maximum allowable voltage difference between the trigger level voltage and the output data level voltage of the A / D converter 23 as described above. Therefore, if the aliasing does not occur, it will enter between D _t and D _P both sure of (T-A) ~ (T + A).

FIG. 5 is an operation explanatory diagram when aliasing has occurred in the operation of the flowchart of FIG.
In the figure, A indicates an input waveform, and B indicates a display waveform. Here, when a uniform probability density distribution of the input waveform A, the probability P that falls between D _t and D _P is (T-A) ~ (T + A) is become. According to the probability density distribution of the input waveform, the probability _P that _Dt and Dp fall between (TA) to (T + A) is other than the above equation, but P <1. If, as P = 1/5, when repeated 10 times, with 10 times D _t and D _P is (T-A) ~ (T + A)
Becomes P (1/5) ^m , and the probability that the aliasing detection fails will be small.

In the case of a square wave, as shown in FIG. 6, the difference between the voltage at the trigger point and the immediately preceding voltage is usually large. In this case, the conventional aliasing detection does not pose a problem in practical use.In order to cope with various other input waveforms other than the square wave, the conventional aliasing detection and the configuration of the present invention may be used in combination. The probability that aliasing detection fails can be improved.

Further, in the above-described embodiment, the waveform is displayed for five periods, but may be appropriately increased or decreased.

The detection of aliasing may be performed by software processing, or may be performed by an electronic circuit such as a gate array.

Alternatively, the trigger point may be set to the waveform data before crossing the trigger level, and the aliasing detection may be performed using the waveform data immediately after the trigger point.

Further, the number of times n for performing the aliasing detection may be set arbitrarily.

<Effects of the Invention> As described above, according to the present invention, even if there is a difference between the set trigger level and the output data of the A / D converter, the presence or absence of aliasing can be identified with high probability,
The effects of reducing the cost of parts, reducing the number of adjustment steps during manufacturing, and preventing aliasing detection errors due to aging can be obtained.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing the configuration of an embodiment of the present invention, FIGS. 2 and 3 are flowcharts showing the flow of the operation of FIG. 1, and FIG. 4 is an explanatory diagram of the operation when no aliasing occurs. , FIG. 5 is an explanatory diagram of the operation when aliasing occurs, FIG. 6 is an explanatory diagram of the operation of square wave input, FIG.
Fig. 8 is a display example before the automatic setting operation, Fig. 8 is a display example after the automatic setting, Fig. 9 is an explanatory diagram of the aliasing, Figs.
FIG. 12 is an explanatory diagram of the operation when the input frequency is 5 Hz, and FIG.
Fig. 14, Fig. 14 is an explanatory diagram of the operation when the input frequency is 995Hz,
FIG. 15 is an operation explanatory diagram when there is a level difference between the trigger level and the output data of the A / D converter. 1 Trigger circuit 2, A / D converter 3, Operation control unit (CPU) 4, Data memory 5, Display unit 6,
... keyboard, 7 ... RAM, 8 ... ROM.

Claims (1)

(57) [Claims] A waveform display device for reproducing and displaying a waveform based on waveform data discretely sampled by an A / D converter, comprising: a voltage of a waveform data at a trigger point and a waveform data of a waveform data immediately before the trigger point. The voltage falls within an aliasing detection level range set to a value larger than the maximum allowable voltage difference between the output data level of the A / D converter and the trigger level around the output data level of the A / D converter. A waveform display device comprising an aliasing detecting means for detecting whether or not aliasing has occurred based on whether or not the waveform has occurred.