JPH02276971A - Waveform display device - Google Patents

Abstract

PURPOSE:To detect the generation of aliasing with high probability by utilizing whether a trigger point and the voltage of waveform data which is right before it are in a range larger than the difference between the output data level of an A/D converter and a trigger level. CONSTITUTION:This display device consists of a CPU 3, a trigger circuit 1 whose trigger level and trigger delay time are set by the CPU 3, an A/D converter 2 and a data memory 4 stored with its output data, a display device 5 to which waveform data is read out, a RAM 7 for a system memory and a ROM 8 stored with a control program including the aliasing detection range data larger than the maximum permissible value of the difference between the trigger level and the output data level of the converter 2. Then the CPU 3 detects whether or not the aliasing is generated according to the waveform data in the memory 4, the trigger data of the circuit 1 and the detection range data of a ROM 8. Consequently, even when there is a deviation between the set trigger level and the output data of the converter 2, the generation of aliasing can be discriminated with high probability.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a waveform display device that reproduces and displays waveforms based on discretely sampled waveform data. (at 1asina).

<Prior art> For example, when measuring and displaying repetitive signals with a digital oscilloscope, the vertical axis sensitivity (ν/
div), horizontal time axis sensitivity (T/div), trigger level, etc., may result in an unobservable screen as shown in Figure 7.

Therefore, as shown in FIG. 8, the input waveform is automatically set to be displayed for several cycles near the center of the waveform display area on the display screen.

Here, the vertical axis sensitivity can be set to a maximum of 3 [82 values] by sequentially switching the voltage sensitivity and offset.

On the other hand, the horizontal time axis sensitivity can be set to an optimal value by sequentially switching the time sensitivity, but if aliasing is not detected, there is a risk that the input waveform will be displayed with the wrong time axis sensitivity as shown in FIG. In Fig. 9, the solid line A indicates the input waveform, the ○ marks indicate the sample points, and the broken line A indicates the sample point.
1B shows a displayed waveform with aliasing. Such aliasing occurs when 2·f i > f s, where the input waveform has a frequency ft and the sample clock frequency fs.

Conventionally, the presence or absence of such aliasing has been detected based on the relationship between the trigger level, data at the trigger point, and data immediately before the trigger point, as described below.

For example, the waveform data of a sine wave input signal with a frequency of 5 Hz and an amplitude of ±2 V as shown in Figure 10 is captured at a sample rate of 1000 sps (1000 samplings per second), and 1000 points as shown in Figure 11 are acquired. It is assumed that five cycles of waveform data are displayed.

The trigger level is Ov, and the rising trigger point is 5.
00th point Hinaru. FIG. 12 is an enlarged view of a rectangular portion showing the vicinity of the trigger point in FIG. 11. In FIG. 12, if the next data that crosses the trigger level OV is the l trigger point, the previous data P will be below the trigger force level.

On the other hand, the frequency shown in FIG. 13 is 995]I
Even when the waveform data of a sine wave input signal with Z'''C'' amplitude of ±2V is captured at a sample rate of 1000 sps (1000 samplings per second) and 1000 points of waveform data are displayed for 5 cycles, the same result as shown in Fig. 14 is obtained. 1st as shown in
The displayed waveform will be similar to that shown in Figure 1. In this case, it is possible to detect whether aliasing has occurred based on whether the trigger point and the data immediately before it cross the trigger level. The probability that the trigger point and the data immediately before it cross the trigger level is 1/200 in 5/1000 because the rising edge of the waveform crosses the trigger level five times. Then, the probability that one measurement will cross all n times is (1/200
) n, and the probability of failure in aliasing detection becomes smaller.

By the way, the trigger point is determined by the trigger level. Then, the level of the trigger point and the previous data P is determined from the output data of the A/D converter that samples the input waveform.

For this purpose, as shown in FIG. 15, the trigger level Ov
If the Ov of the A/D converter and the Ov of the A/D converter are different, it may be determined that aliasing is occurring even though it is not occurring, or conversely, it may be determined that aliasing is not occurring even though it is occurring. There is.

That is, in conventional aliasing detection, the set trigger level must match the output data level of the A/D converter.

<Problem to be solved by the invention> However, in order to match the trigger level set in this way with the output data level of the A/D converter, a highly accurate circuit must be configured, which increases component cost. It gets expensive.

Further, a considerable amount of man-hours are required for adjusting the circuit.

Additionally, there is a risk that aliasing may be detected incorrectly due to aging.

The present invention focuses on these points, and its purpose is to identify with a high probability whether or not aliasing has occurred even if there is a discrepancy between the set trigger level and the output data of the A/D converter. An object of the present invention is to provide a waveform display device.

Means for Solving the Problems> The waveform display device of the present invention is a waveform display device that reproduces and displays a waveform based on waveform data discretely sampled by an A/D converter. The voltage and the voltage of the waveform data immediately before the trigger point reach a value larger than the difference between the output data level of the A/D converter and the trigger level with the output data level of the A/D converter as the center. The present invention is characterized in that an aliasing detection means is provided for detecting the occurrence of aliasing based on whether or not the level falls within a set level range.

Aliasing detection in the present invention is performed when the voltage of the waveform data at the trigger point and the voltage of the waveform data immediately before the trigger point are centered on the output data level of the A/D converter.
This is done based on whether or not the difference between the output data level of the converter and the trigger level is set to be greater than the difference and falls within the zero range.

This reduces the probability that aliasing detection will fail even if the output data level of the A/D converter and the trigger level deviate.

<Example> Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a configuration explanatory diagram showing one embodiment of the present invention.
In the figure, an input signal is applied to a trigger circuit 1 and an A/D converter 2. Trigger circuit] includes an arithmetic control section (
The trigger level, trigger delay time, etc. are set from the CPU 3. The output data of the A/D converter 2 is stored in the data memory 4. Note that the range of the A/D converter 2 is set by the calculation control section 3. The waveform data stored in the data memory 4 is read out and displayed on a display section 5 including a display such as a CRT. The keyboard 6 is the calculation control unit 3
Set measurement conditions, memory conditions 9 display conditions, etc. R
AM7 is used as system memory. A control program is stored in the ROM 8, and part of it includes aliasing detection range data that is larger than the maximum allowable difference between the trigger level set by the trigger circuit 1 and the output data level of the A/D converter 2. is stored.

In such a configuration, the trigger circuit 1 outputs a control signal to the A/D converter 2 when the trigger condition is satisfied and one frame worth of waveform data to be displayed is stored in the data memory 4, Writing of waveform data to the data memory 4 is stopped. Then, the waveform data for one frame stored in the data memory 4 is displayed on the display section 5.

On the other hand, the arithmetic control unit 3 stores the waveform data stored in the data memory 4 and determines whether or not aliasing has occurred based on the trigger data set by the trigger circuit 1 and the aliasing detection range data stored in the ROM 8. To detect.

FIG. 2 is a flowchart showing the overall operation flow of the apparatus shown in FIG. That is, by pressing the automatic setting key provided on the keyboard 6, step (1
), set the voltage sensitivity to the maximum range. and,
After measuring one frame at any sample rate (
Step (2)), it is determined whether the set range and offset are optimal (step (3)). If these are not suitable, change the range, offset, and force level so that they are optimal (step (4))
, Once the setting range and offset are optimally set, set the sample rate to the lowest speed (step (5)).
Measure one frame (step (6)), then
Determine whether the waveform displayed in one frame has 5 cycles or less (step (7)), and if it does not have 5 cycles or less,
The sample rate is increased one step at a time until the period is reached (step (8)). When the displayed waveform becomes 5 periods or less, aliasing is determined (step (9)), and it is determined whether aliasing has occurred. (Step 00)) If aliasing is occurring, increase the sample rate one step at a time until aliasing no longer occurs (Step 8)) Automatically set when aliasing no longer occurs The operation ends.

FIG. 3 is a flowchart showing the flow of the aliasing determination operation in step (9) of the flowchart of FIG. From one frame of waveform data measured in step (1) and stored in the data memory 4, the data Dt at the trigger point is read out (step (2)), and the data Dp immediately before the trigger point is read out (step (2)). (T -A) ≦Dt≦('T' + A) Determine whether or not the condition expressed by ('T' + A) is satisfied (step (4)),
Here, if this condition does not hold, it is determined that aliasing has occurred (step (5)). On the other hand, if the condition of step (4) holds, it is determined that aliasing occurs one point before the trigger point. For the data DP of It is determined that aliasing has occurred (step (5)). On the other hand, if the condition of step (6) is also satisfied, this series of operations is repeated 0 times (step (7)). , step (6
), it is determined that aliasing has not occurred.

FIG. 4 is an explanatory diagram of the operation shown in the flowchart of FIG. 3 when aliasing does not occur.

Trigger level voltage T [V] set in trigger circuit 1
is internally the output data level voltage T of the A/D converter 2
It is treated as converted to [V]. Here, the aliasing detection range voltage ±A is set to be larger than the maximum allowable voltage difference between the trigger level voltage and the output data level voltage of the A/D converter 23, as described above. Therefore, if aliasing does not occur, both Df and DP will always fall between (TA) and (T+A).

FIG. 5 is an explanatory diagram of the operation when aliasing occurs in the operation of the flowchart of FIG. 3. In FIG. 0, A indicates an input waveform, and B indicates a display waveform. Here, if the probability density distribution of the input waveform A is made uniform, it becomes Df and DP. Due to the probability density distribution of the input waveform, Dr and Dp are (T-A') ~ (T-)-A>
The probability P that falls between is other than the above expression, but P<1.

Assuming that P = 115 and repeating 10 times, the probability P that Dt and DP will fall between (TA) and ('T'+A) for all 10 times becomes (115)'', and aliasing detection will fail. The probability becomes smaller.

In addition, in the case of a square wave, as shown in FIG. 6, a case where the difference between the voltage at the tri-point and the previous voltage is large is a V-pass. In this case, there is no practical problem with conventional aliasing detection, so in order to be able to handle various input waveforms other than square waves, it is sufficient to use the conventional aliasing detection together with the configuration of the present invention. The probability of failure in aliasing detection can be improved.

Further, in the above embodiment, the input waveform is displayed for five cycles, but the display may be increased or decreased as appropriate.

Further, detection of aliasing may be performed by software processing, or may be performed by an electronic circuit such as a gate array.

Alternatively, the aliasing detection may be performed by setting the trigger force point to the waveform data before crossing the trigger level and using the waveform data immediately after the trigger point.

Furthermore, the number n of times aliasing detection is performed may be set arbitrarily.

<Effects of the Invention> As explained above, according to the present invention, even if there is a discrepancy between the set trigger level and the output data of the A/D converter, the presence or absence of aliasing can be identified with high probability.
Benefits include lower parts costs, reduced adjustment man-hours during manufacturing, and prevention of aliasing detection errors due to aging.

[Brief explanation of drawings]

FIG. 1 is a configuration explanatory diagram showing one embodiment of the present invention, FIGS. 2 and 3 are flowcharts showing the flow of the operation in FIG. 1, and FIG. 4 is an explanatory diagram of the operation when aliasing does not occur. , Fig. 5 is an explanatory diagram of the operation when aliasing occurs, Fig. 6 is an explanatory diagram of the operation with square wave input, Fig. 7 is an example display before automatic setting operation, and Fig. 8 is after automatic setting. Display example diagram, Figure 9 is an explanatory diagram of aliasing, Figures 10~
Fig. 12 is an explanatory diagram of the operation when the input frequency is 5H2, Figs. 13 and 14 are explanatory diagrams of the operation when the input frequency is 995 It z, and Fig. 15 is an illustration of the tri-power level and the A/D converter. FIG. 7 is an explanatory diagram of the operation when there is a level difference in output data. 1...Trigger circuit, 2...A/D converter, 3...
Arithmetic control unit (CPU), 4... data memory, 5...
・Display diagram diagram diagram diagram diagram diagram diagram cause diagram B ward diagram 9 Gunpur point. □ Human power 5 counter-sign 5 one-one match 3F type x to figure'ry 0 figure 12 [Figure

Claims (1)

[Claims] A waveform display device that reproduces and displays a waveform based on waveform data discretely sampled by an A/D converter, comprising: a voltage of waveform data at a trigger point and waveform data immediately before the trigger point; whether the voltage falls within a level range set to a value larger than the difference between the output data level of the A/D converter and the trigger level, centered around the output data level of the A/D converter. What is claimed is: 1. A waveform display device comprising aliasing detection means for detecting the presence or absence of aliasing based on the waveform display device.