JPH0646199B2 - Power factor meter - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a power factor meter for measuring a power factor of a three-phase AC circuit, and more specifically, to a phase of a load current with respect to a line voltage. The present invention relates to a digital power factor meter having a polarity detecting means.

[Conventional technology]

In measuring the power factor, conventionally, the voltage and current of the measured circuit are detected, the waveform is shaped into a square wave voltage, and a voltage of a magnitude proportional to the phase down φ at the rising time is formed. To the left and right with the median value being 1, for example
In addition to the meter with a non-linear scale of φ, the power factor co
The sφ is indicated.

Here, FIG. 5 (a) shows a line voltage V, FIG. 5 (b) shows a load current I, and FIGS. 5 (c) and (d) show a line voltage V and a load current I, respectively. Suppose that the square wave voltages V _v and Vi are waveform-shaped at 1. At the rising time of the square wave voltage V _v , for example, when the square wave voltage Vi is at the H level, it is in the lead phase, and conversely L
When it is at the level, it can be judged as a delay phase, and accordingly −
Alternatively, a + phase polarity signal is generated, whereby the pointer of the meter is swung left (advance) and right (lag).

[Problems to be Solved by the Invention]

However, the rising time point of one of the square-wave voltage V _v (or falling time), the capture level of the other square-wave voltage Vi accurately and reliably, square-wave voltage V _v and the square wave waveform-shaped Since a separate latch circuit for temporarily latching the voltage Vi is required, the load on the hardware increases.

It is also conceivable to synchronize a clock pulse of, for example, a CPU (central processing unit) in the instrument with a voltage signal of an electric circuit under test, which is an external signal, to detect a rising point of the voltage, but in practice, It is extremely difficult to synchronize the two.

[Means for Solving the Problems]

The present invention has been made in view of the above-mentioned conventional circumstances, and the configurational features thereof will be described with reference to FIG. 1. The voltage and current of the measured electric circuit 1 are detected and converted into a square wave voltage, respectively. A voltage having a magnitude proportional to the phase difference is formed and measured to obtain the power factor of the measured electric circuit, and a predetermined phase polarity sign is given to the power factor according to the delay or advance of the phase difference. In the power factor meter provided with the phase polarity detecting means, the phase polarity detecting means is the measured electric circuit 1
Edge detection means (rise detector) 5 that operates with a plurality of timing pulses that are asynchronous with one of the square wave voltages representing the voltage component of, and detects the rise (or fall) of the same square wave voltage. The level detection means 9 for detecting the level of the other square wave voltage representing the current component of the measured electric circuit 1 at the edge detection time of the edge detection means 5 a predetermined number of times, and the level detected by the level detection means 9. The polarity detection means 14 that forms a predetermined phase polarity signal corresponding to the magnitude and one of the phase polarity signals output from the polarity detection means 14 are cumulatively held, and the number of holdings is 1 Depending on whether it is greater than or equal to or 0, the polarity setting means 15 for sending the corresponding phase polarity code to the power factor measuring unit 11 is provided.

[Operation] Referring also to FIG. 2 (A), in FIG. 2 (A), the voltage V of the measured circuit 1, the current I _{lag in} a phase delayed with respect to this voltage V, and the current I _{lag in} a phase advanced with respect to this voltage V are shown. I _lead is shown. Further, FIG. 3C shows an example in which the voltage V is shaped into a square wave voltage V _v by a ZEROSS comparator, and the two currents I _lag are shown in FIGS. , I _lead are converted into voltages, and then the waveform is similarly shaped into the square wave voltage Vi by the zero-cross comparators.

In the present invention, as shown in FIG. 2B, a CPU (not shown) generates a plurality of timing pulses asynchronous with the voltage V of the measured electric circuit 1, and the rising edge detector is generated at the same timing pulses. 5 is adapted to carry out the detection motion difference.

Here, assuming that the rising edge of the voltage V _v is detected by the rising edge detector 5 at a time point of t ₁ , t _2, ...
When the level detector 9 measures the level of the voltage Vi representing the current component at that time, the polarity detector 14 can detect the delayed phase polarity depending on whether it is the L level or the H level. However, since the detection timing pulse of the rising detector 5 and the voltage V of the non-measurement circuit 1 are asynchronous, in the present invention, the number of times the rising of the voltage V _v is detected is set to a plurality of times for accuracy.

That is, the rising detection timing pulse and the voltage V _v
As shown in FIG. 4, both voltages V _v and Vi are at the L level at the time of the nth timing pulse generation, but at the time of the next n + 1th timing pulse generation, as illustrated in FIG. both voltage _V v, when Vi of both H-level, the voltage Vi relative to the voltage _{V v} in FIG (a) is considered into two states: FIG (b) (c), the voltage _{V v} , Vi cannot be determined until whichever rises first, and therefore, in order to avoid this, the number of times the rise of the voltage V _v is detected is set to a plurality of times. In addition,
It may be detected the level of the voltage Vi at the falling time of the voltage V _v.

The detection result of the polarity detector 14 is sent to the polarity setter 15 and is temporarily stored in the register, and after the predetermined number of measurements,
The final setting of lag or lead phase polarity is made.

In the embodiment, for example, the level of the voltage Vi at the time of rising of the voltage V _v is detected, and if it is at the L level, it is held as data indicating the phase polarity of the delay, but if it is at the H level, it is ignored. ing.

This measurement is repeated a predetermined number of times for the reasons described above,
If the L level is detected once or more, the phase polarity is set to "delay" in the final determination. On the other hand, when the L level is not detected and all are at the H level, “advance” is set.

In the case of detecting the level of the voltage Vi at the falling time of the voltage V _v is reversed to the above, the detection data of the L level is ignored, the phase polarity if more than one H level is detected Is set as "delayed".

The above-mentioned phase polarity detection operation will be supplementarily described with reference to FIG. In addition, FIG. 2A collectively shows (B), (C), and (D). here,
_Let t ₀₀ , t ₀ , ... T _{n be} the actual rising points of the voltage V _v .

In the same figure (g), the rising time t ₀₀ of the voltage V _v is enlarged and shown, where t is the detection timing and A and B represent the detection time, the voltage V _{v at the} point A.
The rising edge of is not detected. At the point B, the rising of the voltage V _v is detected. In this case, both voltages V _v and Vi mean “advance” at the H level, but this detection data is ignored as described above.

The voltage Vi is not detected even at t ₀ in FIG.
The H level data detected at time B is similarly ignored. In the figure, the detection time points A and B are shifted to the left, for example, but this is because the detection timing is asynchronous with the repetition cycle of the voltage V _v as described above, and therefore, relative to the time pitch related to the frequency. This is due to changes in the target position.

The rise t of the voltage V _v in FIGS.
_{For 1} and t ₂ , L of voltage Vi at time B
The level is detected and this data is retained and used for the final determination of phase polarity.

〔Example〕

Referring again to FIG. 1, for example, a voltage detector 2 for detecting the voltage component V of the non-measurement circuit 1 and an attenuator 3 for adjusting the detection output to an appropriate level are provided in the voltage input section of the power factor meter.
And a waveform shaper 4 for shaping the adjusted voltage into a square wave voltage V _v, and the shaped square wave voltage V _v is applied to the rising detector 5.

In the current input section, a current detector 6 for detecting the current component I of the measured circuit 1, a current / voltage converter 7 for converting the detected output into a voltage of an appropriate level, and the converted current component. And a waveform shaper 8 for shaping the voltage representing the above into a square wave voltage Vi as described above, and the shaped square wave voltage Vi is applied to the level detector 9 and the rising detector 5. .

At the time of power factor measurement, the square wave voltage V _v representing the voltage component applied from the waveform shaper 4 in the rise detector 5
Then, each rise of the square wave voltage Vi representing the current component applied from the waveform shaper 8 is detected, and the detection output is input to the phase difference signal generator 10.

In the same phase difference signal generator 10, the phase difference signal Vφ having a magnitude proportional to the time difference is calculated from the two signals.
Is formed and sent to the power factor measuring unit 11. Same power factor measurement unit 1
1 converts this phase difference signal Vφ into a power factor signal cosφ, and when the final determination of the phase polarity in the polarity setting device 15 is determined to be, for example, a lag phase, the data of the power factor signal cosφ is displayed as it is. When the final judgment is made and the phase is set, the above cos is sent.
The φ data is sent with, for example, a minus sign.

Next, the lead / lag phase polarity measurement will be described with reference to FIG. As shown in FIG. 7A, in the measurement, the register of the polarity setting device 15 is set to “0”, and the initial value setting device 16 means “advance” as an initial value, for example. A signal is set, and only when a delay (L level) is detected in the subsequent measurement, the register of the polarity setting unit 15 is caused to cumulatively count the number of detections. Then, a predetermined number of times of measurement is set in the number-of-measurements setting device 17, and the measurement is started.

If the delay is detected once or more at the time when the measurement of the predetermined number of times is completed, the polarity setter 15 sets the phase polarity as “final” as the final result, and the delay is 1
If no advance is detected and only advance (H level) is detected, “advance” is set and the result is transmitted to the power factor measurement unit 11.

FIG. 3 (B) shows an example of the operation in each phase polarity measurement. That is, at the same time as the start of measurement, for example, the timer of the measurement censoring device 18 is set, and the rising detector 5
The rise of the voltage V _v is detected at. Here, the same voltage V
_{If v} is not at L level, the detection is repeated until the level returns to L, and if it does not become L level even after the elapse of a predetermined time, it is timed out according to the instruction from the timer and, for example, the open phase processor 13 causes the register to write to that register. No voltage input,
That is, the phase is considered to be a missing phase and the measurement is terminated.

Once the voltage V _v returns to the level L, the rise to the level H is detected next. In this case, if you do not stand up within the predetermined time, it will time out like the above,
Treated as an open phase.

When the rise of the voltage V _v is detected, the level detector 9 detects the current level. In this case, if the voltage Vi representing the current level is L level, the polarity detector 14
Is output, one of the delay setting registers provided in the polarity setting device 15 is set, and the voltage Vi is set to H level.
If it is a level, there is no change in the register and the process proceeds to the phase polarity judgment of the next step.

Note that each block surrounded by a chain line in FIG. 1 is a functional block actually included in the microcomputer 19, and the clock pulse of the microcomputer 19 is used for the timing pulse of the rising edge detector 5. There is.

〔The invention's effect〕

As described above, according to the present invention, the rise (or fall) of the voltage component is detected by the timing pulse asynchronous with the external input signal, and the level of the current component at that time is detected. It is possible to determine whether the phase is advanced or delayed.

Therefore, since the latch circuit is not required and it is not necessary to synchronize with the input signal from the outside, it is possible to design the microcomputer without imposing an extra program load on the microcomputer. Played.

[Brief description of drawings]

FIG. 1 is a block diagram of a power factor meter according to an embodiment of the present invention, FIGS. 2 (A) and 2 (B) are explanatory views for explaining the operation of the present invention, FIG. 3 (A) and (B) is a flow chart showing an example of controlling the phase polarity measurement of this power factor meter by, for example, a microcomputer, and FIG. 4 is a relationship between a square wave voltage and a timing pulse asynchronous with that for detecting the rise of the same voltage. FIG. 5 is a waveform diagram of voltage and current shown for explaining the conventional phase polarity discriminating method. In the figure, 1 is a circuit to be measured, 2 is a voltage detector, 4 and 8 are waveform shapers, 5 is a rise detector, 6 is a current detector, 9 is a level detector, 10 is a phase difference detector, and 11 is a phase difference detector. Power factor measuring section,
Reference numeral 14 is a polarity detector, 15 is a polarity setting device, and 17 is a measurement number setting device.

Claims (1)

[Claims] 1. The power factor of the circuit under test is measured by detecting the voltage and current of the circuit under test, converting the voltage and current into a square wave voltage, and forming and measuring a voltage having a magnitude proportional to the phase difference. In the power factor meter having the phase polarity detecting means for giving a predetermined phase polarity sign to the power factor according to the delay or advance of the phase difference, the phase polarity detecting means is a voltage component of the measured circuit. Represents the current component of the measured electric circuit, which is operated by a plurality of timing pulses asynchronous with one of the square wave voltages, and which detects the rising (or falling) of the same square wave voltage. Level detecting means for detecting the level of the other square wave voltage at the edge detection time of the edge detecting means a predetermined number of times, and corresponding to the level detected by the level detecting means. A polarity detection means for forming a constant phase polarity signals, and holding one of the signal of the phase polarity signal output from the polar detecting means cumulatively, the holding number 1 or more or 0
And a polarity setting means for sending the corresponding phase polarity code to the power factor measuring section.