JPS58223072A - Low frequency counter - Google Patents

Abstract

PURPOSE:To enable a highly accurate measurement of frequency regardless of the continuation time by repeatedly reading an input signal of a relatively low frequency with a short continuation time in terms of the sampling period. CONSTITUTION:When an input signal is inputted into a counting control circuit 1, an input gate circuit 2 is opened for a certain time and allows the input signal to be sent to a digital memory 5 and a counter 6 through an A/D converter 3. The counter 6 adds by 1 at each inversion of the digitalized signal from positive to negative and produces an output by multiplying the measured value M times. The memory 5 repeatedly reads digitalized signals until the counts of a counter 7 become equal to an output value of the counter 6. On the other hand, while the counts of the counter 7 is not 0, a gate circuit 10 opens and allows a reading clock signal to be sent to a cycle counter 11 and closes as soon as the output of a gate control circuit 9 becomes the logic value 1. An arithmetic circuit 12 calculates the frequency of a input signal from counts of the counter 7 and the cycle counter 11.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a frequency measuring device, and particularly to a relatively low frequency measuring device.

(b) Background of the Technology A strain measurement method using a vibrating string has been adopted as one method for measuring deformation strain of architectural structures and the like. The principle of this method is to vibrate a vibrating string, convert it into an electrical signal, extract it, and calculate the length of the vibrating string from its frequency.The change in the length of this vibrating string with respect to the reference length is then deformed. Strain is measured.

(C) Prior art and problems Conventionally, the frequency of the vibrating string is measured using the above strain measurement method.
This was done by artificially detecting the zero beat sound by interfering the output electrical signal of the strain meter with the output electrical signal caused by the vibration of the reference string. When automating such strain measurements, it is desirable to be able to measure the frequency of the electrical signal output from the direct type needle, and the measured values must be sufficiently detailed in order to detect minute deformation strains. However, the frequency of the vibrating string and the duration of its vibration (the time during which the output electric signal can be effectively detected) are each several hundreds of hours.
z and 1 to several seconds, the detail of the measurement values obtained using a conventional frequency counter is at most 1/2 seconds.
The limit was about too much.

(d) Object of the Invention An object of the present invention is to provide a frequency counter suitable for measuring the frequency of a signal having a relatively low frequency and a short duration as described above.

(e) Structure of the Invention The present invention provides a frequency counter that includes an input gate circuit that allows an input signal to pass through for a certain period of time, and an A-D converter that samples the input signal that has passed through the input gate circuit in synchronization with a sampling clock signal. a digital memory for storing the signal output from the converter; and a first circuit for counting the number of times the positive or negative sign is reversed in the output signal of the converter, multiplying this counted value by a predetermined integer, and outputting the result. and a second counter for counting the number of times the positive or negative sign is reversed in the output signal of the digital memory output in synchronization with the read clock signal.
a coincidence detection circuit that outputs a coincidence signal when the output values of the first counter and the second counter match; and a coincidence detection circuit that outputs a coincidence signal when the output values of the first counter and the second counter match; a period counter that counts the number of the read clock signals until a signal is obtained, and calculates the frequency of the input signal from the period of the read clock signal, the count value of the second counter, and the hand value of the period counter. It is characterized by calculating.

(f) Examples of the invention Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of a frequency counter according to the present invention. In the figure, when an input signal is input, a counting control circuit 1 opens an input gate circuit 2 for a certain period of time, and sends the input signal to a ^-D converter 3. The A/D converter 3 samples the input signal in synchronization with the sample clock signal from the clock signal generating circuit 4 and sends the digitalized signal to the digital memory 5 and the first counter 6. This first counter 6 has a function of adding 1 each time the positive/negative sign of the input digitized signal is reversed, and multiplying the counted value i by a predetermined integer (M) and outputting the result. In FIG. 1, the digital memory 5 stores the input digitized signal in synchronization with the sampling clock signal, and also stores the input digitized signal in synchronization with the readout clock signal from the clock signal generation circuit 4. Send to the counter 7 of 6
The second counter 7 is similar to the first counter 6,
It has a function of adding 1 each time the positive/negative sign of the input digitized signal is reversed. This second counter 7 repeatedly reads the digitized signal until its count value becomes equal to the output value of the first counter 6, that is, the count value □ of the first counter 6 multiplied by the M times. put out. - The number calculation circuit 8 outputs a signal of logical value 1 only when the output count values of the first counter 6 and the second counter 7 match. Gate control circuit 9
outputs a logical value of 1 only when the output value of the minus number construction circuit 8 is a logical value of 1 and the count value of the second counter 7 is not 0. The gate circuit IO opens when the output count value of the second counter 7 is not 0 and sends the read clock signal to the period counter 11, and closes when the output value of the gate control circuit 9 becomes a logical value 1.

In the above, when the output values of the first counter 6 and the second counter 7 match, the match detection circuit 8 returns a logic value of 1.
As a result, the gate control circuit 9 outputs a signal with a logic value of 1, so that the gate circuit is closed. At this time, the hand value of the second counter 7 and the count value of the period counter 11 are manually input to the arithmetic circuit 12.

FIG. 2 shows the input signal (
The relationship between a), the digitized signal (b), and the count value of the first Karank-6 (c) is shown, and T is the time during which the input gate circuit 2 is open. Also, n is the first counter 6
is the count and value during the period of time T.

FIG. 3 shows the reading period from the digital memory 5 (T
Output value of the first counter 6 at M) (A)
and the count value of the second counter 7 (b) and the -number output circuit 8
FIG. 3 is a diagram showing the relationship between the output value (c) of the gate control circuit 9, the output value (d) of the gate control circuit 9, and the count value of the period counter 110 (e).

The calculation circuit 12 contains the count value No. of the second counter 7 when the gate circuit 10 is closed, and the period counter 1.
The frequency F of the input signal is calculated from the count value N of 1 and the period τr of the read clock signal using the following equation.

F-(No-1)/2N・τr(H2)...(1) In equation (1), 1 is subtracted from No. As is clear from FIG. This is because the number of sign inversions is one more than the number of half cycles of the input signal during the period in which this number of times is counted.

According to the present invention, it is possible to measure the frequency of input signals having waveforms as shown in FIG. 4 if these signals are manually input for one period or more. In the figure, (a) is an example of a signal waveform with asymmetric polarity, and (b) is an example of a signal waveform that includes harmonics. According to the frequency counter of the present invention, the fundamental frequency of these waveforms can be measured. be done. Other signals on which noise is superimposed can also be measured in the same way.

(g) Effects of the Invention According to the frequency counter of the present invention, an input signal with a short duration and a relatively low frequency is repeatedly read out and measured using the sampling period as a unit. There is an effect that can be improved. Furthermore, since the measurement is performed by sampling a plurality of periods of the input signal, there is an effect that highly accurate measurement values can be obtained with less errors due to fluctuations in the period.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the periodic counter of the present invention,
1. : Figure 2 shows the relationship between the input signal (a), the digitized signal (b), and the count value of the first counter (c), and Figure 3 shows the relationship between the output value of the first counter (a) and the count value of the first counter (c). 2
The count value of the counter (b) and the output of the -number output circuit (+
Figure 4 shows an example of a signal waveform with asymmetric polarity (A) and harmonics. It is a figure which shows the example (b) of a signal waveform. In the figure, ■ is a counting control circuit, 2 is an input gate circuit,
3 is an 8-0 converter, 4 is a clock signal generation circuit,
5 is a digital memory, 6 is a first counter, 7 is a second counter, 8 is a coincidence detection circuit, 9 is a gate control circuit, 10 is a gate circuit, 11 is a period counter, and 12 is an arithmetic circuit. Irie 57 Figure 3 Man 4 Flash

Claims (1)

[Claims] An input gate circuit that passes an input signal for a certain period of time, a ^-D converter that samples the input signal that has passed through the input gate circuit in synchronization with a sampling clock signal, and a signal output from the ^-D converter that is stored. a digital memory, a first counter that counts the number of times the positive/negative sign is reversed in the output signal of the A-D converter, multiplies the counted value by a predetermined integer, and outputs the result in synchronization with a read clock signal; a second counter that counts the number of times the positive/negative sign is reversed in the output signal of the digital memory; and a coincidence detection that outputs a coincidence signal when the output values of the first counter and the second counter match. a period counter for counting the number of the read clock signals from when the second counter starts counting stitches until a coincidence signal is obtained from the minus number calculation circuit; , a low frequency counter that calculates the frequency of the input signal from the count value of the second counter and the count value of the period counter.