JP3055225B2 - Phase difference measuring device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase difference measuring device.

[0002]

2. Description of the Related Art The configuration of a conventional phase difference measuring device is shown in FIG. 3, and its measuring principle will be described with reference to FIGS. The two signals under test A1 and A2 are input to waveform shapers 12 and 13, respectively. The waveform shapers 12 and 13 output H (the level is high, the same applies hereinafter) when the input signal is positive, and output L (the level is low, the same applies hereinafter) when the input signal is negative. , A2 are converted into rectangular waves like V1 and V2, respectively. The exclusive OR circuit 14 and the AND circuit 15 generate a phase difference pulse V3 corresponding to the phase difference between A1 and A2 from V1 and V2. The reference clock pulse CK and the phase difference pulse V3 from the reference clock pulse generator 19 are input to the AND circuit 16, and the output is input to the counter 17 to convert the phase difference V3 into a digital value. Since the counting of the phase difference by the counter 17 ends at the fall of V1, the signal processing unit 18 captures the count value of the counter 17 after the fall of V1, calculates the phase difference by multiplying by a certain proportional constant, and calculates the phase measurement value. And Thereafter, the counter 17 is reset before the start of the next count. The phase advance / delay is determined by the signal processing unit 18 based on the output signal of the advance / delay discriminator 20 that outputs H when V2 is ahead of V1 and L when V2 is opposite, and adds a plus / minus sign to the phase difference. . FIG. 4 shows the waveforms of the input voltage and output voltage of each section in FIG.

[0003]

In the conventional phase difference measuring device, the measurement is performed by counting the time width of the phase difference difference between the two signals to be measured by using the reference clock pulse. I could only measure. Further, when the frequency of the signal under measurement fluctuates, a measurement error occurs.

[0004] It is an object of the present invention to provide a phase difference measuring apparatus capable of eliminating the limitation of the measurement frequency and measuring without causing an error even if the frequency of the signal to be measured fluctuates.

[0005]

To achieve the above object, a phase difference measuring apparatus according to the present invention comprises a first and a second AC converter for converting first and second AC inputs into rectangular waves V1 and V2.
, An exclusive-OR circuit having the V1 and V2 as inputs, and a first AND which outputs the output of the exclusive-OR circuit and V1 and outputs a phase difference V3 between V1 and V2 Circuit, a reference clock pulse generator, a second AND circuit that receives the reference clock pulse and V3 as inputs, and outputs a reference clock pulse included in the period of V3, and a reference output from the second AND circuit. A first counter that counts clock pulses, a third AND circuit that receives a reference clock pulse and V1 as inputs, and outputs a reference clock pulse included in a period of V1, and a third AND circuit that is output from the third AND circuit A second counter for counting a reference clock pulse; a divider for outputting a value obtained by dividing a count value of the first counter by a count value of the second counter; Means for resetting the second counter for each cycle, one of the edges as input V1 and V2
Detection of the other level at the timing of
And an output of the divider and an output of the advance / delay determiner are output as phase difference measurement values of the first and second AC inputs.

[0006]

According to the present invention, since the phase difference is obtained by dividing the two count values in the above configuration, no measurement error occurs even if the measured frequency fluctuates.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to FIGS. The two signals under test A1 and A2 are input to the first and second waveform shapers 1 and 2, respectively. The waveform shapers 1 and 2 output H when the input signal is positive and output L when the input signal is negative, and the signals A1 and A2 to be measured are V1 and V, respectively.
As shown in FIG. The exclusive OR circuit 3 and the first AND circuit 4 generate a phase difference pulse V3 corresponding to the phase difference between A1 and A2 from V1 and V2. The reference clock pulse CK and the phase difference pulse V3 from the reference clock pulse generator 10 are input to the second AND circuit 5, and the output is input to the first counter 7 to convert the phase difference V3 into a digital value V7. . On the other hand, the output V1 of the waveform shaper 1 and the reference clock pulse CK are input to the third AND circuit 6, and the output thereof is input to the second counter 8 to convert the pulse width of V1 into a digital value V8. The divider 21 converts the count value V7 of the first counter 7 into the count value V
Divide by 8 to determine the ratio of the phase difference to the half cycle (180 °). Since the counts of the counters 7 and 8 end at the time of the fall of V1, the signal processing unit 9 captures the output value (V7 / V8) of the divider 21 after the fall of V1.
The phase difference is calculated by the following calculation and used as a phase measurement value.

Phase difference (°) = 180 ° × V7 / V8 Thereafter, the counters 7 and 8 are reset before the start of the next count. Regarding the advance / delay of the phase, the lead / lag discriminator 1 outputs H when V2 is ahead of V1, and outputs L when V2 is opposite.
The signal processing unit 9 makes a determination based on the output signal of No. 1 and adds a positive or negative sign to the phase difference. As an example of the configuration of the processing unit 9 and the divider 21 , hardware may be configured by a microcomputer, and the above processing may be performed by software. FIG. 2 shows the time course of the input voltage and output voltage waveforms of each section in FIG.

If the measured value is not stable due to the fluctuation of the phase difference of the signal to be measured or the noise of the signal to be measured, the average value of the phase difference at each time may be obtained and used as the phase measurement value.

[0010]

As described above, according to the present invention, there is provided a phase difference measuring apparatus capable of measuring a phase difference irrespective of a measured frequency and generating no measurement error even if the measured frequency fluctuates. can do.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a phase difference measuring device according to the present invention.

FIG. 2 is a timing chart for explaining the operation of the phase difference measuring device of the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional phase difference measuring device.

FIG. 4 is a timing chart illustrating the operation of a conventional phase difference measuring device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 1st waveform shaper 2 2nd waveform shaper 3 Exclusive OR circuit 4 1st AND circuit 5 2nd AND circuit 6 3rd AND circuit 7 1st counter 8 2nd Counter 9 Signal processing unit (means for resetting the counter) 10 Reference clock pulse generator 11 Lead / lag discriminator 21 Divider A1 First AC input A2 Second AC input

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G01R 25/08 H03K 5/26

Claims (1)

(57) [Claims] 1. A method according to claim 1, wherein the first and second AC inputs are connected to a rectangular wave V1.
A first and a second wave shaper for converting to V2 and V2,
An exclusive OR circuit having the V1 and V2 as inputs, and V1 and V2 having the output of the exclusive OR circuit and V1 as inputs.
A first AND circuit that outputs a phase difference V3 of the reference clock pulse generator; a second AND circuit that receives the reference clock pulse and V3 as inputs and outputs a reference clock pulse included in a period of V3; A first counter that counts the reference clock pulse output from the second AND circuit; a third AND circuit that receives the reference clock pulse and V1 as inputs and outputs a reference clock pulse included in the period of V1; A second counter for counting the reference clock pulse output from the third AND circuit, and a divider for outputting a value obtained by dividing the count value of the first counter by the count value of the second counter. Means for resetting the first and second counters every cycle,
1 and V2 as inputs and the other at the timing of one edge
And a process proceeds to detect to lead-lag determine square level delay discriminator, position that outputs the output of the output and lead-lag discriminator of the divider as the first and the phase difference measurement value of the second AC input Phase difference measurement device.