JP2012037308A - Phase advance/delay discrimination apparatus for power-factor indicator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an apparatus and method capable of measuring advance/delay for phases of a current and a voltage of measured power in simple configuration.SOLUTION: The present invention relates to an apparatus which is used together with a digital power-factor indicator for measuring a power factor of measured power from a voltage and a current and discriminates advance/delay for phases of the current and the voltage, including: a means for detecting digital data in a predetermined term for a period of a predetermined length; a first multiplier for sequentially calculating a first product of multiplying new voltage data and former current data at a predetermined time point in a memory sequentially storing data from the detection means; a second multiplier for sequentially calculating a second product of multiplying new current data and former voltage data at a predetermined time point among data in the memory; an arithmetic circuit for integrating and averaging the first product and the second product, respectively, to determine a first arithmetic value and a second arithmetic value; a subtractor for determining a polarity of a difference of the second arithmetic value from the first arithmetic value; and a discriminator for discriminating advance/delay of the phases of the voltage and current from the polarity of the difference.

Description

  The present invention relates to an apparatus used together with a power factor meter, and relates to an apparatus for discriminating a lead / lag of a current phase with respect to a voltage phase of a target measurement power.

  The AC power supplied as a commercial power supply usually has a power factor that deteriorates because the current phase is delayed from the voltage phase as a general characteristic of the load. Therefore, the power factor is improved by measuring the power factor and applying a phase advance capacitor according to the measured power factor.

  As described above, when power is supplied from an ordinary commercial power source to an electrical device, the current phase is delayed, so that the power factor is recognized as a delayed power factor. A generally used power factor meter is configured to display only a numerical value as a (delayed) power factor.

JP-A-8-262073

  However, when private power generation is used in combination with commercial power, the above point does not necessarily apply and the delay power factor may not be limited.

  In such a situation, a power factor meter that can simply measure the power factor value is insufficient, and if the advance / delay cannot be measured, correct power factor correction measures cannot be taken.

  However, the conventional power factor meter only displays “numerical value” and does not display “advance and delay”.

  The present invention has been made in view of the above points, and an object of the present invention is to provide an apparatus and method that can measure the advance / lag of the current phase of the measured power with respect to the voltage phase with a simple configuration.

In order to achieve the above object, in the present invention,
The digital data of the voltage and current at the measured power to be measured for the power factor is given and used together with the digital power factor meter for measuring the power factor of the measured power so that the phase of the current advances with respect to the phase of the voltage A device for determining whether or not it is late,
Detecting means for detecting the digital data in a predetermined cycle over a period of a predetermined length;
A memory for sequentially accumulating data given from the detection means;
A first multiplier that sequentially calculates a first product of a voltage and a current at a predetermined time by multiplying predetermined new voltage data and predetermined old current data among the data stored in the memory;
A second multiplier for sequentially calculating a second product of current and voltage at the predetermined time by multiplying predetermined new current data and predetermined old voltage data among the data stored in the memory;
An arithmetic circuit that integrates and averages the first product and the second product separately to obtain a first arithmetic value and a second arithmetic value, and
A subtractor for obtaining a polarity of a difference obtained by subtracting the second calculated value from the first calculated value;
A power discriminator phase discriminator comprising: a discriminator for discriminating the advance or delay of the phase of the current with respect to the phase of the voltage from the polarity of the difference;
Is to provide.

  As described above, the present invention can determine the advance and delay of the phase of the current with respect to the voltage without adding any complexity to the configuration by adding each element below the detection means to the digital power factor meter. Regardless of the power to be used, appropriate measures for power factor improvement can be taken.

Explanatory drawing which shows the structure of a general digital power factor meter. FIG. 2 is an explanatory diagram showing a configuration example in which a phase advance / lag measurement function is added to the power factor meter of FIG. 1; FIG. 3 is an explanatory diagram showing another configuration example in which a phase advance / lag measurement function is added to the power factor meter of FIG. 1; Explanatory drawing which shows the structure of one Example of this invention. FIG. 5 is an explanatory diagram illustrating a configuration of a shift register used in the embodiment illustrated in FIG. 4. Explanatory drawing which shows operation | movement of the Example shown in FIG.

  DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the technology that forms the basis of the present invention will be described with reference to the accompanying drawings, and then embodiments of the present invention will be described.

General power factor meter

ここで、P＝測定電力
U＝電圧
I＝電流
と表される。 FIG. 1 is a block diagram showing a configuration of a general digital power factor meter. If the power factor is expressed as PF,

Where P = measured power
U = Voltage
I = current.

When the voltage U and the current I are digital signals formed by A / D conversion by sampling, the voltage U, the current I, and the power P are expressed as follows.

  FIG. 1 shows a configuration of a general digital power factor meter that obtains a power factor PF using this digital signal. In this circuit, an alternating voltage u and an alternating current i are given as inputs, the voltage u is transformed by the transformer circuit 11, digitized by the A / D converter circuit 12, and given to the digital arithmetic circuit 30, and the current i is converted into current. The current is converted by the circuit 21 a, converted to a voltage by the voltage conversion circuit 21 b, digitized by the A / D conversion circuit 22, and supplied to the digital arithmetic circuit 30.

  The digital arithmetic circuit 30 performs a power factor calculation based on two digital signals obtained by applying a sampling clock to the two A / D conversion circuits 12 and 22 and digitizing them, and a power factor signal as a measurement result. Is output.

  However, this power factor signal indicates only the magnitude of the power factor and does not include phase components, that is, advance and delay. This is because, in the case of a commercial power supply, the current phase is usually delayed and it is not necessary to measure the delay. However, in the present situation where a customer has a power generation facility and sells power to an electric power company, the power factor of the measured power with the advanced current phase may be measured.

  FIG. 2 shows a circuit configuration example in which a phase shift circuit is added to the circuit of FIG. 1 so that phase advance and delay can be measured. For this purpose, a phase shift circuit 41 and an A / D conversion circuit 42 for digitizing the voltage signal phase shifted by the phase shift circuit 41 are added to the circuit of FIG.

  3 is provided with a PLL circuit 40 in place of the phase shift circuit 41 and the A / D conversion circuit 42 in the circuit of FIG. The circuit of FIG. 3 measures the phase angle based on the discrete Fourier transform. Using this discrete Fourier transform means that the number of samples per cycle of the measurement signal is kept at a constant N times, and therefore a sampling clock having a frequency N times the frequency of the measurement signal is generated. A / D conversion is performed in synchronization with the frequency of the measurement signal using the PLL circuit.

  These circuits in FIGS. 2 and 3 can measure the power factor with the advance and delay of the current phase, but this lead and lag measurement function makes the configuration considerably more complicated than the circuit of FIG. There's a problem.

  The present invention has been made to solve this problem, and provides a power factor meter with a phase advance / delay measurement function with a simple circuit configuration.

  FIG. 4 shows a circuit configuration of a power factor meter with a current phase advance / delay measurement function according to the present invention. In this circuit, the measured voltage and current are digitized, and the digital signal is given to the input terminal IN.

  In FIG. 4, the lower part of the drawing, that is, the one below the one-dot chain line is shown as a more detailed configuration, but shows a configuration equivalent to the digital arithmetic circuit 30 shown in FIG. 1, that is, a part of the power factor meter. There is a circuit configuration newly added in the present invention from the one-dot chain line, that is, a phase advance / delay measurement circuit.

First, regarding the power factor meter, the voltage digital signal u (k) and the current digital signal i (k) given from the input terminal IN are given to the multipliers 101, 201 and 301, and the voltage square value u ² , current 2 The multiplication value i ² and the multiplication value u · i of the voltage and current are obtained and integrated by the computing units 102, 202 and 302, and the average value is obtained.

Next, the outputs u ² and i ² of the computing units 102 and 202 are given to the route computing units 103 and 203 to calculate the respective root values, and are given to the multiplier 303 to divide the product U · I between them. Is provided to the vessel 304. The divider 304 is supplied with the measured power value P from the calculator 302, calculates the power factor P / U · I, and sends it to the output terminal OUT1 as the measured power factor value.

  On the other hand, the phase lead / lag measuring circuit sequentially stores time series signals in the shift register 1 as a memory, and supplies the oldest data u (kM), i (kM) of the shift register 1 to the input terminal IN. The latest data u (k) and i (k) thus obtained are given to the multipliers 2a and 2b.

  Here, the latest data u (k), i (k) should be called the latest value or current value of the measured voltage and current, while the oldest data u (kM), i (kM) is This is data (values) of voltage and current at a time point preceding a period corresponding to a predetermined phase from the present time. As the predetermined phase, for example, a time point preceding by 90 degrees is selected.

  5 (a) and 5 (b) show the data accumulation state in the shift register 1, FIG. 5 (a) shows the state before update, and FIG. 5 (b) shows the state after update. ing. As shown in FIG. 5 (a), the latest data u (k), i (k) is given to the shift register 1 from above, and the oldest data u is shown in FIG. 5 (b). (kM) and i (kM) are taken out from the lower part of the figure.

  Then, using the latest data u (k), i (k) and the oldest data u (kM), i (kM) in the shift register 1, the multiplier 2a uses u (k) · i (kM). However, i (k) · u (kM) is calculated in the multiplier 2b.

両演算器3a,3bの出力ＬＤ，LGが減算器４に与えられて

D＝LD−LG (7)

が算出され、得られた差Dは判定器５に送られ「進み」、「遅れ」あるいは「進みも遅れもなし」が判定されて出力端子OUT2に出力される。 That is, in the multiplier 2a, the product of the latest voltage signal and the oldest current signal is obtained, and in the multiplier 2b, the product of the latest current signal and the oldest voltage signal is obtained and given to the arithmetic units 3a and 3b. . In the arithmetic units 3a and 3b, values obtained by averaging the integrated values over a predetermined period of the measurement signals u (k) i (kM) and u (kM) i (k) are obtained by the following equations (5) and (6). .

The outputs LD and LG of both arithmetic units 3a and 3b are given to the subtractor 4.

D = LD−LG (7)

Is calculated, and the obtained difference D is sent to the determiner 5 to determine “advance”, “delay” or “no advance or delay” and output to the output terminal OUT2.

  As a result, the power factor value and the phase advance and delay are displayed from the outputs of the two output terminals OUT1 and OUT2, and it becomes clear what reactance needs to be used and how much to improve the power factor.

  FIG. 6 is a flowchart showing the operation of the phase advance / delay measurement circuit (upper part of FIG. 4) in the circuit shown in FIG. In the circuit shown in FIG. 4, the voltage u (k) and current i (k) applied to the input terminal IN are stored as a pair in the shift register 1 as the latest data (step S1).

  The shift register 1 is sequentially given the latest data in the sampling clock cycle, and is stored as voltages u (k-1), u (k-2), u (k-3),. M pairs of data are stored up to u (kM) and i (kM).

  The latest data thus obtained, that is, voltage u (k) and current i (k) and the oldest data, that is, voltage u (kM) and current i (kM) are applied to multipliers 2a and 2b. (Step S2). Multiplier 2a multiplies voltage u (k) and current i (kM), and multiplier 2b multiplies voltage u (kM) and current i (k) (step S3). .

  The multiplication results of the multipliers 2a and 2b are given to the calculators 3a and 3b, and the calculations shown in steps S4 to S7 are performed. That is, the first product u (k) · i (kM) that is the multiplication result of the multiplier 2a and the second product u (kM) · i (k) that is the multiplication result of the multiplier 2b are integrated separately. (Step S4).

  The operations in steps S1 to S4 are repeated N times while being sequentially switched by “k ← k + 1” (step S5). Then, average values for the first product and the second product during the repetitive operation, that is, the first calculation value and the second calculation value are obtained (step S7), and LD, LG according to the above formulas (5) and (6) are obtained. Is obtained (step S8) and sent to the subtractor 4.

  In the subtracter 4, D = LD-LG is calculated (step S9), and the obtained difference D is given to the determiner 5. The determination unit 5 determines D> 0 (delay), D = 0 (in-phase, that is, no advance delay), and D <0 (advance) (steps S10, S11, S12, S13, S14).

  If the current phase is delayed in accordance with this determination result, the power factor is improved by phase adjustment using a phase advance capacitor, and if it is advanced, phase adjustment is performed using a phase delay inductance.

  As described above, the present invention can display the advance and delay of the current phase in addition to the numerical value of the power factor, while having a simple circuit configuration. That is, when compared with the circuit of FIG. 1, the arithmetic circuits LD and LG required in the present invention need only partially use the digital arithmetic circuit 30, and the shift register 1 uses the existing memory for the power factor meter. It ’s enough. Further, when compared with the circuit of FIG. 2, the phase shift circuit 11 is unnecessary and a part of the A / D conversion circuit can be omitted. Furthermore, the PLL circuit 40 is not necessary as compared with the circuit of FIG. 3, and the digital arithmetic circuit 30 can be greatly simplified.

Modified example

  In the above embodiment, a shift register is used to form time-series data. However, such processing may be performed by software processing from a series of digital data. The subsequent data processing can also be performed by software.

1 shift register, 2 multiplier, 3 operator, 4 subtractor, 5 determiner,
101 multiplier, 102 calculator, 103 root calculator, 201 multiplier, 202 calculator, 203 root calculator, 301 multiplier, 302 calculator, 303 multiplier, 304 calculator.

Claims (4)

The digital data of the voltage and current at the measured power to be measured for the power factor is given and used together with the digital power factor meter for measuring the power factor of the measured power so that the phase of the current advances with respect to the phase of the voltage A device for determining whether or not it is late,
Detecting means for detecting the digital data in a predetermined cycle over a period of a predetermined length;
A memory for sequentially accumulating data given from the detection means;
A first multiplier that sequentially calculates a first product of a voltage and a current at a predetermined time by multiplying predetermined new voltage data and predetermined old current data among the data stored in the memory;
A second multiplier for sequentially calculating a second product of current and voltage at the predetermined time by multiplying predetermined new current data and predetermined old voltage data among the data stored in the memory;
An arithmetic circuit that integrates and averages the first product and the second product separately to obtain a first arithmetic value and a second arithmetic value, and
A subtractor for obtaining a polarity of a difference obtained by subtracting the second calculated value from the first calculated value;
And a discriminator for discriminating the advance or delay of the phase of the current with respect to the phase of the voltage from the polarity of the difference. In the phase determination device for power factor meter according to claim 1,
The predetermined new voltage data and the predetermined new current data are a phase determination device for a power factor meter which is the latest value of the measured voltage and current. The phase determination device for a power factor meter according to claim 1,
The predetermined old voltage data and the predetermined old current data are power factor phase discriminating devices that are data at a time point preceding a predetermined phase in the measurement voltage and current. The phase determination device for a power factor meter according to claim 1,
A phase determination apparatus for a power factor meter, wherein the memory is a shift register.

Images