JPH05119070A - Digital oscilloscope - Google Patents

Abstract

PURPOSE:To provide a digital oscilloscope which can surely measure waveforms at equivalent sampling time and can properly perform analysis control, etc. CONSTITUTION:This digital oscilloscope is provided with an equivalent sample data control circuit 5 which measures the time interval between a trigger point and clock and inputs the address corresponding to the time interval to a data memory 3 after generating the address and data updating discrimination circuit 6 which stores the address after the address is inputted and outputs the updated state of the address to a display circuit 8 for display.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital oscilloscope, and more particularly to a digital oscilloscope capable of clarifying the update completion state of the stored memory contents by the measured data when displaying the measured data by the equivalent sampling method.

[0002]

2. Description of the Related Art In a digital oscilloscope, the sampling oscilloscope method uses a signal sampling technique to extract samples which are instantaneous voltage components of sequentially different portions of a periodic input signal and reproduce and display the input signal. .. This sampling method includes a random sampling method and a real-time sampling method, but an equivalent sampling method is often used.

[0003]

In the equivalent sampling method, the measured data at the trigger point is gradually stored in the memory by using the repetitive signal waveform as the reference and the C
The original waveform is reproduced by reconstructing the data in the memory by the PU or the like.

In this case, particularly in the random sampling method, unless the data stored in the memory after starting the measurement or the data remaining in the memory before starting the measurement is not distinguished, the measured waveform is reproduced correctly. It cannot be determined whether or not there is. In such a case, when performing analysis or automatic control based on the measured waveform, the authenticity of the measurement result is likely to be erroneous because the authenticity of the waveform cannot be reliably obtained.

The present invention has been made in view of the above points, and an object of the present invention is to realize a digital oscilloscope which can reliably perform waveform measurement at the time of equivalent sampling and can properly perform analysis control and the like.

[0006]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a trigger circuit which detects a trigger point exceeding a trigger level of measurement data and generates a trigger, and a sample clock which samples the trigger point and data. An equivalent sample data control circuit for designating an address by a time difference from the data, a data memory for storing the measured data converted into a digital signal at an address designated by the equivalent sample data control circuit, and the equivalent sample data control circuit A data update determination circuit for storing that an address has been accessed and for detecting an update state of data in a predetermined range of addresses, and a display circuit for displaying the measured data and the data update state. Is.

[0007]

The trigger circuit generates a trigger at the trigger point that exceeds the trigger level. The equivalent sample data control circuit stores the measured data in the data memory by designating the address corresponding to the time difference between the trigger and the clock immediately after. Further, the address designated by the equivalent sample data control circuit is input to the data update determination circuit, and the data update determination circuit stores the address and outputs the updated state of the address data to display it on the display circuit.

[0008]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention. In the figure, 1 is an AD converter for converting an analog signal input to the measurement input terminal 2 into a digital signal, and 3 is a data memory for storing digitized measurement data.

[0009] 4 has a preset trigger level,
The trigger circuit detects a trigger point where an input signal exceeds the trigger level and generates a trigger. Reference numeral 5 is an equivalent sample data control circuit that controls the storage of measurement data by designating an address on the data memory 3 according to the time difference between the trigger point and the sample clock for sampling data. Reference numeral 6 denotes a data update determination circuit which stores that the address designated by the equivalent sample data control circuit 5 is accessed, detects that all the data in the address in the predetermined range has been updated, and outputs a data update determination signal. is there.

Reference numeral 7 denotes an arithmetic control circuit for controlling data arithmetic processing and operation of the entire apparatus, and 8 displays a data update determination signal RC output from the data update determination circuit 6, and
It is a display circuit for displaying measurement data. Further, the above signals and data are communicated with the outside of the device through the external communication circuit 9. Reference numeral 10 is a clock generator that supplies a clock for data sampling to the AD converter 1, and also inputs the clock to the equivalent sample data control circuit 5 for measuring the time difference from the trigger point.

Next, the operation of the embodiment configured as described above will be described. The measurement data input from the measurement input terminal 2 is converted into a digital signal by the AD converter 1. or,
The measurement data is also input to the trigger circuit 4, a trigger point is generated by detecting a trigger point that intersects with the trigger level, and is input to the equivalent sample data control circuit 5. The equivalent sample data control circuit 5 measures the time difference from the clock immediately after the input trigger, and the data memory 3 corresponding to this time difference.
Specify the address above. The digital data output from the AD converter 1 is stored in the address of the data memory 3.

The above address is also input to the data update determination circuit 6, and the data update determination circuit 6 stores that the address designated by the equivalent sample data determination circuit 5 has been accessed, and the data of the address within the predetermined range is stored. When all the data have been updated, the fact is detected and the data update determination signal R indicating that all the data has been updated is given to the arithmetic control circuit 7.
Output C.

FIG. 2 is a block diagram of an example of the data update determination circuit 6. In the figure, 11 is a decoder for decoding the address input from the equivalent sample data control circuit 5, to which addresses A _{0 to} A _n are input,
When a certain address is designated, a decode signal corresponding to that address is output. 12a to 12n are decoders 1
This is a flip-flop in which the voltage H is output from the Q terminal when each output of 1 is input. When an address is designated and a decode signal is output once, the flip-flop 12
It is stored that the address is designated by a to 12n. The fact that this address is specified more than once means that the data at that address has been updated. That is, the data before the measurement is updated and does not remain. Therefore, all the measured data on the data memory 3 have been updated at the stage where all the addresses are designated. At this time, the output signals of the flip-flops 12a to 12n connected to all the decoded signals are all "1". This output is input to the AND circuit 13, the logical product is obtained, and the data update determination signal RC is output.

Based on the data update determination signal RC, the data update determination circuit 6 causes the display circuit 8 to display the progress of data update in the data memory 3 at the time of equivalent sampling, and causes the external communication circuit 9 to communicate with the outside. Or

Thus, it can be seen that all the measurement data displayed on the display circuit 8 when the data update determination signal RC is displayed on the display circuit 8 is data after the start of measurement. As described above, according to this embodiment, it is possible to know whether the data displayed on the display circuit is the data after the start of measurement or the data that was left in the data memory before, and the waveform of the equivalent sample It becomes possible to prevent the trouble caused by the incompleteness of the data update when performing the analysis or the control based on this, and the reliable observation analysis of the waveform can be performed. Further, by outputting this signal to the outside, stable and reliable operation can be secured during automatic measurement and automatic control.

The present invention is not limited to the above embodiment. FIG. 3 is a block diagram of a data update determination circuit 6 according to another embodiment of the present invention. In the figure, the same parts as those in FIG. 2 are designated by the same reference numerals. 14a to 14 in the figure
n is a pulse conversion circuit that converts the rising edge of the output data of the flip-flops 12a to 12n into a pulse, and 15 is an output line of each pulse conversion circuit 14a to 14n that receives a pulse from which pulse conversion circuit 14a to 14n. Is an OR circuit that outputs "1", and 16 is a counter that counts the number of outputs of the OR circuit 15.

In this circuit, each flip-flop 12a ...
The output of 12n is converted into a pulse by the pulse conversion circuits 14a to 14n and input to the OR circuit 15, and the OR circuit 15 outputs one pulse each time the pulse is input and inputs the pulse to the counter 16. The counter 16 outputs the data update determination signal RC when counting the number of input pulses and counting the number of decode signals output from the decoder 11.
After this signal output, the circuit is similar to that of FIG.

In the circuit of this embodiment, the rate of data update can be sequentially grasped by periodically reading the count value of the counter 16, and based on this, the update rate is displayed on the display circuit 8, for example. By doing so, the user can know the current state of the equivalent sample.

FIG. 4 shows another embodiment of the data update determination circuit 6. In the figure, reference numeral 21 is an address controller which receives the input address of the equivalent sample data control circuit 5 and converts it into the address of the memory 22 by the address input from the address bus of the CPU.

In this circuit, a memory 22 is used for storing data updates. First, the contents of the memory are cleared to 0 before measurement. Then, after the measurement is started, "1" is written in the same address as the data memory 3. When the contents of the memory 22 are all "1", the CPU outputs the data update determination signal RC. The subsequent data processing and the like are the same as those in the embodiment of FIG.

In this circuit, the dependence on software is large. From the contents of this memory 22, it is possible to mark which part of the displayed waveform has been updated.

[0022]

As described above in detail, according to the present invention, it is possible to grasp the update completion status of measurement data, ensure waveform observation during equivalent sampling, and perform digital analysis control correctly. It is possible to realize an oscilloscope, and the practical effect is great.

[Brief description of drawings]

FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram of an example of a data update determination circuit of the device of the embodiment.

FIG. 3 is a block diagram of another example of a data update determination circuit.

FIG. 4 is a block diagram of still another example of the data update determination circuit.

[Explanation of symbols]

 3 data memory 4 trigger circuit 5 equivalent sample data control circuit 6 data update determination circuit 8 display circuit

Claims (1)

[Claims] 1. A trigger circuit (4) for generating a trigger by detecting a trigger point exceeding a trigger level of measurement data, and equivalent sample data for designating an address by a time difference between the trigger point and a sample clock for sampling the data. A control circuit (5), a data memory (3) for storing the measurement data converted into a digital signal at an address specified by the equivalent sample data control circuit (5), and the equivalent sample data control circuit (5) A data update determination circuit (6) for storing that the accessed address has been accessed and for detecting the update status of the data in a predetermined range of addresses, and a display circuit (8) for displaying the measured data and the data update status. A digital oscilloscope characterized by: