JPH11153625A - Waveform memory device - Google Patents

Waveform memory device

Info

Publication number
JPH11153625A
JPH11153625A JP9321140A JP32114097A JPH11153625A JP H11153625 A JPH11153625 A JP H11153625A JP 9321140 A JP9321140 A JP 9321140A JP 32114097 A JP32114097 A JP 32114097A JP H11153625 A JPH11153625 A JP H11153625A
Authority
JP
Japan
Prior art keywords
converter
phase
sample
memory
equivalent
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9321140A
Other languages
Japanese (ja)
Other versions
JP3429993B2 (en
Inventor
Noboru Hosokawa
昇 細川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Denshi KK
Original Assignee
Hitachi Denshi KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Denshi KK filed Critical Hitachi Denshi KK
Priority to JP32114097A priority Critical patent/JP3429993B2/en
Publication of JPH11153625A publication Critical patent/JPH11153625A/en
Application granted granted Critical
Publication of JP3429993B2 publication Critical patent/JP3429993B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Abstract

PROBLEM TO BE SOLVED: To make A/D converter for equivalent sampling unnecessary and make noise generation due to the characteristic of multi-phase A/D converter impossible during equivalent sampling, by performing equivalent sampling using only a single phase of the multi-phase A/D converter of real time sampling. SOLUTION: Four phase clock is generated from a sample clock of four phase clock generation circuit 15, and a digitizer system at first phase of an A/D converter 7 and a memory 11 for sample, second phase of a converter 8 and a memory 12 for sample, third phase of an A/D converter 9 and a memory 13, and fourth phase of a converter 10 and a memory 14 are functioned by turn to sample input signal. As only one system of multi-phase converter is used in equivalent sampling to digitize, the characteristic difference of multiple A/D converter becomes no relation. Also, as no digitizing circuit for equivalent sample is used, the system is realized with small rise of cost and consumption power. When this device is used in an oscilloscope, the waveform of the memory signal is indicated with an indication circuit 23 by way of a control circuit 22.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、オシロスコープ等
の波形記憶装置における等価サンプリング回路の改善に
関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in an equivalent sampling circuit in a waveform storage device such as an oscilloscope.

【0002】[0002]

【従来の技術】従来の技術としては、オシロスコープを
例として、図2、図3のブロック図を用いて説明する。
超高速サンプリングを行う波形記憶装置では、普通AD
変換器を複数個用いてサンプリングのクロックの位相差
を変えて高速サンプリングを行っている場合が多いが、
それでも実時間サンプリングを越えるタイムレンジで
は、等化サンプルを用いる。
2. Description of the Related Art As a conventional technique, an oscilloscope will be described as an example with reference to block diagrams shown in FIGS.
In a waveform storage device that performs ultra-high speed sampling,
In many cases, high-speed sampling is performed by changing the phase difference of the sampling clock using a plurality of converters.
Still, in the time range beyond real-time sampling, equalized samples are used.

【0003】従来は、図2に示すように実時間サンプル
Bを行う系列とは別に等価サンプルA自身用の回路を持
っていた。1は入力部、2はアッテネータ、3はアン
プ、4は等価サンプル用サンプルホルダ、5は等価サン
プル用AD変換器、6は等価サンプル用メモリ、7から
10は実時間サンプル用AD変換器、11から14は実
時間サンプル用メモリ、15は4相クロック発生回路、
16はクロック発生回路、17は分周回路、18はサン
プルコントロール回路、19はトリガゲート発生回路で
ある。22は表示制御回路、23はLCD等の表示器を
含む表示回路である。
Conventionally, as shown in FIG. 2, a circuit for the equivalent sample A itself has been provided separately from the sequence for performing the real-time sample B. 1 is an input unit, 2 is an attenuator, 3 is an amplifier, 4 is a sample holder for equivalent samples, 5 is an AD converter for equivalent samples, 6 is a memory for equivalent samples, 7 to 10 are AD converters for real time samples, 11 To 14 are real-time sampling memories, 15 is a four-phase clock generation circuit,
16 is a clock generating circuit, 17 is a frequency dividing circuit, 18 is a sample control circuit, and 19 is a trigger gate generating circuit. 22, a display control circuit; and 23, a display circuit including a display such as an LCD.

【0004】実時間最高サンプルまでは、7から14ま
での実時間サンプル用AD変換器とメモリで多相で波形
記憶を行い、それ以上の水平掃引レンジでは、4から6
の等価サンプル用の系を用いて繰り返しサンプリングを
行い、等価サンプルを行っていた。
[0004] Up to the maximum real-time sample, waveforms are stored in polyphase by an AD converter and memory for real-time samples from 7 to 14;
Were repeatedly sampled using the equivalent sample system described above to obtain equivalent samples.

【0005】一方、図3の従来例では、実時間サンプル
用AD変換器及びメモリを用いて、等価サンプル時は、
20,21のスイッチ回路を切り替えて、4のサンプル
ホルダを用いて実時間サンプルと同様に等価サンプルを
行っていた。
On the other hand, in the conventional example shown in FIG. 3, using an AD converter and memory for real-time sampling, at the time of equivalent sampling,
By switching the switch circuits 20 and 21, the equivalent sample was performed using the sample holder 4 in the same manner as the real-time sample.

【0006】22は表示制御回路、23はLCD等の表
示器を含む表示回路である。
Reference numeral 22 denotes a display control circuit; and 23, a display circuit including a display such as an LCD.

【0007】[0007]

【発明が解決しようとする課題】従来の技術で、例えば
図2の例では、実時間サンプル用と等価サンプル用の2
系統のハードウェアが必要となりコストアップになり、
低消費電力、小型化にも不利になる。
In the conventional technique, for example, in the example of FIG.
System hardware is required, cost increases,
It is disadvantageous for low power consumption and miniaturization.

【0008】図3の例では、ハードウェアが、実時間サ
ンプルと等価サンプルで全く同じというメリットがある
が、等価サンプルで扱う広帯域信号を多相のAD変換器
でサンプルするために、多相同士の特性のズレが記憶波
形のノイズ成分となりS/Nの悪い等価サンプルとな
る。
In the example shown in FIG. 3, there is an advantage that the hardware is exactly the same between the real-time sample and the equivalent sample. Is a noise component of the stored waveform, and becomes an equivalent sample having a poor S / N.

【0009】本発明の第一の目的は、多相AD変換器を
用いた波形記憶装置でコスト、消費電力を大幅増になら
ずに等価サンプルを実現することを目的とする。
A first object of the present invention is to realize an equivalent sample in a waveform storage device using a polyphase AD converter without significantly increasing cost and power consumption.

【0010】第二の目的は、多相AD変換器の特性差に
よる等価サンプル時のノイズ量を低減することにある。
A second object is to reduce the amount of noise at the time of equivalent sampling due to the characteristic difference of the polyphase AD converter.

【0011】[0011]

【課題を解決するための手段】本発明は、上記の目的を
達成するため、実時間サンプルの多相AD変換器の1相
のみを用いて等価サンプルを行うようにしたものであ
る。
According to the present invention, in order to achieve the above object, an equivalent sample is obtained by using only one phase of a real-time sample polyphase AD converter.

【0012】これにより等価サンプル用のAD変換器系
を必要とせず、また、多相AD変換器の特性差によるノ
イズを等価サンプル時に発生しない。
This eliminates the need for an AD converter system for equivalent samples, and does not generate noise due to differences in characteristics of the polyphase AD converters during equivalent sampling.

【0013】[0013]

【発明の実施の形態】以下本発明の実施例をオシロスコ
ープを例にして図1により説明する。1は入力部、2は
アッテネータ、3はアンプ、7から10はAD変換器、
11から14はサンプル用メモリ、15は4相クロック
発生回路、16はクロック発生回路、17は分周回路、
18はサンプルコントロール回路、19はトリガゲート
発生回路、20と21はスイッチ回路、である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. 1 using an oscilloscope as an example. 1 is an input unit, 2 is an attenuator, 3 is an amplifier, 7 to 10 are AD converters,
11 to 14 are sampling memories, 15 is a four-phase clock generator, 16 is a clock generator, 17 is a frequency divider,
18 is a sample control circuit, 19 is a trigger gate generation circuit, and 20 and 21 are switch circuits.

【0014】クロック発生回路16からのクロックを分
周回路17で設定されたタイムレンジに応じて分周し、
サンプルクロックを作る。4相クロック発生回路15で
サンプルクロックから4相クロックを発生させ、AD変
換器7とサンプル用メモリ11の1相目、AD変換器8
とサンプル用メモリ12の2相目、AD変換器9とサン
プル用メモリ13の3相目、AD変換器10とサンプル
用メモリ14の4相目のディジタイザの系を順次交互に
動かして、入力信号をサンプリングする。
The frequency of the clock from the clock generation circuit 16 is divided according to the time range set by the frequency dividing circuit 17,
Make a sample clock. The four-phase clock generation circuit 15 generates a four-phase clock from the sample clock, and outputs the first phase of the AD converter 7 and the sampling memory 11, the AD converter 8
And the second phase of the sample memory 12, the third phase of the AD converter 9 and the sample memory 13, and the digitizer system of the fourth phase of the AD converter 10 and the sample memory 14 are sequentially and alternately moved to obtain the input signal. Is sampled.

【0015】実時間サンプルの時は、スイッチ20,2
1は、下側に接続され入力信号は、4のサンプルホルダ
を通さずにディジタイズされる。すなわち、トリガゲー
ト発生回路19で入力信号からトリガが発生すると、サ
ンプルコントロール回路18でトリガ以降のサンプルク
ロックをカウントし、分周回路17からのサンプルクロ
ックを停止させ、サンプルを止める。これにより、トリ
ガ前後の規定の波形がメモリ11から14に記憶される
ことになる。
At the time of real time sampling, switches 20 and 2
1 is connected to the lower side and the input signal is digitized without passing through 4 sample holders. That is, when the trigger is generated from the input signal by the trigger gate generation circuit 19, the sample clock after the trigger is counted by the sample control circuit 18, the sample clock from the frequency dividing circuit 17 is stopped, and the sampling is stopped. Thereby, the prescribed waveforms before and after the trigger are stored in the memories 11 to 14.

【0016】等価サンプル時は、スイッチ回路20と2
1を上側に接続して4のサンプルホルダを通して、AD
変換器7で入力波形をディジタイズする。トリガが来て
サンプルが止まったとき、実時間サンプル時は、メモリ
11〜14を順次交互に読んでいたが、等価サンプル時
は、メモリ11のみを読み出す。
At the time of equivalent sampling, the switch circuits 20 and 2
1 is connected to the upper side, through the sample holder of 4, AD
The input waveform is digitized by the converter 7. When the trigger comes and the sampling stops, the memories 11 to 14 are sequentially read alternately during the real-time sampling, but only the memory 11 is read during the equivalent sampling.

【0017】以上のようにして等価サンプル時は、多相
のAD変換器の1系統のみを用いてディジタイズさせる
ので、多相AD変換器の特性差は、関係なくなる。ま
た、等価サンプル用に特別にディジタイズ回路を用いて
いないのでコスト、消費電力のアップは、少なく実現で
きる。この波形記憶装置をオシロスコープに用いた場合
には、メモリに記憶された信号は表示制御回路22を介
して、表示器を有する表示回路23にて波形表示され
る。
As described above, at the time of equivalent sampling, digitization is performed using only one system of the polyphase AD converter, so that the characteristic difference of the polyphase AD converter becomes irrelevant. Further, since a digitizing circuit is not specially used for the equivalent sample, it is possible to realize a small increase in cost and power consumption. When this waveform storage device is used for an oscilloscope, the signal stored in the memory is displayed as a waveform by a display circuit 23 having a display via a display control circuit 22.

【0018】[0018]

【発明の効果】以上のようにして等価サンプル時は、多
相のAD変換器の1系統のみを用いてディジタイズさせ
るので、多相AD変換器の特性差は、関係なくなる。ま
た等価サンプル用に特別にディジタイズ回路を用いてい
ないのでコスト、消費電力のアップは、少なく実現でき
る。
As described above, at the time of equivalent sampling, digitization is performed using only one system of the polyphase AD converter, so that the characteristic difference of the polyphase AD converter becomes irrelevant. Further, since a digitizing circuit is not specially used for the equivalent sample, the cost and power consumption can be reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例の全体構成を示すブロック
図。
FIG. 1 is a block diagram showing an overall configuration of an embodiment of the present invention.

【図2】従来技術を説明するブロック図。FIG. 2 is a block diagram illustrating a conventional technique.

【図3】従来技術を説明するブロック図。FIG. 3 is a block diagram illustrating a conventional technique.

【符号の説明】[Explanation of symbols]

1:入力部、2:アッテネータ、3:アンプ、7から1
0:AD変換器、11から14:サンプル用メモリ、1
5:4相クロック発生回路、16:クロック発生回路、
17:分周回路、18:サンプルコントロール回路、1
6:トリガゲート発生回路、20と21:スイッチ回
路、5:等価サンプル用AD変換器、6:等価サンプル
用メモリ。
1: input section, 2: attenuator, 3: amplifier, 7 to 1
0: AD converter, 11 to 14: sample memory, 1
5: 4-phase clock generation circuit, 16: clock generation circuit,
17: frequency divider circuit, 18: sample control circuit, 1
6: trigger gate generation circuit, 20 and 21: switch circuit, 5: AD converter for equivalent sample, 6: memory for equivalent sample.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 複数のAD変換器により構成した多相A
D変換器を用いて単体のAD変換器以上のサンプル周波
数を行う波形記憶装置であって、該多相AD変換器の最
高サンプル周波数以上のサンプル周波数を等価的に実現
する等価サンプル方式において、 該多相AD変換器の1相のみを用いて等価サンプルを行
うことを特徴とした波形記憶装置。
1. A polyphase A comprising a plurality of AD converters
What is claimed is: 1. A waveform storage device which performs a sampling frequency higher than that of a single A / D converter by using a D converter. A waveform storage device for performing equivalent sampling using only one phase of a polyphase AD converter.
JP32114097A 1997-11-21 1997-11-21 Waveform storage device Expired - Fee Related JP3429993B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32114097A JP3429993B2 (en) 1997-11-21 1997-11-21 Waveform storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32114097A JP3429993B2 (en) 1997-11-21 1997-11-21 Waveform storage device

Publications (2)

Publication Number Publication Date
JPH11153625A true JPH11153625A (en) 1999-06-08
JP3429993B2 JP3429993B2 (en) 2003-07-28

Family

ID=18129258

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32114097A Expired - Fee Related JP3429993B2 (en) 1997-11-21 1997-11-21 Waveform storage device

Country Status (1)

Country Link
JP (1) JP3429993B2 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05119070A (en) * 1991-09-30 1993-05-14 Yokogawa Electric Corp Digital oscilloscope
JPH0563128U (en) * 1992-01-31 1993-08-20 横河電機株式会社 High-speed A / D conversion circuit
JPH06324085A (en) * 1993-05-17 1994-11-25 Yokogawa Electric Corp Digital oscilloscope
JPH0774634A (en) * 1993-08-31 1995-03-17 Hitachi Denshi Ltd Waveform storage device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05119070A (en) * 1991-09-30 1993-05-14 Yokogawa Electric Corp Digital oscilloscope
JPH0563128U (en) * 1992-01-31 1993-08-20 横河電機株式会社 High-speed A / D conversion circuit
JPH06324085A (en) * 1993-05-17 1994-11-25 Yokogawa Electric Corp Digital oscilloscope
JPH0774634A (en) * 1993-08-31 1995-03-17 Hitachi Denshi Ltd Waveform storage device

Also Published As

Publication number Publication date
JP3429993B2 (en) 2003-07-28

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