JPH08194013A - Waveform memory device - Google Patents

Abstract

PURPOSE: To deal with the sampling of higher speed by detecting the maximum value and the minimum value of the data of each phase which is sent in order for a fixed period of time at the preceding stage of the memory of each phase of a digital data memory circuit and storing it into the memory of a succeeding stage. CONSTITUTION: An analog input signal from Vin is digitalized in sequence by AD converters 1 to 4 operating in four phases and latched by latches 5 to 20 connected in four phases to the succeeding stage of each AD converter. The latch output is simultaneously latched by latches 101, 102 in a circuit 21 for detecting the maximum value and the minimum value in the order of phase lags A-1, A-2... A-16, and the phase-arranged data is outputted to A-1a and A-2a. Two input data are compared with each other in a comparater circuit 121, and a larger data is outputted to S-1 and a smaller data is outputted to S-2. A circuit 131 for detecting the maximum value detects the maximum value from the data of a larger side and outputs it to B-1 to store it in the memory 22 of the succeeding stage, and similarly detects the minimum value from the data of smaller side and outputs it to B-2 to store it in the memory 26 of the succeeding stage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sampling data processing system for a waveform storage device such as a digital oscilloscope.

[0002]

BACKGROUND OF THE INVENTION The present invention relates to a peak of a waveform for extracting and storing the maximum value or minimum value or maximum value and minimum value (that is, peak value) of an input signal suitable for use in combination with a display device such as an oscilloscope. The present invention relates to a value detection (extraction) storage method and device.

Conventionally, oscilloscopes have been used for observing waveforms of various data, and especially research and development of electronic equipment.
It was indispensable and useful for production, etc., but there was one aspect that it could not store waveforms. However, along with the development of digital technology, a digitized oscilloscope has been developed and waveform storage has become possible. Among them, the waveform storage device stores the analog input signals of various data after digital processing and stores them, and enables observation of the stored waveforms and other applications by combination with a display device, computer, etc. Is.

By sampling an analog input signal at high speed, AD-converting it into digital data, and storing and displaying the maximum peak amplitude (that is, the maximum value and the minimum value) of the digital data within an arbitrary time one after another, It is possible to extract so-called glitch extraction that extracts very high-speed noise that cannot be extracted by normal sampling, or envelope measurement and aliasing. Further, it is widely known that the peak value can be extracted by similarly extracting the maximum value or the minimum value.

A method of storing the maximum and the minimum of the waveform data is, for example, PAT. no. No. 4,271,486 and Japanese Utility Model Publication No. 63-110942.

US PAT. no. 4271486 is a basic method for detecting the maximum value and the minimum value, which is composed of a latch and a comparator, and compares sequentially input data with previously latched data, and when the data is large (or small), the data in the latch is compared. It is updated to new data and finally holds the maximum value (or minimum value).

In Japanese Utility Model Publication No. 63-110942, in order to further speed up the above method, a number of flip-flops corresponding to the number of values that digital data can take (256 for 8-bit digital data) are arranged, Each flip-flop is associated with each value that digital data can take as an address, and each time new data is received, the flip-flop corresponding to that data is set, and these flip-flops are set at any time. Among these, the maximum and minimum addresses of those already set are encoded and output to detect the maximum and minimum values.

[0008]

In the conventional method, it is necessary to increase the speed of the constituent devices when the sampling speed is increased, but using a high speed device results in a very expensive apparatus. In addition, as a high-speed sampling technique, a multi-phase memory is used for storing after high-speed AD conversion, and an AD converter is also used in multi-phase for higher-speed sampling. In order to detect the maximum value and the minimum value of the data of such a polyphase sampling system, the data which is polyphase in the conventional technique is multiplexed,
Since it has to be detected as one-phase ultra-high-speed data, it is difficult to realize and becomes a very expensive system.

[0009]

SUMMARY OF THE INVENTION In order to solve the above problems, the present invention simultaneously latches the data output in multiple phases at the same time for each adjacent phase data so that the data phases are aligned. After that, the larger data is sent to the maximum value detection circuit, the smaller data is sent to the minimum value detection circuit, and the maximum and minimum data of the set period are detected and stored in the memory in the subsequent stage of each phase. It was done.

[0010]

As a result, the multiphase data can be compared without being multiplexed into high-speed one-phase data, and the data can be compared in each phase, so that the comparison speed can be reduced for high-speed sampling. Therefore, higher speed sampling can be supported. Also, since the comparison with the neighboring phases is performed first in terms of timing, a maximum value and a minimum value are detected from each of the two phases, a total of two, so the number of memories connected to each phase and the maximum value,
The minimum number of data matches one-to-one, making the system easy to store.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. 1 to 4 are AD converters, 5 to 20 are latch circuits, 21
Is a maximum value / minimum value detection circuit, and 22 to 37 are memory circuits. The analog input signal from Vin is sequentially digitized by the AD converters 1 to 4 operating in four phases, and latched in the latches 5 to 20 connected in four phases after each AD converter. Since the latch has 16 phases as seen from the input Vin, the outputs of the latches 5 to 20 fall to 1/16 of the sampling frequency, which is 16 times the sampling cycle. However, the phases are shifted by the sampling period. Latch output is A-1,
The phase shifts A-2, A-3, ..., A-16 are input to the maximum value / minimum value detection circuit 21 in this order. The detection result of the maximum value and the minimum value is stored in the memories 22 to 37 in the subsequent stage.

Next, the details of the maximum / minimum value detection circuit 21 will be described with reference to FIG. The data input from A-1 and A-2 are simultaneously latched by the latches 101 and 102 in the maximum value / minimum value detection circuit 21, and the data whose phases are aligned are A-1a and A-1.
-2a is output. The comparator 121 compares the two input data, the larger data is output to S-1, and the smaller data is output to S-2. The maximum value detection circuit 131 detects the maximum value from the larger data that comes in sequence, outputs it to B-1, and stores it in the memory 22 in the subsequent stage. Similarly, the minimum value detection circuit 132 detects the minimum value from the smaller data sequentially and outputs it to B-2, and the memory 26 at the subsequent stage.
I will remember. The same applies to the following circuits in this figure.

Details of the comparison circuit shown in FIG. 2 will be described with reference to FIG. The comparator 155 compares the sampling data input from A-1a and A-2a and outputs the H level when the A input is smaller than the B input. According to the signal, the selectors 153 and 154 switch the inputs of A-1a and A-2a, and output the larger data to S-1 and the smaller data to S-2. The maximum value detection circuit 131 and the minimum value detection circuit 132 in the subsequent stage can use the method described in the related art.

FIG. 4 is a timing chart of these. As can be seen from the figure, in the present embodiment, the above-described maximum value / minimum value detection processing may be performed in a time 16 times the sampling period. Therefore, it is possible to support higher-speed sampling.

In this embodiment, the AD converter is used in four phases,
Furthermore, an example is shown in which four-phase memory is assigned to each AD converter to finally provide 16 phases, but the number of phases can be arranged in any manner.

Although not described in the present embodiment, in FIG.
-1 to B-1, A-5 to B-5 (same below)
It goes without saying that the normal waveform observation mode in which all the sampling data is stored is stored in the through path of.

[0017]

According to the present invention, the sampling frequency is
The maximum and minimum values can be detected when the speed becomes higher. As a function to detect the maximum and minimum values (peak detect) of digital oscilloscopes and waveform storage devices for multi-phase AD and multi-phase memory systems, which will be essential for high-speed sampling in the future, for observation while saving memory for high-speed single-shot signals. It is valid.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of a maximum value / minimum value detection circuit 21 of FIG.

3 is a detailed block diagram of a comparison circuit 121 in FIG.

FIG. 4 is a timing chart of an embodiment of the present invention.

[Explanation of symbols]

 1-4 AD converter 5-20 Latch 21 Maximum value minimum value detection circuit 22-37 Memory 101-116 Latch 121-128 Comparison circuit 131-146 odd number maximum value detection circuit 131-146 even number minimum value detection circuit 153 and 154 Selector 155 Comparator 156 NOT circuit

Claims (4)

[Claims] 1. In a digital data storage circuit in which digital data is demultiplexed and distributed in multiple phases and stored in a memory in each phase, the respective phases are sequentially sent in front of the memory of each phase. A digital data storage device, characterized in that the maximum and minimum values of incoming data are detected for a certain period of time and are stored in the memory at the subsequent stage. 2. The AD converter according to claim 1, further comprising: an AD converter for digitizing an input signal, a plurality of latch circuits for latching digital data digitized by the AD converter, and a plurality of latch circuits for sequentially latching the digital data. , Waveform storage device for demultiplexed polyphase digital data. 3. The waveform storage device according to claim 2,
Maximum value and minimum value of 1 for each of the two phases of polyphase digital data
A waveform storage device characterized by detecting data by data and storing a total of two data in a corresponding memory for two phases, and as a result, storing the maximum and minimum values of all phases. 4. The waveform storage device according to claim 2,
A waveform storage device comprising a plurality of AD converters, and a multi-phase AD converter circuit for sequentially digitizing common analog signals in an interleaved manner.