JPS5945293B2 - Series ↓-parallel signal converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high speed serial-to-parallel signal converter for converting a bit-serial type digital signal to a bit-parallel type digital signal.

Digital technology is making inroads into various technical fields that traditionally employed analog technology because of its simplicity and high accuracy in signal processing.

The most complex and large-scale digital equipment is, as is well known, the digital electronic computer, and efforts have been made to increase system speed in order to increase the efficiency of the machines.

Incidentally, a serial-parallel signal converter converts a serial signal into a parallel signal for the purpose of increasing data processing speed, but in digital systems such as those mentioned above, it is used to convert signal flows for design and maintenance purposes. A considerable number of these serial-to-parallel signal converters are used during testing.

The conversion frequency of a serial-to-parallel converter is limited by many factors, and even with currently available state-of-the-art technology, a single device cannot convert serial signals into parallel without errors at frequencies of 100 MHz (period Ions) or higher. It is extremely difficult to convert it into a signal.

This is because, in order for a flip-flop (hereinafter simply referred to as FF) to accurately respond to the instantaneous value of an input digital signal, the input signal requires a so-called setup time Ts and a hold time TH.

Here, Ts refers to the time that the input signal must be held in a stable state (high or low level) before the clock signal is applied to the FF in order for the FF to respond correctly to the input signal. .

Further, TH refers to the time period after application of a clock signal that this FF must continue to be held in the previous stable state in order to be reliably set to the new state.

On the other hand, various attempts have been made to develop high-speed series-to-parallel signal converters that operate at high frequencies of 500 MHz or higher.
One method is to use a shift register that continuously accumulates a serial digital input signal as a high-frequency clock pulse (hereinafter referred to as CP), and to transfer and set the output of the shift register to multiple launch circuits. .

However, this method has the following drawbacks.

That is, high-speed shift registers are very expensive, and
Due to the high power consumption, a considerable amount of heat is released, and furthermore,
This method requires a high frequency CP that is the same as the highest frequency of the input digital signal to be sampled, and also requires more parts than the conventional method, making the circuit configuration complicated.

An object of the present invention is to provide a high-speed serial-to-parallel signal converter that can operate up to a conversion frequency of IGHz or higher, has a clock frequency sufficiently lower than the conversion frequency, and has a simple circuit configuration.

To summarize the features of the present invention, a plurality of input (or sampling) FFs connected to a common signal input terminal, and
A plurality of output FFs that hold outputs from F are provided, and a delay line that provides a multiphase CP to each of these human-powered FFs is provided, and outputs from - or two or more input FFs at the last stage or the preceding stage are provided. An additional delay line is used to delay the output when it is transferred to the output FF.

As will be explained in detail later, the output FF that receives the input signal via the delay line will delay the transfer data, so the other output FF
It will receive data -clock cycles earlier than the data received by F.

The configuration and operation of embodiments of the present invention will be described below with reference to the accompanying drawings.

1 and 3 show embodiments of the present invention, and FIG. 2 is a time chart for explaining the operation of the embodiment of FIG. 1.

In FIG. 1, an input digital signal is input to a D (delay) type input (or sampling) FF 20 via a common input terminal 10.
It is added to the input end of A to 20D.

In this case, in order to equalize the propagation delays of input signals, although it is not clear from the diagram, it is assumed that the signals are applied through input lines of equal length.

On the other hand, CP from the CP input terminal 12 is directly transmitted to the first FF 20A without passing through the delay line, and is transmitted directly to the second FF 20B through the delay line D.
Two delay lines DLI are connected to the third FF20C via LI.
and DL2, and the fourth FF 20D is applied to the clock terminal C via three delay lines DLI, DL2 and DL3.

As will be clear from the description below with reference to FIG. 2, the delay lines DL1 and DL2.

DL3 generates multiphase tarok pulses, and preferably has electrically equal characteristics.

On the other hand, the above link signal is also output from the D-type output FF30a.
˜30d are applied directly to the clock end C, i.e. at the same time.

A delay line DL4 is connected between FFs 20D and 30d to provide a delay to the transferred data, as will be explained later with reference to FIG.

Parallel digital data is output from FFs 30d and 30a.

It is obtained from each output terminal 1, 2, 3.4 of 30b, 30c.

The operation of the embodiment shown in FIG. 1 will be explained based on the time chart shown in FIG.

FIG. 2A schematically shows single-channel 500MHz digital data applied to the data input ends of the input FFs 20A to 20D via the common signal input end 10, and FIG. 2B shows the following: A CP applied to the CP input terminal 12 is shown.

C, D, and E in FIG. 2 are the CPs at the output ends of the delay lines DLLDL2 and DL3, which are multiphase clock signal generation means,
Each is delayed by 2 ns.

In other words, the pulses B to E are input to the input FF20A on each front line.
Polyphase CP for triggering ~20D at precise time intervals
It consists of

FIGS. 2F to 2 schematically show the output states of the human-powered FFs 20A to 20D, respectively.

FIG. 2J shows the output at the output end of delay line DL4, which has the same characteristics as delay lines DL1-DL3.

Finally, in FIG. 2, -N indicates the output signals of the output FFs 30a to 30d from the output terminals 2, 3, and 4°1, respectively.

Now, at time t1, CP(B) has FF20A at its leading edge.
is triggered, and this FF 20A samples the input data signal A1.

Of course, at this time, input data A1 is Ts and T of FF20A.
It shall satisfy H standard.

At the same time, each of the output FFs 30a to 30d sets the contents (or outputs) of the corresponding input FFs 20A to 20D at the leading edge of the CP(E%l).

What must be noted here is that the FF at time t1
The content of 20A is not 80, but the previous old data A.

It is. This is due to the nature of FFs, which is that they cannot respond immediately to input signals.

Furthermore, because of Ts and TH mentioned above, even if new data A1 is input at this point, the FF 30a cannot respond to it, but responds to the data before CP is applied.

Therefore, the digital signals from output terminals 2, 3, 4.1
Data are Ao, Bo, and co, respectively.

It becomes D-1.

This parallel data is equal to one cycle of CP(B) (
tl ts).

At time t2 when CP(C') is applied to the FF 20B, the FF 20B samples the second data B1.

Similarly, FF20C receives third data C1 at time t3,
FF20D samples the fourth data D1 at time t4.

By the way, as mentioned earlier, the FFs 30a to 30d do not receive the leading edge of CP([3)7) until time t5, so they are not triggered and their contents (or outputs) do not change.

Now, at time t5 when the next leading edge of CP(Q arrives), FF20
A is triggered to sample the next data A2, and at the same time, FFs 30a-30d are also triggered by the leading edge of CP(B) to receive the contents of corresponding FFs 20A-20D, respectively.

If there is no delay line DL4, the last stage FF, 3
0d must receive data D1 sampled at time t4.

However, this data D1 is applied to the data input of FF 30d in an extremely shorter time T than 2 ns due to the operation delay of FF 20D and the propagation delay of the signal path between input and output FFs, so FF 30d cannot be completely set.

In other words, the above-mentioned Ts becomes a big problem in data reception by the FF 30d.

Therefore, the upper limit of the operating frequency of the entire serial-to-parallel signal converter is limited depending on whether data reception by the FF 30d is performed accurately.

The present invention uses an additional delay line DL4 to solve this problem.

That is, as shown in FIG. 2J, the delay line DL4 is connected to the FF2
Since a delay of, for example, 2 ns is given to the output data from 0D, at time t when the output FF performs sampling, as shown in waveform J, the FF 30d receives not the new data D1 but the previous data D.

is being transferred. In other words, at time t5, the output FF
Parallel output data beams sampled by 30a-30d.

g Al y Bl s C1. This output data is held as it is until time t6 when the next leading edge of CP(B) arrives.

The above operation is performed for the following time 1. -16 and so on, and so on.

Note that the parallel output data at time t6 are Dl, A2. B2
．． It is clear that it is C2.

In other words, it should be noted that the last FF 30d outputs data that arrived temporally earlier than data that reached the other FFs 30a to 30c.

Therefore, the FFs 30a to 30c naturally output data subsequent to the output data of the FF 30a.

Therefore, the output terminals of each of the output FFs 30a to 30d in FIG. 1 are numbered 2.3°4.1.

Adjacent parallel output data (D-1, Ao, Bo, co)
, (Do, A1.B1°C+) t (DI, A2
s B2 s C2) , etc., the interval is CP
CB) (8 ns (125MHz) in this example)
), which is the input signal period 2ns (500
Note that it is sufficiently smaller (one-fourth) than MHz).

This means that relatively slow devices such as memory can operate accurately and stably to store data.

Therefore, the serial-to-parallel signal converter of this embodiment samples a digital input signal, stores it in an integrated circuit memory, etc., and later uses it in a logic analyzer or measurement device for analyzing the signal on the screen of a cathode ray tube. It is suitable for

As is clear from FIG. 2, it is not FF30d that is likely to cause problems in operation in this embodiment, but FF20C to 4n.
The FF 30c receives data sampled s before.

However, even an FF with a relatively slow response speed does not require a long Ts of 4 ns, so it is possible to reliably serial-parallel convert an input signal of 500 MHz or more frequency with a fairly low frequency CP without any problem. It is possible.

In the embodiment shown in FIG. 1, when the input signal frequency is set to IGHz, the delay time of each of the delay lines DL1 to DL3 is halved, that is, Ins, and the frequency of the clock pulse is doubled, that is,
Must be 250MHz.

In this case, the third output FF 30c poses an operational problem.

This is because the corresponding input FF20C is the output FF30c.
This is because the input data is sampled 2 ns before the data is received.

This problem is caused by a new 2n between FF 20C and 30c.
This can be solved by inserting a delay line with a delay time of s.

In that case, the third and fourth output FFs 30c and 30
d will receive the data sampled in the previous clock cycle, and the temporal order of the parallel data signals is:
FF30c, 30d.

The order is the output of 30a and 30b.

In the embodiment shown in FIG. 1, there are four FFs in each of the input and output stages.
However, the present invention is not limited to this, and the present invention is not limited to this.
F can be used to convert the same serial input data into parallel data at the same or lower clock frequency than the embodiment.

In this case, the delay time td in the delay line must be changed depending on the clock frequency used and the number of input FFs so as to satisfy the following equation.

td=Tc/N +++++++ (i) Here, N: number of input FFs Tc: period of CP By the way, the maximum frequency of the input signal is determined by the reciprocal of the delay time.

Note that the delay time of the delay line D L' 4 does not necessarily have to be equal to the delay times of the other delay lines, and as is clear from FIG. 2, it may have a considerably large value.

Now, considering the case where the clock frequency is 125 MHz and the input signal frequency is IGHz, it can be seen from equation (1) that eight input FFs are required.

Therefore, in the embodiment of FIG. 1, the input stage has four inputs F
F20E, 20F, 20G, 20H, and the same four output FF30e s 30 f s 30g in the output stage.

30h and apply the multiphase CP to the input FFs 20A to 20H via delay lines each having a delay time of Ins.

In this case, in order to avoid the problem caused by Ts described above, delay lines are inserted between the input and output flip-flops of the last two or more stages.

In this way, a parallel data output consisting of 8 bits can be obtained. Below, when multiple input/output FFs are generally used, the number of delay lines to be inserted between the input/output FFs and the number of delay lines for each delay line will be explained. The required delay time will be explained based on the general principle diagram of the present invention shown in FIG.

In FIG. 3, N input FFs 20(1) to 20CN) are connected to (N-1) delay lines DLI, each having a delay time of K (ns).
It is triggered by the polyphase CP created by DL(N-1).

On the other hand, N output FFs 30(1) to 30(N) are provided as shown in the figure.

Now, K(M+1)≦T p 1TW 1T S =・
If (2) holds true, it is necessary to insert a delay line between the input and output FFs of the (M+1)th stage (M=0, 1, 2, 3, . . . ) from the last stage.

In the above equation: Delay time of each of the delay lines DLI to DL(N-1) TP: Time until the FF generates an output from the leading edge of CP Tw: Data propagation delay time between input and output FF By the way,
As mentioned above, in order to operate the FF reliably, T
TH is required in addition to s.

Therefore, in order to reliably set the output FF of the (M+1)th stage from the last stage, the delay time on the left side of equation (2) must be further delayed by the hold time TH.

In other words, between the (M+1)th input/output FFs 20(N-M) and 30(NM), there are K(M+1)+TH...
... It is necessary to insert a delay line with the delay time of (3).

Of course, there is no problem in providing a delay time longer than this, but in order to shorten the length of the delay line, it is preferable to use a delay line having the delay time of formula (3).

In the embodiment shown in FIG. 1, the delay time of the delay line DL4 is 2n.
The reason why TH is not taken into consideration in s is that some FFs may operate normally even with such a delay time.

The delay time in equation (3) generally indicates the time required to operate the serial-parallel signal converter reliably, without taking into account the specific characteristics of the FF or its usage. .

As explained above, according to the present invention, - or more delay lines are inserted between the input and output FFs, and from the input FF to the output FF.
By delaying the signal transferred to F, it is possible to reliably convert a 10 Hz or higher serial human digital signal into a parallel digital signal at a relatively slow clock frequency.

[Brief explanation of drawings]

1 and 3 are embodiments according to the present invention, and FIG. 2 is a time chart for explaining the operation of the embodiment of FIG. 1. 10... Common input terminal, 1, 2. ..., N-
1゜N...Output terminal, 20A to 20D, 3
0a to 3030d...Flip-flop,
DL1 to DL(N-1)...Delay line, 20(1
)~20(N), 30(1)~30(N)...
-Flip flop.

Claims (1)

[Claims] 1. A plurality of first flip-flops each having an input terminal connected to a common signal input terminal to which a serial digital signal is applied;
a plurality of second flip-flops each having an input terminal connected to an output terminal of the first flip-flop, and a clock signal being simultaneously applied to each clock signal terminal of the second flip-flop; a clock signal generating means for applying a multiphase clock signal to each clock signal terminal of the flip-flop, and a clock signal generating means formed between the output terminal of the first flip-flop and each of the input terminals of the plurality of 27th flip-flops. A signal delay means is provided in the signal propagation path of the first flip-flop to which a clock pulse is applied at least at the end of the plurality of signal propagation paths;
A serial-to-parallel signal converter that outputs parallel digital signals from each output of a flop. 2. According to claim 1, the lengths of the plurality of signal propagation paths formed between the common signal input terminal and the input terminals of the plurality of first flip-flops are made equal. Series-to-parallel signal converter. 3. The serial-parallel clock signal according to claim 1 or 2, wherein the clock signal generating means has a plurality of delay lines, and the multiphase tarlock signal is generated by the plurality of delay lines. signal converter.