JPS6141228A - Serial-to-parallel converter - Google Patents

Abstract

PURPOSE:To decrease the number of bit counter circuits down to just one and to simplify the structure of a serial/parallel converter, by using a delay circuit which can set optionally the number of delay stages that delays the serial reception signals, a serial/parallel converting circuit which converts the delayed serial reception signals into parallel signals and a bit counter circuit which counts the bits of the serial reception signals. CONSTITUTION:The number of delay stages of a delay circuit 3 is controlled by the set contents of a setting register 4. The setting information is transferred from a processor 1 via a bus and set by a load control signal LD. The reception signal delayed by the circuit 3 is applied to a shift register 2 and shifted successively by a clock signal CLK. The timing for serial/parallel conversion is produced when the processor 1 reads the contents of a bit counter circuit 7. This circuit 7 is reset by the detection signal SYN of a frame synchronizing signal F of a transmission signal and counts clock signals CLK. The circuit 7 also serves as a parallel/serial converter at a transmission part (not shown in figure).

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides serial reception signals in a time-division direction control transmission system (ping-pong transmission system) so that the reception timing is constant with respect to the transmission timing. The present invention relates to a serial-to-parallel converter that converts a serial received signal into a parallel signal by setting the number of delay stages for delaying the signal.

[Conventional technology]

In the time-division direction control transmission method, transmission and reception are alternately switched at a fixed period between devices such as terminals connected by a two-wire digital line, and mutual communication is carried out similarly to the full-duplex communication method. This is a transmission method that repeatedly transmits after receiving, so it is also called the bing-bong transmission method. In this case, since it is transmitted as a serial signal, the receiving section converts it into a parallel signal and processes it.

For example, if (a) in Figure 3 is the master station, (bl is the transmitted and received signal of the slave station, and (e) is the transmission frame format, then when the master station sends out signal A, the slave station will have a transmission delay time τ It will later be received as signal a.The slave station determines the transmission timing of signal B based on this received signal a.The master station will receive this signal B as a signal after the transmission delay time τ. become.

As mentioned above, within one burst period T, the master station transmits signal A and receives the signal from the slave station, and in the next burst period it transmits signal C, It will receive the signal d from the slave station. Further, the slave station receives the signal C and transmits the signal.

At the beginning of the transmission signal, as shown in (C), a frame synchronization signal F is added, and for example, 8-bit data DI is added.
, D2. ca, . . . are transmitted in series, and a balance bit etc. is added at the end. The transmitting section converts the 8-bit parallel transmission data into a serial signal and transmits it, and the receiving section converts the signal received as a serial signal into 8-bit parallel receiving data. be. Note that if a 16-bit processor or the like is used, the received signal will be serially converted every 16 bits.

[Problem that the invention seeks to solve]

Generally, the distances between the master station and the plurality of slave stations are different, and therefore the transmission delay time τ differs depending on the slave stations. Therefore, the master station transmits signal A in synchronization with each burst cycle.

Even if C is transmitted, the reception timing of signals S and D differs depending on the slave station or the transmission route. When converting a parallel signal into a serial signal and transmitting it, and receiving a serial signal and converting it into a parallel signal, the conversion process is performed in units of, for example, 8 bits, but as mentioned above, the master station In this case, the transmission timing and the reception timing are not synchronized, so it is necessary to provide a bit counting circuit for parallel-serial conversion and a bit counting circuit for serial-parallel conversion, respectively.

SUMMARY OF THE INVENTION An object of the present invention is to perform serial-to-parallel conversion of a received signal in a time-division direction control transmission system by requiring only one bit counting circuit.

[Means for solving problems]

The serial-to-parallel conversion device of the present invention includes: a delay circuit that can arbitrarily set the number of delay stages for delaying a serial received signal; a serial-to-parallel conversion circuit that converts the serial received signal delayed by the delay circuit into a parallel signal; It is equipped with a bit counting circuit that counts the number of bits of a serially received signal.

[Effect]

The number of delay stages of the delay circuit is set to delay the received signal, thereby making the conversion timing in the serial-to-parallel conversion circuit have a certain relationship. This circuit can also be used as a bit counting circuit.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, where 1 is a processor (MPU) and 2 is a shift register (SREG).
, 3 is a delay circuit (DEL), 4 is a setting register (R
EG), 5 is a bit buffer register (BBF),
6.8 is a bus driver, 7 is a bit counting circuit (BCNT)
). The received signal St is sent to the pit buffer register 5.
is written by the clock signal CKI extracted from this received signal Si, and the clock signal CL in the device is written.
K is read out and applied to the delay circuit 3.

The number of delay stages of the delay circuit 3 is controlled by the setting contents of the setting register 4, and setting information is transferred from the processor 1 via the bus and set by the load control signal LD. The received signal delayed by the delay circuit 3 is applied to the shift register 2 and clock signal CLK
are sequentially shifted by The contents of this shift register 2 are transferred in parallel to the processor 1 via the bus driver 6, thereby performing serial-to-parallel conversion.

The timing for this serial-parallel conversion is created by the processor 1 reading the contents of the bit counting circuit 7, and this bit counting circuit 7 is reset by the detection signal SYN of the frame synchronization signal F of the transmission signal. It counts the clock signal CLK, and is also used for parallel-to-serial conversion in a transmitter (not shown).

The processor l reads the contents of the shift register 2 by outputting the enable signal EN1 at the cycle of the clock signal CLK until it identifies the frame synchronization signal F of the received signal St. When this frame synchronization signal F is identified, the count contents of the bit counter circuit 7 are read by applying the enable signal EN2 to the bus driver 8, and the number of bits shifted is calculated.For example, , if there is a 3-bit shift, add 3-bit delay stage number setting data to the setting register 4 via the bus and set it using the load control signal LD.The delay circuit 3 follows the set contents of the setting register 4. The received signal is delayed by the number of delay stages and added to the shift register 2, and the timing for reading out the contents of the shift register 2 in parallel is determined by the count contents of the clock signal CLK in the bit counting circuit 7.

FIG. 2 shows a delay circuit 3 according to an embodiment of the present invention, with FF1 to
FF5 is a flip-flop, and SEL is a selector.

Since the clock signal CLK is applied to the clock terminal CK of the flip-flops FFI to FF5, and the reception signal Si is applied to the data terminal of the first stage flip-flop FFI, the Q terminal output of each flip-flop 1FFI to FF5 is the clock signal CLK. The received signal Si delayed according to
The input reception signal Si and the Q terminal output signal of each stage are applied to the selector SEL.

It goes without saying that the number of stages of the flip-flops FFI to FF5 may be eight if the parallel signal has an 8-bit configuration, and the setting register 4 may be configured to set setting data corresponding to the number of delay stages. As mentioned above, if there is a difference of 3 bits, depending on the set contents of setting register 4,
The output from the flip-flop FF3Q terminal is selected and output by the selector SEL.

Since the received signal St delayed by the delay circuit 3 is synchronized with the transmission timing, it is converted into a parallel signal by the shift register 2 according to the count contents of the bit counting circuit 7.

〔Effect of the invention〕

As explained above, the present invention provides a delay circuit 3 for delaying a serially received signal, a serial-to-parallel conversion circuit including a shift register 2, etc., and a bit counting system in a time division direction control transmission system (ping-pong transmission system). By setting the number of delay stages of the delay circuit 3, the reception timing can be kept constant with respect to the transmission timing, so when converting a parallel signal into a serial signal and transmitting it. It is possible to convert the received signal in parallel by sharing the bit counting circuit with the bit counting circuit of the above, which has the advantage of simplifying the configuration.

[Brief Description of the Drawings] Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 1 is a processor (MPU), 2 is a shift register (SREG)
, 3 is the delay circuit (DF, L), 4 is the setting register (
REG), 5 is pit buffer register (BBF)
, 6.8 is a bus driver, 7 is a bit counting circuit (BCN
T), FF1 to FF5 are flip-flops, and SEL is a selector. of

Claims (1)

[Claims] A serial-to-parallel conversion device for converting a serial received signal into a parallel signal in a time division direction control transmission system includes a delay circuit that can arbitrarily set the number of delay stages for delaying the serial received signal, and a delay circuit that delays the serial received signal by the delay circuit. A serial-to-parallel conversion device comprising: a serial-to-parallel conversion circuit for converting a serially received signal into a parallel signal; and a bit counting circuit for counting the number of bits of the serially received signal.