JP2540770B2 - Data communication circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a data communication circuit,
In particular, the present invention relates to a data communication circuit for accessing a memory.

[0002]

2. Description of the Related Art Conventionally, a data communication circuit of this type performs only transfer rate conversion by using a FIFO using a dual port RAM or the like capable of simultaneously writing and reading asynchronously and a synchronous single port memory. For example,
Japanese Patent Application Laid-Open No. 01-316820 describes a technique for converting the data transfer rate using a synchronous single port memory.

[0003]

In this conventional data communication circuit, the data input / output order cannot be changed even though the transfer rate can be converted. Further, there is a problem that the number of input / output lines is only one line and a plurality of lines cannot be handled.

[0004]

A data communication circuit according to the present invention includes a plurality of transmission and reception address counters capable of setting an arbitrary address value, and inputs and outputs data to and from a memory corresponding to each of the counters. In order to do so, a serial / parallel converter that performs serial / parallel conversion of data,
A selector that switches them, a parallel-serial converter that performs the opposite, a disist that switches them,
It has a CPU and a timing circuit for controlling all of the above.

[0005]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. The apparatus shown in FIG. 1 has a configuration in which lines of two lines can be connected to each of the receiving side and the transmitting side. The one side on the receiving side operates with the clock for the one side on the receiving side from the timing circuit 107, and the two side on the receiving side operates on the timing circuit 107.
From the timing circuit 107, the transmission side 1 side operates from the timing circuit 107 for the transmission side 1 side clock, and the transmission side 2 side operates from the timing circuit 107 transmission side. It operates on the clock for two sides, and each operates asynchronously. On the receiving side, a serial-parallel converter (SP) 109 for converting received serial data into parallel data, and a buffer for connecting parallel data from SP or data from the CPU to the data bus of RAM (BUF) 105, and a detector 104 for detecting a reception header code and a reception tail code of the data. In order to store and edit the data, the RAM 106 in which the data output from the BUF is stored through the data bus, the counter 101 for addressing the RAM, and the counter 101-1 or 01.
, A selector 103 for selecting which of the two to use,
Give a pulse of which to select with that selector,
Timing circuit 10 for giving transmission / reception timing to each part
7. It has a CPU 102 for editing RAM data. This timing circuit operates as shown in FIG. The transmission side includes a parallel-serial conversion device (PS) 108 that converts parallel data on the data bus into serial data.

Next, the operation of FIG. 1 will be described. 3 and 4 are waveform charts for explaining the operation of FIG. The serial data received from the line on the receiving side is S
-Converted to parallel data in P109-1. The parallel data is detected by the detector 1 which is composed of, for example, a comparator.
When the received header code is detected in 04-1 (1 in FIG.
-1 to 108), a header detection pulse is output to the timing circuit 107, and the timing circuit outputs a set pulse to the CPU 102 and the reception counter 101-1. CPU
When receiving the set pulse, sets the start address 0 to the reception counter. When one byte of data is received, the timing circuit 10 issues a write request to the RAM 106.
7, the timing circuit sends out a RAM write pulse from the timing circuit when the selector 103 selects the receiving address counter 101-1 and turns on the buffer 105-1 so that 1 byte on the 1st side of the received data. Write (1-9 to 1-16) to RAM. Immediately thereafter, the address counter of 101-1 is incremented by 1 and the address is updated to 1. The above operation is repeated until the data ends, and when the tail of the received data is detected by the detector 104-1, the writing is ended. The data written in the RAM can be edited into any data by directly accessing the CPU, and the data edited into the transmission data can be edited as follows.
It is transferred to the transmission area of the RAM. The same applies to the two receiving sides. On the transmission side, the transmission timing is set so that the 1st side and the 2nd side are cyclically selected, so that the timing circuit 107 sets the parallel-serial converters (hereinafter P-S) 108-1 and 108-2. Selected regularly. When sending to the 1 side of the sending side, first,
The transmission counter 100-1 is selected by the signal from the CPU, the start address of the transmission data is set in the transmission counter, the CPU instructs the timing circuit to start transmission, and the selector 103 selects the transmission address counter 100-1. Sometimes the timing circuit sends a load pulse to P-S108-1 to load the first byte of transmission data. One byte of data is sent from P-S108-1 to the sending side, one bit at a time, and when the timing circuit recognizes the sending of 8 bits, a load pulse is issued again. The number of bytes is counted each time one byte is sent and repeatedly sent. When the number of bytes designated by the CPU is counted, the transmission ends. In the series of transmission and reception, the switching of the selector 103, the buffer 105, and the P-S 108 on the transmission side is asynchronous with the transmission data and the reception data as shown in FIG. 4, but is synchronized at a speed sufficiently faster than the line speed. Since the transmission is performed, the line speeds of the receiving side and the transmitting side are arbitrary, and transmission / reception can be performed simultaneously.

This system is the same when the number of transmissions is expanded to N and the number of receptions is expanded to M, and a block diagram thereof is shown in FIG.

[0009]

As described above, since the data communication circuit according to the present invention has the same number of address counters for reception as the number of lines, each line can receive data independently. Further, since the transmission and reception data areas are separately provided in the RAM, the CPU can perform data editing such as changing the data transmission order. Further, the transmission side also has address counters for transmission corresponding to the number of lines, so that any data can be sent to any line. Further, the transmission / reception line speed has an effect that an arbitrary speed can be set for each line.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram in which FIG. 1 is generalized.

3 is a waveform chart 1 for explaining the operation of FIG.

FIG. 4 is a waveform diagram 2 for explaining the operation of FIG.

[Explanation of symbols]

 100 Transmission Address Counter 101 Reception Address Counter 102 CPU 103 Selector 104 Detector 105 Buffer 106 RAM 107 Timing Circuit 108 Parallel / Serial Conversion Device 109 Serial / Parallel Conversion Device

Claims (1)

(57) [Claims] 1. A plurality of transmission and reception address counters capable of setting arbitrary address values, and serial data corresponding to each of these counters for inputting / outputting data to / from a memory. A data communication circuit having a parallel converter, a selector for switching between them, a parallel / serial converter for performing the reverse operation, a disist for switching between them, and a CPU and timing circuit for controlling all of the above.