JP3094714B2 - Noise removal filter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION This invention relates to a noise reduction filter to be used on the occasion to the partial discharge measuring high voltage equipment, a power cable (line).

[0002]

2. Description of the Related Art Prior art related to the present invention includes:
There are two cases by the present inventor: Japanese Patent Application No. 4-191405 and Japanese Patent Application No. 4-250494. The former is a discrimination method in which the regularity of the time series characteristics of the partial discharge pulse is quantified using indexes such as a group pulse rate and a pulse rate, and a detection signal is discriminated as a partial discharge or a noise. On the other hand, the latter uses the regularity (time-to-pulse characteristics) of the time series characteristics of the partial discharge pulse to identify whether each detection pulse is a partial discharge pulse or a noise pulse, and uses software to determine This is a method of removing a noise pulse using the algorithm of (1).

[0003]

However, in the former prior art, partial discharge and noise are distinguished by using the statistical properties of detected pulses (whether or not a partial discharge is included in the detection signal. ), But it was not possible to discriminate whether each pulse was a partial discharge pulse or a noise pulse.

Further, in the latter prior art, each pulse is discriminated as a partial discharge pulse or a noise pulse using the statistical properties of the detected pulse. As this means, since all the detection signals during the measurement time are once taken into a computer, and then individual pulses are identified by software on the computer, noise cannot be identified and removed in real time.

It is an object of the present invention to provide a simple and effective noise removal filter capable of removing a noise pulse in real time in a partial discharge measurement of a power cable line.

[0006]

SUMMARY OF THE INVENTION This invention relates to the use on the occasion to the partial discharge measuring high voltage equipment, power cables (lines)
A noise reduction filter to be, the division voltage waveform Zeroku
Outputs a synchronization timing signal synchronized with the loss timing
Compares the circuit that, the A / D converter and a memory for storing the detection signal waveform, and number of pulses currently measurement period trying to measurement, the number of pulses during the measurement period at the time of previous measurement, a microcomputer difference between the current number of measuring pulses and past measurement number of pulses determines the partial discharge pulse conditions equal to or less than a predetermined number, the partial discharge when the pulse condition is satisfied only in synchronism with the zero-cross timing of the division voltage waveform circuit which outputs a digital waveform stored in the memory Te
And D / A for converting this digital waveform into an analog waveform.
And a converter.

[0007]

By using the above-described noise elimination filter of the present invention, a high
By measuring the partial discharge of voltage equipment and power cables
Thus, the noise pulse can be efficiently removed in real time from the detection signal in which the partial discharge pulse and the noise pulse coexist, and the accuracy of the partial discharge measurement can be improved.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a noise removal filter according to one embodiment. The applied voltage signal input from the applied voltage signal input terminal 1 is converted into a signal of the microcomputer input level by the waveform shaping circuit 2 and input to the microcomputer 3 and the memory control circuit 4. The detection signal input from the filter input terminal 5 is
The signal is input to the waveform shaping circuit 6 and the input amplifier 7. The signal input to the waveform shaping circuit 6 is converted into a signal of a microcomputer input level and output to the microcomputer 3.

The signal input to the input amplifier 7 is amplified to an appropriate input level of an analog / digital (A / D) converter and output to the A / D converter 8. The A / D converter 8 converts an output signal of the input amplifier 7 into a digital signal in synchronization with a clock signal input from the memory control circuit 4. The signal converted into the digital signal is output to the switch 9. The switch 9 is a control signal from the memory control circuit 4 and outputs a signal from the A / D converter 8 to the memory 10 when writing to the memory and outputs a signal from the memory 10 to the D / A converter 11 when reading from the memory. To control.

The D / A converter 11 converts a digital signal read from the memory 10 into an analog signal in synchronization with a clock signal input from the memory control circuit 4. The signal converted into the analog signal is output to the output amplifier 12. The output amplifier 12 amplifies the signal output from the filter output terminal 14 so as to have the same level as that at the time of input, and outputs the amplified signal to the switch 13. The switch 13 switches the signal of the output amplifier 12 and the ground potential according to a control signal from the memory control circuit 4 and outputs the signal to the filter output terminal 14.

The microcomputer 3 sets a counting period based on the applied voltage signal, and counts the number of detection signals input during that period. The count value is compared with a previous count value or a plurality of past count values. As for the count value, if the difference between the previous count value or a plurality of past count values is equal to or less than a predetermined ratio, or is equal to or less than a prescribed value, the comparison result is determined to be the same. Information on the counting period and the comparison result is output to the memory control circuit 4.

The memory control circuit 4 controls the microcomputer 10 to write a detection signal for a period corresponding to the counting period to the memory 10 and to read the detection signal from the memory 10. Therefore, A
The conversion timing of the / D converter 8 and the switching of the switch 9, writing and reading switching of the memory 10, address setting, and the timing of the D / A converter 11 are controlled.

These timings are determined, for example, by the switch 9
Is switched to the A / D converter 8 side, the address of the memory 10 is set, A / D conversion is performed, writing is performed with the memory 10 in a write state, and the switch 9 is set to the D / A converter 1.
1, the address is set in the memory 10, reading is performed, and D / A conversion is performed. Also,
The memory control circuit 4 controls the switch 13 according to the comparison status from the microcomputer 3. That is, the switch 13 is switched to the output amplifier 12 side when the comparison result is coincident, and to the ground potential side when the comparison result is not coincident.

Next, a second embodiment will be described based on FIG. 2 of a block diagram showing a noise removal filter. In this example, the position of the switch 13 is different from that of the first embodiment shown in FIG. That is, in the case of the first embodiment, the output of the signal is blocked by switching the analog signal of the output amplifier 12 to the ground potential by the switch 13. On the other hand, in this example, the digital data of the D / A converter 11 is switched from the signal of the memory 10 to 0 data (ground potential). Therefore, the control of the memory control circuit 4 is different from that of the first embodiment.

In FIG. 2, a memory control circuit 4 controls the microcomputer 3 to write a detection signal for a period corresponding to the counting period to the memory 10 and to read the detection signal from the memory 10.
Therefore, the conversion timing of the A / D converter 8 and the switching of the switch 9, the writing / reading switching of the memory 10, the address setting, the switching of the switch 13, and the conversion timing of the D / A converter 11 are controlled. At these timings, for example, the switch 9 is switched to the A / D converter 8 side, the address of the memory 10 is set, the A / D conversion is performed, the memory 10 is written to the write state, and the switch 9 is set to the D / D converter. It can be realized by switching to the A converter 11 side, switching the switch 13 to the memory 10 side, setting the address of the memory 10, reading out, and performing D / A conversion. Further, the memory control circuit 4 controls the switch 13 according to the comparison status from the microcomputer 3. When the comparison result indicates a match, the switch 13 is switched to the memory 10 side. When the comparison results do not match, the switch 13 is switched to the 0 data (ground potential) side.

Next, a third embodiment will be described with reference to FIG. 3 of a block diagram showing a noise removal filter. In this example, a memory 15 is newly provided, and the number of memories 10 is different from that of the first embodiment. Therefore, the switch 16
Is required. In the case of the first embodiment, writing and reading to and from the memory 10 are alternately performed, thereby realizing a single memory. On the other hand, in this embodiment, two memories are used alternately for each counting period.

In FIG. 3, a memory control circuit 4 controls the writing and reading of a detection signal for a period corresponding to the counting period of the microcomputer 3 to the memory 10 or the memory 15. For this reason, the conversion timing of the A / D converter 8 and the switching of the switches 9 and 16, the writing and reading switching of the memories 10 and 15, the address setting, the switching of the switch 13, and the conversion timing of the D / A converter 11 are changed. Can control.

These timings are determined, for example, by switching the switch 9 to the A / D converter 8 for a certain period,
Is set, the A / D conversion is performed, the memory 10 is written, and writing is performed.
6 is switched to the D / A converter 11 side, the address of the memory 15 is set, reading is performed, and D / A conversion is performed. In the next period, the switch 9 is switched to the D / A converter 11 and the signal is read from the memory 10. At the same time, the switch 16 is switched to the A / D converter 8 and the signal is written to the memory 15. be able to. In the case of this embodiment, although the number of memories increases, writing and reading are switched on a count period basis, so that memory control is simplified.

FIG. 4 is a block diagram showing a case where the noise elimination filter of the present invention is applied to the measurement of partial discharge of a power cable line. That is, the power application transformer 21 is connected to the power cable 22 and the power cable line including the simulated defect, and a voltage is applied to the power cable line. In the present embodiment, the partial discharge signal generated from the connection portion 23 having the simulated defect was detected by the detection impedance 25 via the detection electrode 24 attached outside the connection portion 23. In the case of the noise elimination filter of the present invention, the signal detection method is not particularly limited. The detected signal is amplified by the amplifier 26 and input to the noise elimination filter 27 of the present invention. Then, it is output to the monitor 29 and displayed. In this example, the voltage application phase information is obtained by converting the voltage generated in the tertiary winding of the power application transformer 21 via the lead wire 28 into the noise removal filter 27.
Gave to.

FIG. 5 (C) shows the results obtained by the above measurement method.
Shown in That is, the imposed voltage phase shown in FIG. 5A is input to the noise elimination filter 27 via the lead wire 28, and the input pulse train shown in FIG. The operation in the case where the operation is performed will be described. Here, an example is shown in which the noise removal filter of the first embodiment shown in FIG. 1 is used, the number of pulses is compared with the number of pulses one half cycle before, and an output pulse is output only when the number matches.

The noise removal filter 27 has a half cycle of 1A.
Is stored in a part of the memory, and the number of pulses in the half cycle 1A is compared with the number of pulses before the half cycle (0 in this case because there is no measured value). I do.

The input waveform of the half cycle 1B is stored in the memory 10
And the number of pulses in the half cycle 1B = 1 and the number of pulses in the half cycle before (half cycle 1A) = 1
Are compared, and in this case, it is determined that they match.

Since the result of the discrimination in the half cycle 1A is inconsistent, the pulse during the half cycle 1A is judged to be noise, and the output of the noise removal filter 27 during the half cycle 2A is set to the ground potential by the switch 13. . The input waveform of the half cycle 2A is stored in a part of the memory 10, and the number of pulses in the half cycle 2A is compared with the number of pulses in the half cycle before (half cycle 1B) = 1. I do.

Since the results of the determination in the half cycle 1B are the same, the pulse during the half cycle 1B is determined to be a partial discharge, and is stored in the memory 10 in synchronization with the potential application phase 2B during the half cycle 2B. The input waveform of the half cycle 1B is output. Therefore, in this case, the noise removal filter 27
, The pulse is output with a delay of one half cycle. In parallel with this, the input waveform of the half cycle 2B is stored in a part of the memory 10, and the number of pulses in the half cycle 2B = 1
Is compared with the pulse number = 1 before the half cycle (half cycle 2A), and in this case, it is determined that they match.

In the same manner, on / off control of the output is performed every half cycle to remove the pulse. That is, the pulse removed from the input pulse train in FIG.
Pulse 1A, pulse 4B (2 pulses), pulse 5B, pulse 7B (3 pulses), pulse 8A (2 pulses), pulse 8B (1 pulse), pulse 9A (2 pulses), pulse 9B (3 pulses), pulse 10A (1 pulse), pulse 10B (2 pulses), and pulse 11B (3 pulses).

As another embodiment, as the partial discharge pulse conditions, the current measured pulse number N ₁ and the past measured pulse number N
₂ ratio N ₁ / N ₂ is given range (eg, 0.9.
1) may be used. This can be dealt with by improving the software of the microcomputer unit that compares the number of pulses.

[0027]

As described above, according to the noise removal filter of the present invention, noise pulses can be efficiently removed in real time from a detection signal in which a partial discharge pulse and a noise pulse are mixed. This is because the detection signal pulse every half cycle (one cycle) is converted from analog to digital, then stored once, and the noise is determined in real time.
In the case of a noise pulse, removal is performed, and in the case of a partial discharge pulse, analog / digital conversion is performed in accordance with the imposed voltage phase, and the output is output.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a noise removal filter according to a first embodiment of the present invention;

FIG. 2 is a block diagram showing a configuration of a noise removal filter according to a second embodiment of the present invention;

FIG. 3 is a block diagram showing a configuration of a noise removal filter according to a third embodiment of the present invention;

FIG. 4 is a block diagram when a noise removal filter is used for measuring partial discharge of a power cable line;

5 (A), (B) and (C) are waveform diagrams showing the results obtained in FIG. 4, (A) is the imposed voltage phase, (B)
Is an input pulse train, and (C) is an output pulse.

[Explanation of symbols]

 Reference Signs List 1 voltage signal input terminal 2, 6 waveform shaping circuit 3 microcomputer 4 memory control circuit 5 filter input terminal 7 input amplifier 8 A / D converter 9, 13, 16 switch 10, 15 memory 11 D / A converter 12 output amplifier 14 Filter Output Terminal 21 Power Transfer Transformer 22 Power Cable 23 Connection 24 Detection Electrode 25 Detection Impedance 26 Amplifier 27 Noise Elimination Filter 28 Lead Wire 29 Monitor

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Tokuo Minami 832-2 Katsuta-shi, Ibaraki Pref.Hitachi System Plaza Katsuta “Inside Hitachi Image Information System” No. 832 2 Hitachi System Plaza Katsuta "Inside Hitachi Image Information System Co., Ltd." (56) References JP-A-5-312889 (JP, A) JP-A-5-80112 (JP, A) JP-A-6 -11535 (JP, A) JP-A-6-75000 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G01R 31/12-31/14 G01R 31/02

Claims (1)

(57) [Claims] 1. A high-voltage equipment, Te was <br/> with denoising filter used on the occasion to partial discharge measurements of the power cable (line), the synchronization timing signal synchronized with zero-cross timing of the division voltage waveform output circuit and, for storing the detection signal waveform analog to - digital (a / D) converter and memory and the pulse in the measurement period during the current measuring Gyoo I and to the number of pulses during the measurement period past are measured comparing the number, the difference between the current number of measuring pulses and past measurement pulse number and a microcomputer for determining the partial discharge pulse conditions as the following various constants, the partial discharge pulse if the condition is satisfied only in the division voltage waveform A circuit for outputting a digital waveform stored in the memory in synchronization with the zero-cross timing ,
A noise removal filter comprising a digital-analog (D / A) converter for converting a digital waveform to an analog waveform .