JPH05322931A - Logic analyzer - Google Patents

Abstract

PURPOSE:To obtain a logic analyzer, which can observe the logic operation that is close to an actual circuit. CONSTITUTION:An A/D converter means 1 converts a signal into a digital quantity. Two threshold values Vih and Vil are imparted into a level classifying means 4. In the level classifying means 4, the logic levels of the signals are classified into H or L or logical uncertainty H>L based on two threshold values. A display control means 5 displays the signal region, which is classified as the logical uncertainty H>L in the level classifying means 4, and the logical uncertain regions in the bus displays of a plurality of channels. The logical uncertain regions are distinguished from the logic region, which is determined as H or L, and displayed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic analyzer for analyzing digital signals of a plurality of channels.

[0002]

2. Description of the Related Art Conventionally, a logic analyzer has been widely used as a measuring instrument for analyzing digital signals of a plurality of channels.

In the conventional logic analyzer, a digital signal shown in FIG. 3 (a) to be analyzed is logically judged to be H or L by one threshold value, and the waveform is shaped as shown in FIG. 3 (b). And store it in memory. In this way, the digital signals of a plurality of channels stored in the memory are taken out from the memory to a display unit such as a CRT if necessary, and the logical analysis is performed by an operation such as superposing the digital signals of the respective channels.

[0004]

However, the signal to be analyzed has a finite rising edge time Tue (falling edge time Tde) as shown in FIG. 3 (a), and therefore the threshold setting level is set. Causes the rise time Tu (fall time Td) of the logic judgment to change.

For this reason, in the conventional logic analyzer, when the logic comparison with other channels is performed, there is a possibility that an analysis judgment different from the logic operation in the actual circuit may be made.

Further, as shown in FIG. 3 (c), an actual signal has crosstalk from another channel, superposition of external noise, and waveform disturbance due to impedance mismatching. In such a case, the disturbance of this waveform cannot be observed. This is because the threshold value is set to the intermediate level of the normal logic judgment level. However, there are cases in which the disturbance of the waveform as shown in FIG. 3 (c), which cannot be observed with the conventional logic analyzer, causes malfunction in the actual circuit.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a logic analyzer capable of easily observing a logic operation situation close to an actual circuit.

[0008]

A logic analyzer according to the present invention is a logic analyzer capable of storing signals of a plurality of channels and displaying the stored signals of a plurality of channels on the same time series, wherein A / D conversion means for converting a level into a digital quantity, and two threshold values are given, and a level classification means for classifying a logic level of a signal as H or L or logic uncertain based on these two threshold values. And a display control means for displaying the signal area classified as logic uncertain in the level classification means and the logic uncertain area in the bus display of a plurality of channels separately from the logic area defined as H or L. It has a feature.

[0009]

With this configuration, by setting the two threshold values to the upper limit value and the lower limit value of the logic determination of the devices constituting the circuit, respectively, it is possible to observe the logical operation in a state close to the actual circuit. It is possible, and the logical uncertainty range in this operating state can be clearly known.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an embodiment mainly including a characteristic part of the present invention.

In FIG. 1, reference numeral 1 denotes an A / D converter which takes an input signal into a logic analyzer of this embodiment by a sampling clock CL sent from a control unit 2. The A / D converter 1 converts the input signal into a digital quantity. The input signal converted and taken in is stored in the memory 3. Similarly, input signals of a plurality of channels are taken into the memory 3.

Reference numeral 4 is a level comparator, and the comparator 4 is provided with two threshold values, a high level threshold value Vih and a low level threshold value Vil, designated by the user. The comparator 3 classifies the input signal read from the memory 3 based on the two threshold values Vih and Vil into H or L and H> L which does not belong to H or L according to this level and controls the display. Send to Part 5.

The display control unit 5 performs necessary logic processing and display processing on the H, L, H> L classification signals for each channel sent from the comparator 4 based on an instruction from the control unit 2, and the display unit 6 to display a bus display on the display unit 6 for each channel or for a plurality of channels.

In the logic analyzer of the embodiment constructed as described above, the signal to be observed is converted into a digital quantity by the A / D converter 1 including the rising and falling edge portions. That is, the analog input signal information including the rising and falling edges of the signal is digitized and taken into the logic analyzer.

In the comparator 4, the high level threshold value Vih is the lowest input voltage that can be recognized as the high level of the device constituting the actual circuit, and the low level threshold value Vil is the constituent device. The highest input voltage that can be recognized as a low level is given.

That is, the comparator 4 uses the high-level threshold value Vih and the low-level threshold value Vil as described above to determine the A / D ratio.
The levels of the converted signals are classified as shown in Fig. 2 (a). In other words, the output is classified into those that can be reliably determined to be logic H or L in the actual circuit and those that are indeterminate logic H> L that cannot be determined to be logic H or L in the actual circuit.

Further, the display control unit 5 has a signal range belonging to the uncertain logic H> L with respect to the signal for each channel sent from the comparator 4, and the signal range belonging to the uncertain logic H> L is defined by diagonal lines and deterministic logic as shown in FIG. It is displayed with a color content different from the H or L part.

Also in the case of a bus display in which a plurality of channels are collectively displayed, the range in which the mutual logic of these channels is not determined is H or L as shown in FIG. It is displayed separately from the definite logic part. In the figure, numbers or symbols represent channels of the same logic displayed in a bus.

According to this embodiment, it is possible to display not only the rising and falling edge portions of the signal but also the portion where the signal waveform is disturbed due to crosstalk or external noise to make the logic uncertain.

In this embodiment, of the two threshold values given, the lowest input voltage that can be recognized as the high level of the device constituting the actual circuit is set as the high level threshold value Vih, and the low level threshold value Vih is also set. As Vil, the one which gives the highest input voltage that can be recognized as the low level of the constituent device has been described, but the operating margin of the circuit can be measured by appropriately selecting these two threshold values.
Further, it is also possible to give a delay to the display signal of the required channel as necessary and observe the change in the logically uncertain range. The present invention is not limited to the above-mentioned embodiments, and can be modified and carried out without changing the gist.
For example, the method of expressing the uncertain logical range is not limited to the method of the above embodiment.

Further, in the above-described embodiment, the case where the input signal stored in the memory after A / D conversion is classified by the comparator has been described. However, it is classified and stored in the memory before being stored in the memory, It is possible to use a configuration in which the analog comparator classifies before A / D conversion.

[0022]

According to the present invention, since a logical operation close to that of an actual circuit can be observed, it is easy to find an unstable operation part. Further, since the logic uncertain range can be clearly displayed on the timing of the logic operation close to the actual circuit, it is possible to easily know the margin of operation and the upper limit of the operation clock.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a time chart explaining the operation of the embodiment.

FIG. 3 is a time chart explaining problems of the conventional logic analyzer.

[Explanation of symbols]

1 ... A / D converter, 2 ... control unit, 3 ... memory, 4 ... comparator, 5 ... display control unit 6 ... display unit

Claims (1)

[Claims] 1. A logic analyzer capable of storing signals of a plurality of channels and displaying the stored signals of the plurality of channels on the same time series, wherein the analog level of the signals is converted into a digital quantity.
/ D conversion means, a level classification means which is provided with two threshold values and classifies the logic level of the signal as H or L or logic uncertain based on the two threshold values, and a logic in the level classification means. 1. A logic analyzer, comprising: display control means for displaying a signal region classified as uncertain and a logical uncertain region in a bus display of a plurality of channels separately from a logical region determined as H or L.