JPS63186153A - Logic analyzer - Google Patents

Abstract

PURPOSE:To perform speedy and accurate counting operation by providing two cursors which move on a displayed input digital signal, a means which counts the state transition number of the input digital signal between the cursors, and a means which displays its counted value. CONSTITUTION:When a display mode is inputted on a keyboard, a CPU reads data out of an acquisition memory in order from a memory address 30 where a gamma cursor 23 is positioned to a memory address 31 where a (c) cursor 24 is positioned according to the program in a ROM. Then the contents of the state transition number storage area in a work RAM are added cumulatively every time patterns 01...10 set in a state pattern setting field 27 are recognized in an input digital signal set in a signal name setting field 28. Then all data in the state transmission number counting range are read out and counted and then the CPU transfers the contents of the state transition number storage area to a video RAM, so that the counted value is displayed in a state transition counted value display field 29.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a logic analyzer used in an oscilloscope or the like having a function of displaying state transitions of an input digital signal in time series.

Conventional logic analyzers have a voltage configuration that allows them to display input digital signals stored in memory in a timing display as a pseudo voltage waveform and as a state display as numerical values such as "0" and "1." has been done. Therefore, when observing the state transition of an input digital signal using the conventional logic analyzer mentioned above,
The timing display shows the rise or fall of the signal waveform, and the state display shows the rise or fall of the signal waveform from "0" to "1".
” or the point of change from “1” to “0”.

Problems to be Solved by the Invention However, in the conventional logic analyzer described above, when counting the number of state transitions of an input digital signal, an observer must visually count the states of the displayed input digital signal one by one. . Therefore, signals with many pulses, such as clock signals, carry signals, decode signals of counter circuits, horizontal synchronization signals, vertical synchronization signals, and clock signals of CRTs, have thick cycles (
When observing a plurality of different signals at the same time, counting the number of state transitions of the input digital signal requires time and effort on the part of the observer, and there is a problem in that counting cannot be done accurately and quickly.

The present invention solves these conventional problems,
The purpose of this invention is to provide a logic analyzer having a function of counting the number of state transitions within a certain section of digital signals stored in a memory using a CPU, and displaying the counted value on a display device. be.

Means for Solving the Problems In order to achieve the above objects, the present invention provides two cursors that move over a displayed input digital signal, and a means for counting the number of state transitions of the input digital signal between the cursors. and means for displaying the counted value on a display device.

Therefore, according to the present invention, by moving two cursors to specific positions on the input digital signal display screen, the number of input digital state transitions between the cursors can be displayed, and the periodic Even when a plurality of signals with significantly different values are simultaneously observed, the number of state transitions of an input digital signal can be quickly and accurately counted.

Embodiment FIG. 1 shows the configuration of an embodiment of the present invention. The digital signal input to the probe 1 is sent from the D/A converter 2 by the comparator in the probe 1 and is compared with the threshold voltage, logically shaped into high level and low level, and sent to the sample/latch circuit 3. The clock selection circuit 4 selects whether to use the external clock sent from the probe 5 as the sampling clock or the internal clock generated by the clock generator 6. The sampled signal is sampled by the sampling clock from the clock selection circuit 4. The glitch detection circuit 7 detects a glitch between the sampling clocks,
The detection signal is sent to the trigger detection circuit 8.

The word detection circuit 9 compares a preset word with the signal ``~'' sampled by the sample latch circuit 3, and if they match, sends a detection signal to the trigger detection circuit 8. The edge detection circuit 10 detects the rising or falling edge of the signal sampled by the sample/latch circuit 3 and sends the detection signal to the trigger detection circuit 8. The trigger detection circuit 8 synthesizes the detection signals from the sample/latch circuit 3, the word detection circuit 9, and the edge detection 1 circuit 10 in a preset combination, and sends the trigger detection signal to the delay counter 11. D, lay counter 1
1 starts operation in response to a trigger detection signal and stops when a preset delay number is counted. When the delay counter 11 stops, the memory address counter 12 also stops at the same time, and the storage operation of the signal sampled by the sample/latch circuit 3 into the buffer memory 13 is completed.

When the above storage operation is completed, the buffer memory 13π-
1. Double cash on delivery. - 1 person R1 each Honnabeima h] S) - Transferred to No So Mori 14. Acquisition memory 14
The data is processed according to the input format (state display, timing display, graph display, etc.) and stored in the video RAM.
Transferred to 15. Display control circuit 16
constantly reads the contents of the video RAM 15 and displays the display device 1.
Generate video signals and horizontal and vertical synchronization signals to be displayed on 7.

The above series of operations is controlled by the CPU (Central Processing Unit) 1.
8 monitors information from the keyboard 20 and the logical state of the hardware according to a program stored in a ROM (read only memory) 19. 21 is a reference memory, and acquisition memory 14
Temporarily memorize by transferring the contents. 22 is C
Work R required when PU18 performs a series of processes
AM (random access memory).

FIG. 2 shows an example of timing display in this actual rotation example, FIG. 3 shows the acquisition memory 14 corresponding to FIG. 2, and FIG. 4 shows the work RAM 22. keyboard 2
When there is a key input from 0 to this display mode, the CPU 18 reads the data in the acquisition memory 14 from memory address 30 where the r cursor 23 is located to memory address 31 where the C cursor address 24 is located, according to the program in the ROM 19. are sequentially read out, and among the above data, 01...10 (1...1 is one or more consecutive 1) is recognized, the contents of the state transition number storage area 34 of the work RAM 22 are cumulatively added.

The CPU 18 reads all the data in the state transition number counting range 33, and when the counting is completed, the CPU 18 stores the data in the state transition number storage area 3.
By transferring the contents of 4 to the video RAM 15, the count value is displayed in the state transition count value display field 29.

As described above, according to the above embodiment, the r cursor 23,
By specifying it with the C cursor 24, the number of transitions is displayed on the display device 17, so that the number of specific state transitions can be counted quickly, accurately, and easily.

In addition, in the above example, the state transition pattern of 01...10 is counted, but this is 10...01.0.
The state transition pattern may be 1.10. In addition, although the above embodiment is an example of timing display,
It may also be a state display.

Effects of the Invention As is clear from the above embodiments, the present invention counts the state transitions of the input digital signal using the CPU and displays the counted value. Therefore, there is no counting error that is common when counting visually, and the process is quick and easy. This has the effect of allowing accurate and easy counting.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a logic analyzer according to an embodiment of the present invention, and FIG. 2 is a block diagram of a logic analyzer according to an embodiment of the present invention. Clock selection circuit, 5... Probe, 6... Clock generator, 7... Glitch detection circuit, 8- Trigger detection circuit, 9... Word detection circuit, 10... Edge detection circuit, 11. ... Delay counter, 12... Address counter, 13... Buffer memory, 14... Acquisition memory, 15...
- Video RAM, 16... Display control circuit, 17... Display device, 18... CPU, 19.
・ROM, 20...Keyboard, 21...Reference memory, 22-RAM, 23"・r cursor, 2
4... C cursor, 25... Timing display data, 26... Signal name, 27... State transition pattern setting field, 28... Signal name setting field, 29...
... State transition count value display field, 30... r cursor memory address, 31... C cursor memory address, 32゛... memory address, 33... state transition number counting range, 34... state Transition number storage area. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
Figure 3 Figure 4]

Claims (1)

[Claims] A trigger detection circuit that detects a specified event from an input digital signal, a memory that stores an input digital signal that is chronologically continuous with the above event, and displays the input digital signal stored in the memory on a display device. a first display means for counting the number of state transitions of the input digital signal that occurs within an interval specified by two different times among the input digital signals stored in the memory, and displaying the number on the display device; A logic analyzer equipped with a second display means.