GB2233102A - Logic analyzer - Google Patents

Abstract

A combined digital and analog signal analyzer comprises a digital part with a plurality of delay lines 41 fed from digital inputs 40, a word recognition circuit 42 fed from the delay lines and programmable to detect desired words, a state sequencer 43 fed from the delay lines and the word recognition circuit, and coupled to a time/event counter unit 44, and a random access memory 45 fed from the delay lines, and preferably also the state sequencer and the time/event counters, and controlled by a further output of the state sequencer via an address counter 46; and it includes an analog part with analog input(s) 50 and an analog-to-digital converter 51 feeding further delay lines 52 which are similarly coupled to the word recognition circuit, the state sequencer, and the random access memory. The analog-to-digital converter may be plug-in module attachable to feed some of the digital inputs. <IMAGE>

Description

L o i c A rl a l y z e r- The present invention relates to logic analyzers.

It is frequently desirable to be able to monitor the operation of some digital circuitry or system, to study its operation if that operation, or some.

aspect of it, is not fully understood. This need arises in particular if the circuitry is not producing the results expected, in which case it may be desirable to monitor the operation of the circuitry either generally or when particular conditions arise in it.

To do this, devices termed logic analyzers have been developed. A logic analyzer is apparatus which is designed to detect specified';onditions or sequences of conditions on a plurality qf logical inputs and to record the subsequent bahaviour of the inputs.

The principles of a known logic analyzer will now be described, by way of example, with reference to the drawings, and in particular to Fig. 1, which is a simplified block diagram of a known logic analyzer.

Referring to Fig. 1, a plurality of inputs 10 are fed to a corresponding plurality of delay lines 11. A word recognition circuit 12 is fed from the delay lines 11, and is programmable to detect desired words. A state sequencer 13 is fed from the delay lines 11 and the word recognition circuit 12, and is also coupled to a time/event counter unit 14. The delay lines 11, the state sequencer 13, and the time/event counter unit 14 feed the data inputs of a random access memory 15, which is controlled by a further output of the state sequencer 13 via an address counter 16. A clock circuit 17 provides high speed (e.g. 100 MHz) clock pulses for use by the rest of the apparatus.

A "word" in this apparatus is a combination of bits appearing simultaneously on the inputs, one bit per input; the word recognition circuit 12 can be programmed to recognize specific combinations of 0, 1, and X (don't care) bits in the words. The state sequencer 13 passes through a sequence of states, in response to conditions which can be programmed into it. These conditions may be the occurrence of specific words tas recognized by the word recognition circuit 12), the occurrence of a specific bit (O or 1) on a specific one of the delay lines 11, or the occurrence of counts in the time/event counter unit 14 which are less than, equal to, or greater than desired values.The time/event counter unit 14 comprises a plurality of counters which can be programmed to count clock pulses and/or events such as the occurrence of particular words or states and to time how long the state sequencer remains in particular states.

The apparatus normally operates at high speed. The passage of the input signals through the delay lines 11 enables the operation of the state sequencer 13 to be synchronized-with that of the word recognition circuit 12, and the operation of the memory address counter 16 to write in the memory 15 to be synchronized with the arrival of the associated data at the memory 15.

The transitions from one state to another of the state sequencer may be simple conditional, each occurring in response to a predetermined condition or combination of conditions (a specific word recognized by the word recognition circuit 12, a specific state of a specific one of the delay lines 11, or a count in the time/event counter unit 14 reaching a specific value), or they may be more complex conditional, such that a given state may be followed by a plurality of further states depending on which of a plurality of combinations of conditions is first satisfied.

The effect of these arrangements is that the apparatus detects the occurrence of particular events in a system being monitored and records the behaviour of the system following the events. More specifically, the apparatus can be programmed to detect an event which consists, in general, of the occurrence of a specific sequence of words and/or bits on the input lines ao the analyzer having specific timing relationships; the apparatus will then record the state or states corresponding to the event, and the signals on the input lines for a desired period following the event.

The apparatus as described so far is purely a digital apparatus; it is incapable of coping with analog signals. However, similar needs arise in analog apparatuses. This it is frequently desirable to be able to monitor the operation of some analog circuitry-or system, to study its operation if that operation, or some aspect of it, is not fully understood. This need arises in particular if the circuitry is not producing the results expected, in which case it may be desirable to monitor the operation of the circuitry either generally or when particular conditions arise in it.

The analysis of analog signals has historically followed a separate line of development, starting with storage oscilloscopes, which can display an analog signal as a waveform. Storage of the waveform is achieved by using a long persistence phosphor. The oscilloscope can be set either to run continuousaly or to operate in triggering mode. In the latter mode, the oscilloscope is triggered either by some pulse signal which is associated with the analog signal to be recorded, or by ~the analog signal itself (in which case the oscilloscope will contain means for setting a threshold voltage which, when reached, triggers the time base to start a fresh trace).

This type of storage oscilloscope has the disadvantage that the storage time of the waveform cannot be controlled; it is determined ~by the persistence of the phosphor. To overcome this, the digital storage oscilloscope (DSO) has therefore been developed. With this, the waveform to be monitored is fed to a digital memory which in turn feeds the screen. Thus the general function is similar, but the waveform can be stored without deterioration as long as desired and then instantly erased. In addition, the user interface has been improved, to provide more features. Also, additional analog channels can be provided, so that the signals on two or more channels can be recorded simultaneously when the DSO is triggered.However, the apparatus is still essentially a "single shot" apparatus intended to allow the monitoring and measurement of analog signals, by storing, when triggered, the analog signal (or all the analog signals) for a single full period of the time-base which has been set into the DSO.

It is frequently desirable to be able to monitor the operation of some digital circuitry or system, to study its operation if that operation, or some aspect of it, is not fully understood. This need arises in particular if the circuitry is not producing the results expected, in which case it may be desirable to monitor the operation of the circuitry either generally or when particular conditions arise in it.

In addition to systems which are substantially either purely digital or purely analog, there are of course many systems which are mixed, parts of them being digital and other parts being analog. The ability to monitor the opera tion of these systems is just as desirable as it is with pure digital and pure analog systems.

In such a system, it is necessary to be able to record either digital signals or analog signals, or perhaps both together. Further, it is desirable to be able to trigger the recording on either a particular digital state of the system or the passage of an analog signal through a threshold value.

We have realized that, by providing signal analyzer apparatus comprising essentially a DSO portion and a digital logic analyzer portion with means for triggering either from the other, these functions can largely be achieved. The DSO portion can be set to trigger on the passage of an analog signal through a threshold value, and this triggering can be used to initiate recording of the digital signals by the digital logic analyzer portion. Similarly, the digital logic analyzer portion can be set to trigger on the occurrence of a particular digital state of the system, and this triggering can be used to initiate recording of the analog signal by the DSO portion. Also, recording by both portions can be initiated simultaneously, whichever portion is used for triggering.

We have realized, however, that although this arrangement appears generally satisfactory, an alternative approach to the problem results in a different type of apparatus which provides a more flexible and integrated solution.

Accordingly the present invention provides a combined digital and analog signal analyzer, comprising: a plurality of delay lines fed from a corresponding plurality of digital inputs; a random access memory fed from the delay lines; control circuitry fed by the delay lines and controlling the memory via an address counter; and, for the or each analog input, an analog-to-digital converter feeding a further plurality of delay lines which are similarly coupled to the control circuitry and the memory. The control circuitry preferably comprises a word recognition circuit programmable to detect desired words, a state sequencer fed from the word recognition circuit, and a time/event counter unit,-and the random access memory may also be fed from the control circuitry.

The analog-to-digital converter may be plug-in module attachable to feed some of the digital inputs.

Thus the analog inputs are converted to digital form and then treated as digital signals just like the digital inputs. The "words" recognized by the word recognition circuit can combine bits from the digital inputs with values from the analog inputs, and great flexibility of triggering on combinations of analog signal thresholds and digital signal values can thus be achieved; and the state sequencer and the time/event counters can operate with equal flexibility on these words. Further, both the analog signals and the digital signals are recorded in the same form in a single common memory, and the length of time for which they are recorded and the recording rate can be controlled with great flexibility by the state sequencer and-time/event counters.

Since the word recognition circuit, the state sequencer, and the time/event counters are common to the.digital and analog channels, there are no timing delays in achieving a comparison of signals on the analog channel and those on the digital channel; and for the same reason, there are no synchronization problems in achieving triggering of the recording of the two channels, or of one channel in response to a triggering signal derived from the other.

In signal analyzer apparatus of the type mentioned above and comprising essentially a DSO portion and a digital logic analyzer portion with means for triggering either from the other, there is duplication of a considerable section of the circuitry and maintenance of previous design architectures, with the associated disadvantages for both the logic analyzer and the DSO, together with the triggering delay. Such duplication and disadvantages are avoided by the present invention.

A combined analog and digital signal analyzer in accordance with the present invention will now be described, by way of example, with reference to the drawings, and in particular Fig. 2 thereof, which is a block diagram of the analyzer.

Referring to Fig. 2, parts corresponding to the Fig. 1 apparatus are referenced 4* instead of 1*. Thus the (digital) inputs 40 feed a set of delay lines 41, and the signals on these delay lines are fed to a word recognition circuit 42 and a state sequencer 43, which is also fed from the word recognition circuit 42.

A time/event counter unit 44 is fed from and feeds the state sequencer 43, which also feeds an address counter 46. A memory 45 is fed from the delay lines 41, the state sequencer 43, and the time/event counter unit 44, and is controlled by the address counter 46.

An analog input 50 is fed to an analog/digital converter 51, which produces a multi-bit digital output, which is fed to a further plurality of delay lines 52.

These further delay lines 52 are largely analogous to the delay lines 41, in that they feed the memory 45, the word recognition circuit 42, and the state sequencer 43.

In operation, a signal on the analog input 50 is converted to a digital form which is passed into the delay lines 52. The (digital) signals in these delay lines represent the amplitude of the analog signal. By programming the word recognition circuit 42 and the state sequencer 43, it is therefore possible for the analyzer to recognize predetermined values of the analog signal and to respond to those values, in conjunction with and in the same way as it recognizes and responds to predetermined values of the digital signals on the inputs 40.

It will usually be desirable for the A/D converter 51 to be of a type which has a high response speed. The delay lines 41 may also be made longer than the delay lines 52 to compensate for any delay in the conversion of the analog input signal at 50 to digital form by the the A/D converter 51, so that the digital signals at 40 are delayed by that additional delay before reaching the tapping points in the delay lines 41 which feed the word recognition circuit 42.

It will often be desirable also for the A/D converter 51 to generate a Gray code, so that false transients are not fed to the word recognition circuit 42 and the state sequencer 43. A range control circuit 53 may be coupled to the A/D converter 51, so that'its range of operation and the trigger threshold values can be preset.

In practice, it may be not necessary to couple the delay lines 52 to the state sequencer 43, but only to the word recognition circuit 42. It may also not be necessary to couple the lower order delay lines 52 to the word recognition circuit 42, but only the most significant ones.

The analyzer of Fig. 2 can thus be programmed to recognize and respond to predetermined conditions on the analog input 50 as well as on the digital inputs 40, and it can record the analog signal < as a sequence of digitized values) along with the digital signals. Depending on the individual analyzer characteristics, the user may program the analyzer and obtain results in analog and/or digital form. The analyzer can also conveniently be provided with a user interface which allows programming of range control and thresholds. Means for displaying analog waveforms in graphical form will normally also be provided.

The state sequencer 43 and the range unit 53 may be coupled together, such that the range and threshold settings of the range unit are programmed to be controlled in dependence on the state of the state sequencer. Thus the user may program the system to have different ranges and thresholds in different states. This allows the user to change the range and threshold, e.g. to a narrower range, for critical conditions, thus giving greater accuracy or sensitivity, while at non-critical periods the range and threshold can be returned to the normal values to provide a "catch-all" environment.

For the word recognition circuit 42 to recognize, from the digital value of the analog input signal produced by the A/D converter 51, when the analog input signal crosses a threshold level, a comparison of two digital values may be necessary, and this tends to involve difficulties. The range control circuit 53 may therefore also be arranged to be set table to detect when the analog input signal crosses one or more set table thresholds, and to signal such crossings to the word recognition circuit 42.

It is clear that a plurality of analog signals can be dealt with by providing further analog channels.

The analog-to-digital converter 51 may be connected to the delay lines 52 via a set of two-way switches (not shown), so that in one position of the switches the analog-to-digital converter feeds the delay lines, while in the other position, the delay lines are fed from a further set of digital signal input terminals (not shown). Alternatively, the analog-t9-digital converter 51 and (if present) the range unit 53 may be constructed as a plug-in unit, such as a data pod, for existing and/or future analyzers; by plugging in such a unit, a number of the digital channels would be converted to analog use by receiving the outputs of the digital-to-analog converter of the plug-in unit. These arrangements provide valuable additional flexibility and choice by enabling the analyzer to be operated as a pure digital analyzer with an increased number of channels.

Claims (8)

Glaims

1 A combined digital and analog signal analyzer, comprising: a plurality of delay lines fed from a corresponding plurality of digital inputs; a random access memory fed from the delay lines; control circuitry fed by the delay lines and controlling the memory via an address counter; and, for the or each analog input, an analog-to-digital converter feeding a further plurality of delay lines which are similarly coupled to the control circuitry and the memory.

2 A signal analyzer according to claim 1, wherein the control circuitry comprises a word recognition circuit programmable to detect desired words, a state sequencer, and a time/event counter unit.

3 . A signal analyzer according to either previous claim, wherein the random access memory is also fed from the control circuitry.

4 A signal analyzer according to any previous claim, including a range control circuit coupled to the A/D converter such that the range of operation and the trigger threshold values of the A/D converter can be preset.

5 A signal analyzer according to claim 4, wherein the state sequencer and the range unit are be coupled together such that the range and threshold settings of the range unit can be controlled in dependence on the state of the state sequencer.

6 A signal analyzer according to either of claims 4 and 5 wherein the range control circuit is also set table to detect when the analog input signal crosses one or more set table thresholds, and to signal such crossings to the word recognition circuit.

7 A signal analyzer according to any previous claim wherein the or each analog-to-digital converter is a plug-in module attachable to feed inputs which could otherwise act as digital inputs.

8 A combined digital and analog signal analyzer substantially as herein described.