JPS6057266A - Logic analyzer - Google Patents

Abstract

PURPOSE:To display a state of various logical signals by controlling a write of an input signal basing on the number of times of generation of a qualifying condition and a trigger condition. CONSTITUTION:A digital signal is inputted to an acquisition system part 250 from a data probe 100. Also, integers K and N, a qualifying condition and a trigger condition are set by a keyboard 1100 and a CPU800. In this state, whenever the qualifying condition is generated K times, the digital signal is written to a measurement control part 400, and basing on a fact that the trigger condition has been generated N times, the write is stopped.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an apparatus for displaying the logical state of a digital signal.

Logic state analyzers, traditionally devices that display the logic state of digital signals, enable storage of an input data state in response to satisfying one preselected qualifier metate, and a second qualifier. It only activates the storage of data states that satisfy the state conditions. The display mode includes some type of vector mapping based simply on the entire data state being formatted, stored, or stored.

The multiple trigger circuit included in one embodiment of the present invention is
2-13741 "Trigger signal generation circuit" is used. These trigger circuits generate output signals in response to an input data state that satisfies one of the preselected quali-7ia state conditions.

A counter and associated seedance logic circuit are connected to the first group of trigger circuits to determine when the storage of input data states should be activated. Another trigger circuit generates a signal to the seedance logic circuit to restart the energization sequence in response to detection of a restart state condition. Data state storage is
It is further modified by a second group of trigger circuits. The output signals of this second group of trigger circuits are OR-combined and then provided to a memory logic circuit, which stores only data states that meet one of the preselected state conditions. A second memory is loaded in parallel with data states stored in the first memory. The data loaded into the second memory includes the contents of the binary counter. A binary counter is connected to either or alternately the internal clock circuit or the counting trigger circuit. The internal clock circuit is configured to determine the time relationship between stored states, and the count trigger circuit is configured to count occurrences of the predetermined data states. A counting trigger circuit determines the number of occurrences of input data states that satisfy a counting qualifier metate interval between storage of selected data states.

The input data state is formalized by focusing adjacent cents on the letter label. Each label may be sequentially treated as an independently addressable field, and an independent base number may be selected for each label. References to next operations and input data refer to these labels. For flat display, the label fields are chained together in alphabetical order.

An alternative graphing display plots the binary number of stored pits corresponding to a selected label field as a function of repeatable position in storage.Distribute the 32 manual data channels into the parameters of interest. Formalize the process as much as possible.

Each adjacent data channel is represented as a single parameter, and each has 6 labels σ)
FIG. 1 is a diagram showing the designation of the display format. In the figure, the black rectangular area indicates a selective input field. In the figure, 16 bits of the address node are assigned to the label "A" and 8 bits of the data node are assigned to the label "D".
Ru. Also, 1 bit of POD (IL/l) is assigned to label "F", and the remaining 7 bits are not assigned (represented by symbol "X"). Further specification and data manipulation is done with reference to the labels in L. For each group of labels assigned in this way, a positive or negative "logical polarity" and a
The base number is specified as base, octal, decimal, or hexadecimal. Additionally, the positive or negative clock transition ("clock slope") at which the input data channel is sampled is selected.

FIG. 16 is a diagram showing the flow of display forming logical operation;
The figure shows the format of a label formation file. 16th
When input signals are given from the keyboard to the microprocessor 800 shown in the figure, a label forming file as shown in detail in FIG. 15 is constructed. It contains parameters that specify the display format. It is also used to process stored data states in the 1cII display data file and graph display data file that are consecutive in 4BC order. One of the above two display data files is then selected and used for display purposes by the display control module 700 and the CRT display 1000.Trace condition input data channels are specified for each assigned label. It is sampled at each clock transition, and is treated as a solidly sampled state.

The trace conditions determine which sampled states should be stored for display and which sampled states should be counted for counting measurements. Trace conditions include the definition of state conditions that specify race positions, selective traces, and count measurements.
The state of this input data channel is defined as an arbitrary combination of 1.0 or × (irrelevant) when the radix is binary. When the base number is octal, decimal, or hexadecimal, the state condition is appropriately specified using alphanumeric characters and x.

Initiate the trace position in response to input data that satisfies a predetermined state sequence (s 'II'&R
T), center (olTgrt) or end (IIEN
D>, selective tracing is possible.

Based on the present application, such selective tracing can be reliably performed. Once a state sequence of up to 7 states is specified and satisfied by the 62 order, intermediate states in the state sequence that are not satisfied are thereby ignored.

The simplest state sequence is a single state condition. Branch, loop or nested states can also be directly analyzed by properly defining the state sequence. Furthermore, each state condition in the state sequence is 1 before the state condition is satisfied.
Specified to occur ~65536 times. This type of positioning allows analysis of the Ith bus of a loop starting at a given state count. Clock delays are implemented by defining the nth occurrence of either state. If the predetermined state sequence is not satisfied prior to or concurrently with the analysis based on the predetermined or start state conditions, the trace logic is specified to again perform an operation that will satisfy the predetermined state sequence. In an "any state" restart operation, it is reassuring that the state sequence is satisfied without any undefined intermediate states.

FIG. 2 is a diagram showing trace condition display. The display shown is for a trace position that begins by satisfying a four-step sequence. Restart state conditions are also defined.

Selective tracing is modified so that the sampled states are stored for display.9 σ) Words from 1 to 7 can be specified as state conditions. By tracing, it is possible to save wasted time searching for unnecessary states, so that the apparent size of the trace is expanded beyond the 64 terms of the trace. In addition, a 51C1 generated word is specified to be stored only every nth satisfaction of the state condition specified by the logical sum. It also shows the condition.

Measure the “time” or “state count” corresponding to each of the 64 stored states,
It is then displayed in one of the following two formats.

Absolute format: Counting from the trace position Relative format: Counting from the previous trace state Time counting is done by counting the number of internal clock occurrences between sequentially stored states. and the display takes place in seconds. For state counting, it is sufficient to simply count the number of occurrences of finger 11 test state 14: ("count") between sequentially stored states. for example,
Specifying "any state" results in a count of the selected clock transitions of the incoming data. In FIG. 2, state counting is done by the occurrence of a specified state condition in the middle of each stored sampled state.

Internal Measurement End Storage 64 One complete measurement pane of sample states is stored internally, and the measurement end contains a sample state that satisfies the display format, trace conditions and state conditions that define the display specification and state sequence. is included. The "current measurement 1st shift" is stored and used as a 0 store measurement 1st pass for later analysis. ``Trace comparison'' compares the results of a previously stored trace with the current measurement end and is used as a further qualifier for data storage. state

Display specification The output display format of the latest measurement end is selected from trace list, trace graph, or trace comparison.

FIG. 3 is a diagram showing a trace list display of stored data states. In the figure, the trace list is a listing of stored states in the order of their occurrence.
The trace states (1 state per line) appear simultaneously on the CI%T display screen. ROLL" key will allow scanning of the 64 stored states. Each line will contain the line number, the states stored according to their radix in alphabetical order on the assigned label, and a time or state count (if selected). ) is included.

FIG. 4 is a diagram showing a trace graph display of stored data states. In the figure, the trace graph shows the relationship between the data size at a given label and the storage location of all 64 stored states. Each state is given a vertical position corresponding to its binary size, and The horizontal position increases according to the order in which states occur. The result is shown as an analog waveform on the oscilloscope display by the magnitude of the voltage. The label to be graphed is ``graph label''
is selected by specifying.

Scaling of magnitude by state content is controlled by specifying an ``upper'' and ``lower'' limit on the vertical axis. These upper and lower limits are specified by being changed proportionally or activated according to logarithmic automatic range control.

Therefore, a portion of the graph can easily be doubled to display at full scale. 20 points corresponding to the lines observed on the trace list shine brightly. This brightness-enhanced portion is also responsive to the "RO to L" control, and their corresponding absolute values are read as traces.

FIG. 5 is a diagram showing a display list of trace comparison output. In the figure, the trace comparison tabulates the differences between the data in the ``Latest measurement run'' and the data in the 6 stored measurements. This listing is done in a similar format as in the trace list. .

The two measurement results are output and displayed as an exclusive OR. That is, identical bits are O, and unequal bits are 1.
The octal number 03" is displayed as the binary number "000".
011"K-equal, and the two bits on the right indicate that the two measurements are different. Trace comparison also reveals a 6-compared traces" mode, in which the current instrument and the stored instrument Rerun the measurements until they are equal or no longer equal. This is 5TOP=
Alternatively, it is performed according to the s'ro p≠ key.

trace mode There are three trace modes as options.

6 trace" performs a single latest measurement; 1 continuous trace" continuously repeats the execution of the latest measurement. “
The most recent measurement is repeated until the desired comparison of the compared traces is obtained immediately after the stored measurement.

Clock Energization and Trigger Output The trigger output generates pulses that can be used for contour measuring instruments such as oscilloscopes. A 501S pulse is generated each time a trace position is observed. The clock enable output is useful for gating the clock or interrupting the device under test.

A high signal level of 1 indicates that the instrument is searching for the trace position.20 The activation output is at a high signal level while the trace position is found or the stop key is pressed. Keyboard and Condition Specification Figure 6 shows the input keyboard. In the figure, the keys are divided into four blocks according to their functions.
r MEASURIi:MENr DISPLAY”
.

'EN'rRY'', ``EDIT''OYOHI''EX
ECUTESTORE". (Due to the war-up sequence, the initial display format is arbitrary, and then the hexadecimal trace list display is automatically selected.

By operating the "ROLL DISPLAY" key, any part of the 64 stored states can be displayed. ”FORMAT 5PECIF'ICA
Press the ``TION'' key to change the display format.E[)
The cursor keys on the IT block move the cursor, which flashes an inverted video field on the display surface to point out the selectable entry field.

"rRAcE 5PECIF'ICATION"r--
Trace conditions can be edited by selecting the display of trace conditions by operating K. This editing is accomplished in a manner similar to how display format specifications are edited.

DETAILED DESCRIPTION The input state is
Two high impedance change thresholds (detected via direct data probes).

FIG. 7 is a block diagram of a digital signal display device according to an embodiment of the present invention. In the figure, data probe 1
00 is divided into four 8-bit data bonds and a fifth bond for clock detection.

Each bond is reset directly to the TTL logic level or variably adjusted within the range of +lOv to -10v to translate the input logic level. data probe 100
The clock signal and 32 human-powered data channels from
Input to state recognition module 200. An internal sampling clock is generated in response to the selected clock slope, an input data signal is selected and compared to a threshold DC voltage, and then the data signal is generated in response to the generation of the internal sampling clock. The state recognition module 200 is launched on the high speed capture system bus 5.
To 00? Output the knobled state. Indexing module 300 accesses sampled states of capture system bus 500-1, compares the sampled states to selected state conditions, and defines trace locations, selective storage events, and state count events. The measurement control module 400 also accesses the capture system bus 500 and stores state or time counts and sampled data states in response to events detected by the index module 300. The bus 600 is connected to other system modules, and the bus 600 transfers selected data and addresses the selected module.

FIG. 8 is a diagram showing the address contents of the memory in the device of the present invention. In FIGS. 7 and 8, the communication bus 600
The sampled data states stored in the memory of the state counting measurement and measurement control module 400 are accessed at an address between 1800 and IFFF'.

FIG. 9 is a diagram showing the relationship between physical addresses and logical addresses in the memory of FIG.

FIG. 10 is a detailed block diagram of the capture system unit 250 in FIG. 7. In the figure, the sampled states of the capture system bus 500 are multiplexed by the Intex module 300.
It is first compared with the qualifier state conditions stored in 5, thereby detecting the trace position. The digital pattern trigger circuit included in the multiple pattern recognition unit 315 is disclosed in Japanese Patent Application No. 52-137, for example.
741 r) Riga Master Generation Circuit".

FIG. 11 shows the multiple pattern recognition unit 315 of FIG.
FIG. 2 is a more detailed block diagram of FIG. In the figure, the multiple pattern recognition unit 315 includes a plurality of 4-bit memories to detect up to eight qualifying state conditions, where each qualifying state condition is
The binary format of l, O, and X inputs are determined to be the same.

Referring again to FIG. The pattern selector 325 is
Select one of the 88 Mg line outputs from multiple pattern recognition units 315 and provide the selected output to state counter 345. Counter 345 counts 1 the number of occurrences of the selected qualifier state condition and generates an output in response to the number of occurrences of the selected qualifier state condition reaching a certain number. This output corresponds to the item ``Break Event'', and for the sequence ethics circuit 350 to respond, the pattern selector 325 must select the next qualifier state condition in sequence, and the counter 345 must count the corresponding count. It is necessary to select Sequence logic circuit 350 +t −j f, NEXT TOLAST B
N-1” in response to the detection of the occurrence of “REAKEVENT”.
Outputs the event flag.

FIG. 12 is a block diagram illustrating a simplified sequential trigger circuit. In the figure, multiple pattern recognition unit 3
16 includes multiple pattern recognition unit 315 and pattern selector 3250 functionality. Furthermore, although the sequence logic circuit 351 has the function of the sequence logic circuit 3500, the only drawback is that the final trigger is output in response to completion of the state sequence. Another way to implement multiple pattern recognition unit 316 is to provide a maximum of three selector bits at the address, so that when the comparator compares the sequential state conditions of the state sequence, each of the memory The comparison is made according to segments.

Referring again to FIG. Outside the point board, where trace selector 320 is OR'ed with the AME line, selective traces are provided in a similar manner.Trace counter 3
40 counts the OR output of each =lnth'' and jMIE and outputs a trace event flag.

The risk unit 310 causes the sequence logic circuit 350 to restart operation to satisfy the state sequence following selection or detection of a start state condition. Restart unit 310 is disabled by sequence logic circuit 350K for data states corresponding to detection of a break event. By setting the restart state condition to one state by the logic circuit 350, the state sequence will be satisfied without any unspecified intermediate states. A counter in measurement control module 400 is strobed upon detection of each state condition.

FIG. 13 shows the measurement control module 40 shown in FIG.
0 is a more detailed block diagram of FIG. Figure 10 and 1
In FIG. 3, event flags from index module 300 are input to high speed control unit 460 and it is determined which temple states should be stored on capture system bus 500. 460 is a data memory 410 and a counting memory 4
20 is then addressed.

FIG. 14 shows the data format of data memory 410 shown in FIG. 1O. In the figure, the sampled state conditions resulting from the pre-event are sequentially stored in positions 1-(N-1). Upon detection of the "N-t" event flag, sampled state conditions are written to the remaining memory locations sequentially, so that when the memory is flush, it is written over the oldest data. The trace location address of the memory location containing the state condition resulting in the final trigger is stored in a register, and the sampled state is written to the appropriate numbered location of the remaining storage device. For example, if the trace is defined at the end by detecting the trace position, the shortened state will not be written following the detection of the trace position. - Easily reconstructed by recovery of the trace location address that appears in the image.

A count selector and synchronizer 450 controls the measurement pupil counter 430, the contents of which are stored in the count memory 420 by updating memory addresses. The low speed interface capability provided by low speed control unit 480 allows high speed control unit 460 to be programmed and to select and latch data for the communication bus 600 interface.

Strobe generator 400 shown in FIGS. 1O and 13
generates a sequence of strobes. When the strobe is introduced into a series of data latches (not shown) and timing logic (not shown), it performs its functions in an orderly manner.

In practice, there are many assembled states in various stages that are processed simultaneously at one time.

Definition of Active Channels Refer again to FIG. 1. Symbol 6! " appears under the assigned input data channel μ in the display format specification. Approximately once every 1 (mS) the sampled state is compared to the 6 final samples" buffer. The state detects any bit change by exclusive OR. And the result is active buffer and 6
The absence of the last sample ``sample to state input to the buffer is ANDed with the sample to state input to the buffer. After 100 samples the active buffer is sampled for display purposes,!'' indicates that the low channel is active; and indicates that the bond clip has become dislodged during the measurement and indicates that the channel is unfavorable in the same or other respects. It is therefore very convenient to use.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the designation of the display format of the logic analyzer of the present invention. FIG. 2 is a diagram showing trace condition display of the logic analyzer of the present invention. FIG. 3 is a diagram showing a list display of stored data states of the logic analyzer of the present invention. FIG. 4 is a diagram showing a graphical representation of stored data states of the logic analyzer of the present invention. FIG. 5 shows a display list in comparison mode of the logic analyzer of the present invention. FIG. 6 shows an input keyboard of the logic analyzer of the present invention. FIG. 7 is a block diagram of the logic analyzer of the present invention, and FIG. 8 is a diagram showing the contents of the memory of the logic analyzer of the present invention. FIG. 9 is a detailed block diagram showing the address relationship of the logic analyzer of the present invention, and FIG. 11 is a more detailed block diagram of the multiple pattern recognition unit 315 of FIG. 10. FIG. 12 is a block diagram of the sequence trigger circuit of the logic analyzer of the present invention. FIG. 13 is a more detailed block diagram of the measurement control module 400 of FIG. FIG. 14 is a diagram showing the data format of the data memory 410 shown in FIG. 10. FIG. 15 is a diagram showing a label format file for logic analysis of the present invention. FIG. 16 is a diagram showing the flow of the display forming logic operation of the logic analyzer of the present invention. 100: Data flow rope, 200 New state recognition module, 300: Index module, 400:
Measurement control module, 250: Acquisition system section, 700
: display control module, 800: microprocessor module, 900: a display MIX movement module, 1
000: CR,T, 1100: Keyboard, 1
200: Self-test flow probe drive module, 13
00: Flint. ■ 1 1 1 FIG, 15 Label Display Format File Continued on Page 1 0 Inventor Gorton Nie Grie Ameline Ray Rebra0 Inventor Steep Society Niece Amerieno f-
Don Tae @ Inventor F. Duncan Terry Amerieve.
1615 Q Place, Colorado Springs, Colorado, United States 3605 Pailin Dan, Colorado Springs, Colorado, United States Apartment 20 2760 Amepen Colive, Meridian, Idaho, United States

Claims (1)

[Claims] an input section into which a digital signal is input; a setting means for setting integers K, N, a qualifying condition, and a trigger condition; writing the digital signal every time the qualifying condition occurs one or more times; and writing the digital signal every time the qualifying condition occurs N times; A logic analyzer comprising: storage means for stopping writing based on what has happened.