GB1593128A - Logic state analyzer - Google Patents

Description

(54) LOGIC STATE ANALYZER (71) We, HEWLETT-PACKARD COMPANY, of 1501 Page Mill Road, Palo Alto, California 94304, United States of America, a corporation organised and existing under the laws of the State of California, United States df America, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described, in and by the following statement: This. invention is concerned with logic state analyzers.

The subject matter of the present patent application is related to the invention disclosed in U.S. Patent Specification No. 4040025 and is related to U.S.

Patent Specification No. 4100532.

Prior art logic analyzers provide merely for enabling the storage of input data states in response to a selected number of satisfactions of a single preselected qualifier state condition and for the storage of data states satisfying a second qualifier state condition. Display modes have comprised formatted listings or certain vector mappings based solely on the entire data state stored.

The present invention provides a circuit for use in the analysis of a digital device by providing an output signal in response to the data states of a monitored digital signal satisfying a sequence of qualifier state conditions, the circuit comprising first pattern recognition means having a first input coupled to receive the digital signal, a second input coupled to receive signals representative of a sequence of qualifier state conditions, a third input and an output, the first pattern recognition means selecting one of the qualifier state conditions in response to receiving a signal on the third input and producing a signal on the output in response to the data state of the digital signal satisfying the selected qualifier state condition; first counter means having a first input coupled to the output of the first pattern recognition means, a second input coupled to receive a sequence of occurrence integers, a third input and an output, for sequentially selecting the occurrence integers in response to receiving a signal on the third input and producing a signal on the output in response to counting a number of signals on the first input equal to the selected occurrence integer; and sequence means having a first input coupled to the output of the first counter means, first and second outputs coupled to the third inputs of the first pattern recognition means and the first counter means respectively, and a third output, for providing signals on the first and second outputs in response to a signal on the first input and providing a signal on the third output in response to the Nth signal on the first input where N is the number of qualifier state conditions in the sequence.

In a circuit as set forth in the last preceding paragraph, it is preferred that the first pattern recognition means comprises a random access memory having a plurality of storage elements providing an output signal representative of data stored in a storage element selected in response to signals appearing on the first and third inputs thereof.

A circuit as set forth in the last preceding paragraph but one may further comprise first storage means having a first input coupled to receive the digital signal, a second input coupled to the output of the first counter means, and a third input coupled to the third output of the sequence means, the first storage means storing at least one data state of the received digital signal in response to a signal appearing on the second input and storing a sequence of data states of the digital signal in response to a signal appearing on the third input thereof A circuit as set forth in the last preceding paragraph may further comprise second counter means having a first input coupled to receive an applied signal having recurring events and an output for providing a signal on the output representative of the count of recurring events, and second storage means having a first input coupled to the output of the second counter means and a second input coupled to the output of the first counter means for storing a signal representative of the count from the second counter means in response to a signal on the second input.

A circuit as set forth in the last preceding paragraph may further comprise a second pattern recognition means having a first input coupled to receive the digital signal, and a second input coupled to receive signals representative of a preselected qualifier state condition for providing the applied signal in response to the data state of the digital signal satisfying the preselected qualifier state condition.

A circuit as set forth in the last preceding paragraph but four may further comprise a second pattern recognition means having a first input coupled to receive the digital signal, a second input coupled to receive signals representative of a preselected qualifier state condition, a third input coupled to the output of the first counter means, and an output coupled to a second input of the sequence means, the second pattern recognition means producing a signal on the output in response to a data state of the digital signal satisfying the preselected qualifier state condition with no signal present on the third input, and the sequence means applying signals to the third inputs of the first pattern recognition means and the first counter means for selecting the initial qualifier state condition and occurrence integer in response to a signal on the second input.

The present invention further provides a method for use in the analysis of a digital device by providing an output signal in response to the data states of a monitored digital signal satisfying a sequence of qualifier state conditions, the method comprising the steps of selecting a sequence of qualifier state conditions: selecting a sequence of occurrence integers with one occurrence integer associated with each qualifier state condition; detecting in sequence the satisfaction of each qualifier state condition by data states of the digital signal N times, where N is the associated occurrence integer; and providing the output signal in response to the detection of the last qualifier state condition the associated number of times.

A method as set forth in the last preceding paragraph may further comprise the step of storing at least one data state of the digital signal in response to each detection of a satisfaction of each qualifier state condition N times and storing a sequence of data states of the digital signal in response to the Nth satisfaction of the last qualifier state condition.

A method as set forth in the last preceding paragraph may further comprise the steps of counting recurring events on an applied signal; and storing the count in response to the storage of data states.

In a method as set forth in the last preceding paragraph it is preferred that the applied signal is provided in response to the data state of the digital signal satisfying a preselected qualifier state condition.

A method as set forth in the last preceding paragraph but three may further comprise the steps of selecting a restart qualifier state condition; detecting data states of the digital signal satisfying the restart qualifying state condition; and restarting the step of detecting in sequence in response to detecting a data state of the digital signal satisfying the restart qualifying state condition.

Sequential data states of a binary data signal are sampled for logical analysis.

A trace specification defines which of these sampled data states are stored in memory for display. The trace specification includes definitions for (a) a trace position, (b) a selective trace, and (c) a count measurement. These definitions are explained more fully below.

The trace position (a) definition is a sequence of qualifier state conditions which must be satisfied before sampled data states are stored into a first memory.

Once the trace position definition is satisfied, the data states are further qualified by the selective trace definition.

The selective trace (b) definition is a set of qualifier state conditions. Only sampled data states meeting one of these qualifier state conditions are stored into the first memory. Thus, once the trace position definition is satisfied, sampled data states satisfying the selective trace definition are stored into the first memory.

Since every data state is not necessarily stored in memory, it is often desirable to determine the number of occurrences of a type of data state intermediate to stored data states. Thus, a count measurement definition (c) of qualifier state condition is associated with a counter for counting the number of times the count definition is satisfied by sampled data states. A second memory has a one-to-one correspondence with the first memory each time a data state is stored into the first memory. Alternatively, a clock signal can be coupled to the counter resulting in the storage of counts into the second memory representing the elapsed time between stored data states.

Detection of the satisfaction of the defined qualifier state conditions is accomplished by the use of multiple triggering circuits of the type described in detail hereinafter. These triggering circuits provide output signals in response to an input data state satisfying one of a number of preselected qualifier state conditions. A counter can be associated with a triggering circuit to further require a defined number of occurrences of a defined state condition before enabling a storage function. Further, the preferred embodiment provides for the storage of the sampled data states which satisfy the sequence qualifier state conditions (hereinafter referred to as "break events").

There now follows a detailed description which is to be read with reference to the accompanying drawings of an embodiment of the invention selected for description to illustrate the invention by way of example only.

In the accompanying drawings: Figure 1 illustrates the interactive format specification display; Figure 2 illustrates the interactive trace specification display; Figure 3 illustrates a trace list display of the stored data states; Figure 4 illustrates a trace graph display of the stored data states; Figure 5 illustrates a trace compare output display list; Figure 6 illustrates the input keyboard; Figure 7 illustrates a block diagram of the present invention; Figure 8 illustrates the distributed memory addressing of the present invention; Figure 9 illustrates the relationship between physical and logical addresses of the distributed memory of Figure 8; Figure 10 is a block diagram of the acquisition system; Figure 11 illustrates a multiple pattern recognition unit; Figure 12 illustrates a simplified sequential triggering circuit; Figure 13 illustrates the measurement and control module; Figure 14 illustrates the data format of the data memory; Figure 15 illustrates the format of the label format file; and Figure 16 illustrates the logic flow of the display formatting logic.

Format Specification Data formatting permits the partitioning of 32 input data channels into parameters of interest. Contiguous data channels which behave as a single parameter may be assigned to one of six labels (A-F). For example, in Figure 1, illustrating the interactive format specification display, 16 bits of an address bus have been assigned to label "A", 8 bits of a data bus have been assigned to label "D", 1 bit of data on pod 1 has been assigned to label "F", and 7 bits have been left unassigned (labeled "X"). Further specifications and data manipulations are made by referencing these labels. Each assigned label may be independently declared to have a positive or negative "logic polarity" and converted to an independently selected radix which can be binary, octal, decimal or hexadecimal.

Further, the slope of the positive or negative clock transition at which time the input data channels are sampled can be selected ("clock slope").

Keyboard entries to the microprocessor 800, as shown in Figure 16, permit the construction of the label format file, shown in more detail in Figure 15 which, contains the format specification parameters. This is used to process the stored data states in the construction of the alphabetically concatenated ASCII display data file and the graphic display data file. Either of the display data files is subsequently selected and used for display purposes by the display control module 700 and the CRT display 1000.

Trace Specification The assigned input data channels are sampled at the specified clock transitions and are treated as one sampled state. The trace specification defines which of the sampled states are to be stored for display and which sampled states are to be counted for count measurement. The trace specification comprises a definition of state conditions specifying the trace position, the selective trace, and the count measurement. Each state condition defines a state of the assigned input data channels in any combination of l's, 0's and/or X's (don't care). In octal, decimal or hexadecimal bases the definition is defined in terms of the appropriate alphanumerics and X's.

A trace position may be selected to a start, center or end the selective trace in response to the input data satisfying a predefined state sequence. In this description it will be assumed that the trace position starts the selective trace. A state sequence of up to seven state conditions must be satisfied in a specified order, ignoring intermediate states which do not satisfy the state sequence. The simplest state sequence is a single state condition. Specific segments of branched, looped or nested forms of state flow may be directly located by properly defined state sequences. In addition, each state condition in a state sequence may be specified to occur from 1 to 65536 times before the state condition is satisfied.

This form of positioning will locate the nth pass of a loop beginning at a give state condition. Clock delay may be incorporated by defining the nth occurrence of any state (an all don't care state specification). The trace logic may also be specified to restart the satisfaction of the predefined state sequence if it is not satisfied before or concurrently with the location of a predefined restart state condition. A restart on "any state" requires that the state sequence be satisfied without any unspecified intermediate states. For example, Figure 2 illustrates the interactive trace specification display for a trace position starting upon the satisfaction of 4 state conditions in sequence. A restart state condition is also defined.

The selective trace is a qualification of which sampled states will be stored for display. One to seven state conditions may be "OR" specified for collection.

Selectively tracing only sampled states of interest eliminates the clutter of unnecessary states and magnifies the apparent size of the trace beyond its 64 terms. Also, an occurrence term may be specified so as to store only every nth satisfaction of an "OR" specified state condition. Figure 2 illustrates the selective trace of every occurrence of a single state condition.

The count measurement performs a "time" or a "state" count associated with each of the (64) states stored and can be displayed in one of two formats: absolute-the count from the trace position relative-the count from the previous trace state.

The time count is performed by counting the occurrences of an internal clock between sequentially stored states and the display is in the units of seconds. A state count similarly counts the number of occurrences of a specified state condition ("count") between sequentially stored states. For example, specifying "any state" would result in a count of the selected clock transitions of the input data. In Figure 2, a state count is performed on the occurrences of a specified state condition intermediate to each sampled state stored.

Internal Measurement Storage One complete measurement of 64 sampled states, which includes the sampled states satisfying the state conditions defining the state sequence and specifications of the format, trace, and display, may be internally stored. The "current measurement" may be stored or exchanged with a "stored measurement" for later analysis. A "trace compare" (described more fully below) compares results of a previously stored trace with the current measurement and may be utilized as a further qualifier on data storage.

Display Specification The output display format of the current measurement may be selected from a trace list, a trace graph, or a trace compare.

A trace list, illustrated in Figure 3, displays a listing of the stored states in their order of occurrence. Twenty trace states, (one per line) are simultaneously presented on the CRT display. The "ROLL" keys allow scanning of the 64 stored states. Each line comprises a line number, the stored state alphabetically sorted into assigned labels in their numerical base, and the time or state count if selected.

A trace graph, as shown in Figure 4, presents a graph of the data magnitude of a specified label versus the storage location for all 64 stored states. Each state is given a vertical displacement corresponding to its binary magnitude and an increasing horizontal displacement for successive states in order of their occurrence. The result is a waveform analogous to oscilloscope displays of voltage magnitude. The label to be graphed is selected by specifying the "graphed label".

Scaling of state magnitude is controlled by specifying the "upper limit" and "lower limit" on the vertical axis. Limits can be specified directly or dynamically varied with logarithmic autoranging controls. These facilities allow any portion of a graph to be magnified to a full scale presentation. The 20 points corresponding to the lines viewed in the trace list are intensified. The intensified portion also responds to the "ROLL" controls, and their corresponding absolute value may be read in the trace list.

A trace compare as illustrated in Figure 5 presents a tabular listing of the difference between results in the "current measurement" and the data in the "stored measurement". The listing is formatted and rolled as in the trace list. The results of the two measurements are exclusive "ORED" such that identical corresponding bits are displayed as zeros and unequal bits are displayed as ones. In an octal base a "3" is equivalent to a binary " l 1" and indicates that the right two bits are different in the two measurements. Trace compare also offers a "compared trace" mode which re-runs a measurement until the current and stored measurement are either equal or not equal. (STOP=, or STOP+) for example, in Figure 5 of the instrument has rerun trace measurements until the "current measurement" equalled the "stored measurement", as indicated by the "STOP=" specification and revealed by the array of "0"'s in the comparison.

Trace Modes Three trace mode options are provided. "Trace" executes a single current measurement. "Continuous trace" repeats the execution of a current measurement continuously. "Compared trace" repeats the execution of a current measurement until the desired comparison with the stored measurement is obtained.

Clock Enable and Trigger Outputs A trigger output provides a triggering pulse for external instrumentation such as oscilloscopes. A 50 ns pulse is generated each time the trace position is found.

The clock enable output is useful for gating clocks or interrupting the device under test. A high signal level indicates that the instrument is actively searching for the trace position. It remains at the high signal level until the trace position has been found or the halt key is depressed. Both outputs are suspended when the format specification is displayed to allow measurement of channel activity.

Keyboard and Specification Designation Referring to Figure 6, an illustration of the keyboard, the keys are functionally segregated into four blocks, the "current measurement display", "entry", "edit", and "execute". A power up sequence initially defines a default set of specifications, displays the default format specification, then automatically selects a hexadecimal trace list display. Activation of the "ROLL DISPLAY" keys permits the presentation of any portion of the 64 states stored. To change the format specification, the "FORMAT SPECIFICATION" key is pressed. The cursor keys in the edit block are used to move the cursor, designating a selectable entry field by a blinking inverse video field on the interactive display.

The trace specification can be edited by selecting the trace specification interactive display by activating the "trace specification" key. Editing is accomplished in the same manner as the format specification is edited. A general description of the functions of the individual keys is given in Appendix A. A detailed description of the interactive display entry fields is given in Appendix B.

Detailed Description Input states are sensed through 32 high impedance variable threshold data probes at rates up to 10 MHz. The data probes 100, illustrated in Figure 7, are segmented into four 8 bit data pods and a fifth pod for clock sensing. Each pod may be preset to TTL logic threshold or variably adjusted in the range of +10 to -10 volts to interpret input logic levels.

The 32 input data channels and the clock signal from the data probes 100 are input to the state recognition module 200. An internal sampling clock is generated in response to the selected clock slope, the input data signals are compared to the selected threshold voltages and interpreted, and the data signals are latched in response to occurrences of the internal sampling clock. The state recognition module 200 outputs the sampled state to the high speed acquisition system bus 500. The index module 300 accesses the sampled state on the acquisition system bus 500, compares the sampled state to the selected state conditions and determines the trace position, selective storage events and state count events. The measurement control module 400 also accesses the acquisition system bus 500 and stores state or time counts and sampled data states in response to the events detected by the index module 300.

The module of the acquisition system 250 communicate with other system modules via the communications bus 600, which provides a means for addressing selected modules and for transferring selected data. The entire system functions as a distributed memory, as illustrated in Figure 8. For instance, addresses between 1800 IFFF on the communications bus 600 access the state count measurements and the sampled data states stored in the measurement control module 400 memories. Figure 9 shows another representation of the system architecture, illustrating the relationship between the physical couplings of Figure 7 and the logical addresses of Figure 8.

Referring to Figure 10, the index module 300 detects the trace position by first comparing the sampled state on the acquisition system bus 500 with a qualifier state condition stored in the multiple pattern recognition unit 315. The multiple pattern recognition unit 315 comprises a digital pattern triggering circuit as described in the aforesaid U.S. Patent Specification 4100532. As illustrated in Figure 11, the multiple pattern recognition unit 315 comprises 2 pairs of 8 sixteen by four bit memories providing for the detection of up to eight qualifier state conditions, where each qualifier state condition is identified by a 1, 0, X input, format (in binary). Pattern selector 325 of Figure 10 selects one of the eight lines output from the multiple pattern recognition unit and passes the selected output to the occurrence counter 345. The occurrence counter 345 counts the occurrences of the selected qualifier state conditions and provides an output in response to counting a specified number of occurrences of the selected qualifier state conditions. This output is termed a "break event" and the sequencer logic 350 in response requests the pattern selector 325 to select the next sequential qualifier state condition and requests the occurrence counter 345 to select the corresponding count. The sequencer logic 350 also outputs a "N-l" event flag in response to detection of the occurrence of the "NEXT TO LAST BREAK EVENT". A simplified sequential triggering circuit is illustrated in Figure 12 where the multiple pattern recognition unit 316 incorporates the functions of the multiple pattern recognition unit 315 and of the pattern selector 325. The sequence logic 351 incorporates the functions of the sequence logic 350 except that the final trigger is output in response to the completion of the state sequence.

Another method of implementing the multiple pattern recognition unit 316 would be to have 3 selector bits be the most significant bits in the address, allowing the comparator to sequence through various segments of memory when comparing sequential state conditions of the state sequence.

Referring again to Figure 10, the selective trace is incorporated in a similar manner except that the trace selector 320 of Figure 10 can "OR" any combination of the AME lines. A trace occurrence counter 340 outputs a trace event flag upon counting each "nth" "ORED" AME event.

The restart unit 310 causes the sequence logic 350 to restart the satisfaction of the state sequence subsequent to the detection of a selected restart state condition. The restart unit is disabled for the data state corresponding to the detection of a break event by sequencer logic 350 which permits the state sequence to be satisfied without any unspecified intermediate state by setting the restart state condition to "any state".

The state count unit 305 strobes a counter in the measurement control module 400 each time the selected state condition to be counted is detected.

The measurement and control module 400 is illustrated in Figures 10 and 13.

The event flags from index module 300 are input to the high speed control 460 and determine which sampled states on the acquisition system bus 500 are to be stored. The high speed control 460 addresses the data memory 410 and the count memory 420 accordingly. Figure 14 illustrates the data format of the data memory 410. The sampled state conditions resulting break events are sequentially stored in locations l.(N-l). Upon detection of the "N-l" event flag, sampled state conditions are sequentially written into the remaining memory locations, writing over the oldest data when the memory is filled. The trace position address of the memory location containing the state condition resulting in the final trigger is stored in a register and sampled states are written into the appropriate number of remaining storage locations. For example, if the trace was defined to end on the detection of the trace portion, no sampled states would be written subsequent to the detection of the trace position. The order of occurrence of the stored data is easily reconstructed by recovery of the trace position address appearing on the communications bus 600 as illustrated in Figure 8. Count selector and synchronizer 450 controls the measurement counter 430, whose contents are stored in count memory 420 upon update of the memory address. The low speed control 480 provides a low speed interface for programming the high speed control 460 and for selecting and latching data for the communications bus 600 interface.

The strobe generator 400, illustrated in Figures 10 and 13, generates a sequence of strobes which, when coupled with a series of data latches (not shown) and timing logic (not shown) effectuate the orderly performance of machine tasks.

In effect, a number of sampled states are simultaneously in various stages of processing at any one time and are "pipelined" through the required logic blocks.

Active Channel Determination Referring to Figure 1, the symbol "!" appears below certain assigned input data channels in the format specification. Approximately once every millisecond the sampled state is compared to a "last sample" buffer. The states are exclusively "ORED" to detect any bit changes. The result is then "ANDED" with an activity buffer and the sampled state input to the "last sample" buffer. After 100 samples the activity buffer is sampled for display purposes. Only the assigned channels are displayed. Absence of a "!" indicates low channel activity and is a good indicator that a pod clip may have fallen off during the measurement or the channel is otherwise suspect.

APPENDIX A GENERAL DESCRIPTION-KEYBOARD CURRENT MEASUREMENT DISPLAY LINES 3 THROUGH 24 ARE DEPENDENT ON DISPLAYED MENU CHOSEN, WHICH MAYBE SELECTED BY KEYS IN CURRENT MEASUREMENT BLOCK: FORMAT SPECIFICATION SELECT CLOCK SLOPE AND FORMAT 32 CHANNELS INTO LOGICAL LABELS AND DESIRED LOGIC POLARITY AND NUMERICAL BASE.

TRACE SPECIFICATION DEFINE TRACE POSITION, SELECTIVE TRACE AND COUNT MEASUREMENT.

LIST DISPLAY RESULTANT CURRENT TRACE AND COUNT DATA.

GRAPH GRAPH RESULTANT CURRENT TRACE DATA FOR SELECTED LABEL, THE 2 INTENSIFIED DOTS CORRESPOND TO TRACE LIST DATA.

GENERAL DESCRIPTION-KEYBOARD (cont.) 8-9, A-F, X ALL OTHER FIELDS MAYBE CHANGED USING THESE KEYS.

EDIT DISPLAYED MENUS MAYBE EDITED BY EDIT BLOCK OR KEYS: DELETE INSERT USED IN TRACE SPECIFICATION MENU ONLY TO OPTIONALLY DELETE OR INSERT STATES TO SPECIFY TRACE POSITION AND SELECTIVE TRACE. A MAXIMUM OF 6 STATES MAYBE USED BETWEEN TRACE POSITION AND SELECTIVE TRACE.

DEFAULT RETURN DISPLAYED MENU TO KNOWN (PRESET, TRACEABLE) CONDITION.

INCR DECR USED IN TRACE GRAPH ONLY TO AUTOMATICALLY CHANGE UPPER OR LOWER GRAPH LIMITS. TO MOVE BLINKING CURSOR TO DESIRED FIELD.

EXECUTE THE REMAINING KEYS ARE THE EXECUTE BLOCK OF KEYS: CURRENT MEASUREMENT KEY SAVES CURRENT SPECIFICATION AND DATA MEASUREMENT IN A STORED FILE. THE STORED MEASUREMENT C-UR-RE-NT-SPECIFICATION AND DATA REMAINS UNCHANGED.

KEY EXCHANGES CURRENT AND STORED MEASUREMENT FILES.

PRINT PRINT CURRENT DISPLAY, EXCEPT TRACE GRAPH ON AN HP 9866 LINE PRINTER USING CONNECTOR ON REAR OF 1618A, TRACE LIST AND TRACE COMPARE WILL PRINT CURRENT PAGE AND ANY REMAINING DATA IN MEMORY.

TRACE EXECUTES CURRENT SPECIFICATION, AND IF DISPLAY IS FORMAT SPECIFICATION OR TRACE SPECIFICATION, THE 1618A SWITCHES DISPLAY TO TRACE LIST.

IF TRACE IS HELD DOWN, THE MEASUREMENT IS TRACED CONTINUOUSLY.

IF COMPARE TRACE MODE IS SET FOR (STOP=) OR (STOP#) THE MEASUREMENT IS TRACED UNTIL COMPARED CONDITION IS MET, THE INSTRUMENT STATUS (lust LINE) IS "COMPARED TRACE-FAILED", IMPLIES CONDITION NOT MET, OR "COMPARED TRACE-COMPLETE", IMPLIES CONDITION MET.

STOP STOPS ANY . MEASUREMENT TRACE, COMPARED TRACE OR PRINT IN PROCESS.

APPENDIX B DETAILED FIELD/S DESCRIPTION CLOCK SLOPE: EXAMPLES: CLOCK SLOPE (+) CLOCK SLOPE (-) PURPOSE: 10 SELECT CLOCK TRANSITION TO STROBE POD DATA INTO 1610A.

LABEL ASSIGNMENT AND ACTIVE CHANNELS: EXAMPLE POD 4 POD 3 POD 2 POD 1 7------0 7------0 7------0 7------0 AAAAAAAA AAAAAAAA DDDDDDDD XXXXXXXF !!!!!!!! !!!!!!!! !!!!!!!! ! ACTIVE CHANNELS PURPOSE: TO ASSIGN LABELS A, B, C, D, E OR F TO ANY NUMBER OF CONTINUOUS CHANNELS INDEPENDENT OF POD BOUNDARIES. IN THE ABOVE. EXAMPLE THE LABEL A IS ASSIGNED TO 16 BITS OF POD3 AND POD4, AND MAY REPRESENT A 16 BIT ADDRESS. LABEL D IS ASSIGNED 8 BITS ON POD2 AND MAY REPRESENT AND 8 BIT DATA BUS.

LABEL F IS ASSIGNED TO BE A SINGLE BIT QUALIFIER (READ, WRITE) AND IS ASSIGNED TO LEAST SIGNIFICANT BIT ON POD1.

ANY UNUSED CHANNELS MAYBE TURNED OFF BY PUTTING A "X" IN GIVEN CHANNELS.

COMMENT: AS MANY AS SIX LABELS OR AS FEW AS ONE MAYBE ASSIGNED ACROSS THE 32 CHANNELS. IF A LABEL IS SPLIT, SUCH AS AABBBAAA (LABEL IS NOT CONTINUOUS) THEN AN ERROR MESSAGE "ERROR-SPLIT LABEL" IS DISPLAYED AND THE CURSOR IS LOCKED TO LABEL ASSIGNMENT FIELDS UNTIL THE ERROR IS CORRECTED.

PRESSING DEFAULT KEY WILL ASSIGN LABEL F TO ALL 32 CHANNELS.

ACTIVE CHANNELS ARE SHOWN BY "!" MARKS FOR EACH ASSIGNED CHANNEL. ABSENCE OF "!" INDICATE LOW CHANNEL (BIT) ACTIVITY, AND ARE GOOD INDICATORS OF POD CLIPS THAT MAY HAVE FALLEN OFF. CHANNEL ACTIVITY IS NOT DISPLAYED WHILE 1610A IS TRACING.

IF POD IS CONNECTED TO DATA PORT ON REAR OF 1610A, THE CHANNEL ACTIVITY "!" FOR LEAST SIGNIFICANT 2 BITS IS NOT SHOWN (DUE TO SYNCHRONOUS 8 BIT COUNT AND 1610A).

LOGIC POLARITY: EXAMPLE: LABEL A D F LOGIC POLARITY (-) ) (+) (+, -) DETAILED FIELD/S DESCRIPTION (cont.) PURPOSE: TO SELECT A LOGIC POLARITY FOR EACH ASSIGNED LABEL.

NUMERICAL BASE: EXAMPLE: LABEL A B F NUMERICAL BASE (HEX) (OCT) (BIN) (BIN, OCT DEC, HEX) PURPOSE: TO SELECT A NUMERICAL BASE TO BE HEXIDECIMAL (HEX), OCTAL (OCT), DECIMAL (DEC), OR BINARY (BIN) FOR EACH ASSIGNED LABEL.

TRACE POSITION: EXAMPLE: (START) TRACE (CENTER) TRACE (END) TRACE PURPOSE: TO SELECT TRACE POSITION TO BE SOME GIVEN STATE AND ITS POSITION IN RESULTANT DATA TRACE FILE SHOULD BE AT (START) FOLLOWED BY SELECTIVE TRACE STATES, OR AT (CENTER) SHOWING ANY SELECTIVE STATES BEFORE AND AFTER "CENTER STATE", OR AT (END) SHOWING ANY SELECTIVE STATES BEFORE THE "END STATE".

EXAMPLE: LABEL A OCCUR BASE HEX DEC FIND IN SEQUENCE 10 00001 THEN 20 00001 THEN 30 00005 (START) TRACE 40 00001 SEQ. RESTART (ON) 58 COMMENT: THIS EXAMPLE HAS THE FOLLOWING MEANING FOR DEFINING TRACE POSITION: FIND IN SEQUENCE 00001 OCCURRENCE OF STATE l, THEN THE l OCCURRENCE OF STATE 2, THEN THE 00005 OCCURRENCE OF STATE 3, AND (START) TRACE AT 00001 OCCURRENCE OF STATE 4.

IF DURING THIS SEQUENCE THE RESTART STATE 58 IS ENCOUNTERED BEFORE REACHING THE 00001 OCCURRENCE OF STATE 4, THE MEASUREMENT RESTARTS, TO FIND IN SEQUENCE THE DssDDl OCCURRENCE OF STATE 10, THEN 00001 OCCURRENCE OF STATE 2 ETC.

NOTE: IF A SEQUENCE STATE IS DEFINED TO BE THE SAME AS THE RESTART STATE, THE SEQUENCE STATE DOMINATES. IF (CENTER) OR (END) WERE SELECTED, SELECTIVE TRACE STARTS AT COMPLETION OF 5 OCCURRENCES OF STATE 3 (SEE SELECTIVE TRACE).

SELECTIVE TRACE: EXAMPLE: LABEL A OCCUR (ALL STATES) DETAILED FIELD/S DESCRIPTION (cont.) PURPOSE: TO TRACE ALL STATES.

EXAMPLE: LABEL A OCCUR BASE HEX DEC TRACE (ONLY STATE) 6 OR 7X OR 8X PURPOSE: TO SELECTIVELY TRACE DESIRED STATES.

COMMENTS: THE ABOVE EXAMPLE HAS FOLLOWING MEANING: DO A SIMULTANEOUS TRACE OF 00001 OCCURRENCE OF STATES 6 OR 7X (7 TO 7F) OR 8X (8 TO 8F).

COUNT: EXAMPLE: LABEL A BASE HEX COUNT (OFF) COUNT (STATE) 7X COUNT (TIME) PURPOSE: TO SELECT COUNT MEASUREMENT TO BE (OFF), OR COUNT (STATE) OR COUNT (TIME).

COMMENT: WHEN COUNT IS (OFF), THE TRACE LIST DOES NOT SHOW COUNT DATA FOR THE NEXT TRACE MEASUREMENT. WHEN COUNT (STATE) IS SELECTED, A 32 BIT COUNT QF SELECTED STATE 7X (7 TO 7F) IS STORED IN MEMORY WITH EACH POD DATA STATE STORED. THE RESULTANT COUNT DATA IS DISPLAYED IN TRACE LIST FOR NEXT TRACE MEASUREMENT.

WHEN COUNT (TIME) IS SELECTED, A COUNT VALUE OF TIME IS STORED FOR EACH POD DATA STATE STORED IN MEMORY, THE RESULTANT TIME DATA IS DISPLAYED IN TRACE LIST FOR NEXT TRACE MEASUREMENT.

GRAPHED LABEL: EXAMPLE: GRAPHED LABEL (A) GRAPHED LABEL (F) PURPOSE: TO SELECT A DEFINED LABEL A, B, C, D, E, OR F TO BE GRAPHED.

STATE COUNT OR TIME (ABS), (REL): EXAMPLE: LABEL A STATE COUNT BASE HEX DEC (ABS) SEQUENCE 18 - 1843 SEQUENCE 2 - 1833 SEQUENCE 3 - -1023 START 40 0 + 60 w +02 70 + 30 +03 71 + 31 * * * DETAILED FIELD/S DESCRIPTION (cont.) LABEL A STATE COUNT BASE HEX DEC (REL) SEQUENCE SEQUENCE 20 10 SEQUENCE 30 20 START 4 1023 +01 60 20 +02 70 10 +03 71 1 * * * LABEL A TIME BASE HEX DEC (ABS) SEQUENCE 18 - 28.3 US SEQUENCE 2 - 200.2 US SEQUENCE 30 - 185.1 US START 40 . US +01 60 + 80.0 US +02 70 + 120.9 MS +03 71 + 122.5 MS PURPOSE: TO VIEW TRACE LIST AND SELECT (ABS) OR (REL) FOR STATE COUNT OR TIME DATA COMMENTS: WHEN ABSOLUTE (ABS) IS SELECTED THEN STATE COUNT OR TIME IS DISPLAYED IN +/- ARSOLUTE VALUES WITH RESPECT TO START STATE 4. ALL STATES BEFORE START STATE 40 ARE SHOWN WITH" COUNT VALUES. START STATE 40 IS SHOWN AS ALWAYS . ALL STATES SHOWN AFTER START STATE 40 ARE SHOWN WITH "+" COUNT VALUES.

WHEN RELATIVE (REL) IS SELECTED, THEN STATE COUNT OR TIME IS DISPLAYED SHOWING COUNT VALUES RELATIVE TO PREVIOUS STATE COUNT VALUE (IF VALID) WITHOUT SIGN.

UPPER/LOWER LIMITS: EXAMPLE: UPPER LIMIT 177 LOWER LIMIT 000 PURPOSE: TO CHANGE UPPER OR LOWER GRAPH LIMITS.

COMMENTS; GRAPH LIMITS MAYBE CHANGED USING ENTRY KEYS OR THE LIMITS MAYBE AUTOMATICALLY INCREMENTED OR DECREMENTED USING INCR OR DECR KEYS IN EDIT BLOCK.

THE UPPER LIMIT MUST BE GREATER THAN LOWER LIMIT, ELSE AN "ERROR-OVERLAPPING LIMITS" IS DISPLAYED AND GRAPH DOTS ARE NOT DISPLAYED.

DETAILED FIELD/S DESCRIPTION (cont.) COMPARED TRACE MODE: EXAMPLE: LABEL A COMPARED BASE HEX TRACE MODE (OFF) SEQUENCE 89) SEQUENCE 88 SEQUENCE START +01 30 +02 00 PURPOSE: TO SHOW THE "EXCLUSIVE OR" OF CURRENT DATA WITH STORED DATA, ALL 'S IMPLIES SAME DATA IN BOTH FILES AND NON 8'S (3) SHOWS THAT DATA STATE DOES NOT COMPARE (BITS 4 AND 5, ASSUMING LSB IS BIT ).

EXAMPLE: LABEL A COMPARED BASE HEX TRACE MODE (STOP=) LABEL A COMPARED BASE HEX TRACE MODE (STOP#) PURPOSE: TO SELECT COMPARED TRACE MODE TO BE STOP WHEN EQUAL (STOP=), OR STOP WHEN NOT EQUAL (STOP#).

COMMENTS: WHEN (STOP=) IS CHOSEN THE MEASUREMENT IS TRACED UNTIL VALID CURRENT DATA EQUA:LS (=) VALID STORED DATA, THE STATUS OF INSTRUMENT WILL BE: "COMPARED TRACE-FAILED" WHICH MEANS CURRENT DATA DOES NOT EQUAL STORED DATA, THE 1618A THEN TRACES AGAIN SHOWING: "COMPARED TRACE-IN PROCESS" AND COMPARES ANOTHER SET OF DATA, THIS PROCESS CONTINUES UNTIL: "COMPARED TRACE-COMPLETE" WHICH MEANS VALID CURRENT FILE EQUALS VALID STORED FILE DATA.

A SIMILAR OPERATION EXISTS FOR (STOP#), EXCEPT THIS MEASUREMENT CONTINUES UNTIL FILES DO NOT COMPARE.

NOTE: THIS IS NOT A REAL TIME MEASUREMENT, BUT RATHER A "SAMPLED COMPARED MODE" THAT IS DEPENDENT IN PART UPON DATA CLOCK RATES, TRACE SPECIFICATION. THIS MEASUREMENT MODE MUST BE TURNED (OFF) TO OBTAIN SINGLE OR CONTINUOUS TRACE MODE.

WHAT WE CLAIM IS: 1. A circuit for use in the analysis of a digital device by providing an output signal in response to the data states of a monitored digital signal satisfying a sequence of qualifier state conditions, the circuit comprising:

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (13)

**WARNING** start of CLMS field may overlap end of DESC **. DETAILED FIELD/S DESCRIPTION (cont.) COMPARED TRACE MODE: EXAMPLE: LABEL A COMPARED BASE HEX TRACE MODE (OFF) SEQUENCE 89) SEQUENCE 88 SEQUENCE START +01 30 +02 00 PURPOSE: TO SHOW THE "EXCLUSIVE OR" OF CURRENT DATA WITH STORED DATA, ALL 'S IMPLIES SAME DATA IN BOTH FILES AND NON 8'S (3) SHOWS THAT DATA STATE DOES NOT COMPARE (BITS 4 AND 5, ASSUMING LSB IS BIT ). EXAMPLE: LABEL A COMPARED BASE HEX TRACE MODE (STOP=) LABEL A COMPARED BASE HEX TRACE MODE (STOP#) PURPOSE: TO SELECT COMPARED TRACE MODE TO BE STOP WHEN EQUAL (STOP=), OR STOP WHEN NOT EQUAL (STOP#). COMMENTS: WHEN (STOP=) IS CHOSEN THE MEASUREMENT IS TRACED UNTIL VALID CURRENT DATA EQUA:LS (=) VALID STORED DATA, THE STATUS OF INSTRUMENT WILL BE: "COMPARED TRACE-FAILED" WHICH MEANS CURRENT DATA DOES NOT EQUAL STORED DATA, THE 1618A THEN TRACES AGAIN SHOWING: "COMPARED TRACE-IN PROCESS" AND COMPARES ANOTHER SET OF DATA, THIS PROCESS CONTINUES UNTIL: "COMPARED TRACE-COMPLETE" WHICH MEANS VALID CURRENT FILE EQUALS VALID STORED FILE DATA. A SIMILAR OPERATION EXISTS FOR (STOP#), EXCEPT THIS MEASUREMENT CONTINUES UNTIL FILES DO NOT COMPARE. NOTE: THIS IS NOT A REAL TIME MEASUREMENT, BUT RATHER A "SAMPLED COMPARED MODE" THAT IS DEPENDENT IN PART UPON DATA CLOCK RATES, TRACE SPECIFICATION. THIS MEASUREMENT MODE MUST BE TURNED (OFF) TO OBTAIN SINGLE OR CONTINUOUS TRACE MODE. WHAT WE CLAIM IS:

1. A circuit for use in the analysis of a digital device by providing an output signal in response to the data states of a monitored digital signal satisfying a sequence of qualifier state conditions, the circuit comprising:

first pattern recognition means having a first input coupled to receive the digital signal, a second input coupled to receive signals representative of a sequence of qualifier state conditions, a third input and an output, the first pattern recognition means selecting one of the qualifier state conditions in response to receiving a signal on the third input and producing a signal on the output in response to the data state of the digital signal satisfying the selected qualifier state condition; first counter means having a first input coupled to the output of the first pattern recognition means, a second input coupled to receive a sequence of occurrence integers, a third input and an output, for sequentially selecting the occurrence integers in response to receiving a signal on the third input and producing a signal on the output in response to counting a number of signals on the first input equal to the selected occurrence integer; and sequence means having a first input coupled to the output of the first counter means, first and second outputs coupled to the third inputs of the first pattern recognition means and the first counter means respectively, and a third output, for providing signals on the first and second outputs in response to a signal on the first input and providing a signal on the third output in response to the Nth signal on the first input where N is the number of qualifier state conditions in the sequence.

2. A circuit according to claim 1 wherein the first pattern recognition means comprises a random access memory having a plurality of storage elements providing an output signal representative of data stored in a storage element selected in response to signals appearing on the first and third inputs thereof.

3. A circuit according to claim 1 and further comprising first storage means having a first input coupled to receive the digital signal, a second input coupled to the output of the first counter means, and a third input coupled to the third output of the sequence means, the first storage means storing at least one data state of the received digital signal in response to a signal appearing on the second input and storing a sequence of data states of the digital signal in response to a signal appearing on the third input thereof.

4. A circuit according to claim 3 and further comprising second counter means having a first input coupled to receive an applied signal having recurring events and an output for providing a signal on the output representative of the count of recurring events, and second storage means having a first input coupled to the output of the second counter means and a second input coupled to the output of the first counter means for storing a signal representative of the count from the second counter means in response to a signal on the second input.

5. A circuit according to claim 4 and further comprising a second pattern recognition means having a first input coupled to receive the digital signal, and a second input coupled to receive signals representative of a preselected qualifier state condition for providing the applied signal in response to the data state of the digital signal satisfying the preselected qualifier state condition.

6. A circuit according to claim 1 and further comprising a second pattern recognition means having a first input coupled to receive the digital signal, a second input coupled to receive signals representative of a preselected qualifier state condition, a third input coupled to the output of the first counter means, and an output coupled to a second input of the sequence means, the second pattern recognition means producing a signal on the output in response to a data state of the digital signal satisfying the preselected qualifier state condition with no signal present on the third input, and the sequence means applying signals to the third inputs of the first pattern recognition means and the first counter means for selecting the initial qualifier state condition and occurrence integer in response to a signal on the second input.

7. A circuit, for use in the analysis of a digital device by providing an output signal in response to the data states of a monitored digital signal satisfying a sequence of qualifier state conditions, substantially as hereinbefore described with reference to the accompanying drawings.

8. A method for use in the analysis of a digital device by providing an output signal in response to the data states of a monitored digital signal satisfying a sequence of qualifier state conditions, the method comprising the steps of: selecting a sequence of qualifier state conditions; selecting a sequence of occurrence integers with one occurrence integer associated with each qualifier state condition; detecting in sequence the satisfaction of each qualifier state condition by data states of the digital signal N times, where N is the associated occurrence integer; and providing the output signal in response to the detection of the last qualifier state condition the associated number of times.

9. A method according to claim 8 and further comprising the step of: storing at least one data state of the digital signal in response to each detection of a satisfaction of each qualifier state condition N times and storing a sequence of data states of the digital signal in response to the Nth satisfaction of the last qualifier state condition.

10. A method according to claim 9 and further comprising the steps of: counting recurring events on an applied signal; and storing the count in response to the storage of data states.

11. A method according to claim 10 wherein the applied signal is provided in response to the data state of the digital signal satisfying a preselected qualifier state condition.

12. A method according to claim 8 and further comprising the steps of: selecting a restart qualifier state condition; detecting data states of the digital signal satisfying the restart qualifying state condition; and restarting the step of detecting in sequence in response to detecting a data state of the digital signal satisfying the restart qualifying state condition.

13. A method, for use in the analysis of a digital device by providing an output signal in response to the data states of a monitored digital signal satisfying a sequence of qualifier state conditions, substantially as hereinbefore described with reference to the accompanying drawings.