JPS6057262A - Logic analyzer - Google Patents

Abstract

PURPOSE:To discriminate easily a mutual relation of digital signals by displaying a storage signal by a graph. CONSTITUTION:A printer 1300, a self-test probe driving module 1200 and a keyboard 1100 are connected to a microprocessor module 800. Also, a display driving module 900, a display control module 700 and an acquisition system part 250 are connected through a communication bus 600 to the module 800. The acquisition system part 250 is constituted of a measurement control module 400, an index module 300, and a state recognition module 200. Plural digital signals are inputted from a data probe 100, and stored in the acquisition system part 250. Also, a value of the stored digital signal and a point related to an address of a memory are displayed on an orthogonal coordinate by a CRT1000.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a logic analyzer that displays stored digital signals in rectangular coordinate format. Conventional logic analyzers only have the function of simply displaying a list of stored digital signals, and have the disadvantage that it takes an extremely long time to find out what kind of interrelationship the digital signals have. .

The present invention has been made in view of the above-mentioned drawbacks, and is a logic system that allows the mutual relationship of the digital signals to be easily determined by displaying the stored digital signals in a graph.
The purpose is to provide an analyzer.

(Designation of display format) For example, 32 channels of digital input data are distributed to predetermined parameters and the data is formatted.

FIG. 1 is a diagram showing the designation of the display format of the logic analyzer of the present invention, which is displayed on a CRT. The data of each adjacent channel is divided into 6 labels (LABEL)A
-Assigned to one of F. Data from channels assigned to the same label form a group and behave as a single parameter. In FIG. 1, the rectangular areas indicate fields that can be selectively input. In FIG. 1, 16 bits of the address bus, which is the channel of bond (POD) 3.4, are assigned to label A, and 8 pins 1- of the data bus, which is the channel of bod 2, are assigned to label D. Also, 1 bit of bod 1 is labeled F
The remaining 7 bits are unassigned (represented by the symbol X). Other specifications and data manipulations are performed based on the label. In the diagram, label A
, D, and F are each positive (+), and the case where the logical polarities are positive is determined to be logic 1. Radix (NIJI! RICAL
BASE) are hexadecimal (HEX), hexadecimal, and binary (B
IN). In addition, the base number is 8
It is also possible to define in decimal (OCT) and decimal (DEC). Also, positive or negative clock transitions (CLOCK 5LOPE) when the input data is sampled
) is shown. FIG. 1 shows the case where the clock transition is positive.

That is, it is indicated by (+).

FIG. 16 is a diagram showing the flow of logical operations for display formation in the logic analyzer of the present invention, and FIG. 15 is a diagram showing a label display format file of the logic analyzer of the present invention. In FIG. 16, the keyboard 11
When signals representing label assignments, cardinal numbers, etc. are input to microprocessor 800 via 00, a label display format file as shown in detail in FIG. 15 is constructed. Also, due to the concatenation definition, the ASCIIs are connected in the order of A, B, and C.
It is used to process stored or written data states in I display data files and graph display data files. Meanwhile, input data states captured by capture system 250 are stored in storage devices 410 and 420. The stored input data state drives the display control module 700 in a format corresponding to the two display files, and the display unit (CRT) 1000 displays the corresponding format.

(Trace Conditions) FIG. 2 is a diagram showing trace conditions, and an overview thereof will be described first. As explained in FIG. 1, the input data of each channel is sampled at designated clock transitions for each assigned label.

The trace conditions determine the qualifying conditions of which sampled data should be stored for display and which sampled data should be counted for counting measurements. The qualifying conditions include a cross-qualifying condition in which data is written in memory in synchronization with a clock when a desired condition is met (for example, when a digital input signal or other external signal reaches a predetermined state), and a desired data pattern. There are boot qualification conditions such as writing only the following information into memory. In addition to the above-mentioned trace conditions, there are conditions specifying selective tracing and counting measurement. The assigned input data is defined as any combination of 1.0 and X (irrelevant) when the base is binary. Also, the base numbers are octal and decimal.

In the case of hexadecimal, it is defined by alphanumeric characters and X.

In response to input data satisfying a predetermined state sequence, the trace position is changed from the beginning (5TART) to the center (5TART).
CENTER) or the end (t!ND) can be selected, allowing selective tracing. State sequence conditions for up to seven states can be set, and intermediate states not included in the sequence conditions are ignored.

The simplest state sequence is a single state condition.

Branch, loop, or nested node-type states can also be directly analyzed by properly defining the state sequence. Additionally, each state condition in the state sequence must be satisfied from 1 to 65 times before the state condition is satisfied.
It can be specified to occur 536 times. This makes it possible to analyze the nth path of a loop that starts with a predetermined state condition. Clock delays are implemented by defining the nth occurrence of either state.

If the predetermined restart state condition occurs before the state sequence is satisfied, the trace logic repeats the sequence of operations again until the state sequence is satisfied. If a condition is set to restart when all states other than those defined in the state sequence occur, no states must exist between the defined state sequences. If another start occurs between the defined states, it will be restarted.

Next, trace conditions will be explained in detail using FIG. 2. In the figure, labels, base numbers, etc. correspond to those in FIG. In Figure 2, the state sequence conditions are: 03CF twice, 03IE2 three times, 0OHI to the label.
This shows a case where 03E3 is triggered and traced based on the fact that 03E3 occurs once after 03E3 occurs in the same order. Note that since the labels D and F are χ, they are not related to the sequence conditions. Further, the trace position is set at the beginning (START). This setting is the FI [! LD5H
This is done using the LECT key. When the sequence conditions of FIG. 2 are set, writing stops after 64 data states are written into the storage device that do not meet the qualifying conditions that occur after 03E3 to the label.

In this case, 03E3 and its corresponding label D.

The data of F etc. are displayed at the first position, and the stored states written after that are displayed subsequently.

If the trace position is set to the center (CENTER), and if the data status positions before and after 03E3 are set to the end (END), writing will stop when 03E3 occurs, and the data written before that will stop. The selected data state is displayed. Here, the qualification condition is a boot qualification condition that stores only 03E1 for label 8, and a boot qualification condition that stores only 03E1 for labels D and F. This is the Chronoku qualification condition of storing synchronized data. Up to seven stays can be specified to be steered. By selectively storing only the desired sample stay L-, unnecessary states can be omitted, reducing the memory capacity (64 in this example).
It is possible to pseudo-enlarge lines (a possible).

Also, it can be set to store the specified state every time the specified state is regenerated N times (OCCUR
). Furthermore, the time between the stored 64 states,
The number of state occurrences is measured and displayed in one of two formats:

Absolute format, , , , ) Count value relative format from race position 83800. Hand value time counting from previous stored states is done by counting the number of internal clock occurrences between successively stored states and display is done in seconds. In addition, the state count counts the number of states that occur between sequentially stored states.

The counting is done based on the number of clocks. In addition,
In the case shown, the restart condition (RESTART) is 0.
3E4, and if 03E4 occurs during the sequence, the trigger condition is restarted starting with the detection of 03CF.

(Internal storage of measurements) Complete measurements of 64 sampled states are stored internally and the measurements satisfy the display format, trace conditions and state conditions that define the display specification and state sequence. Contains sample states.

The most recent measurements are stored and become stored measurements for later analysis.

1~ In race comparison mode, the results of previously stored traces are compared with the latest measurements and available. The above l/race comparison will be described in more detail below.

(Display specification) There are three types of display formats: list display, graph display, and comparison mode display.

FIG. 3 is a diagram showing a list display of stored data states. In the figure, the list is shown in the order of occurrence of stored cheese 1.

20 states (1 state per line) are CR at the same time
It appears on the second display screen. By ROLL gee which will be mentioned later,
64 stored states can be scanned. For each line, the line number, the state stored in the alpha vent class according to their cardinality and the state old value are displayed on the assigned label, and the time count value is displayed if selected.

In this case, it is indicated that temporary data such as 03E3.03E4.03B1 is stored at label 8 due to the setting of the l/race condition.

FIG. 4 is a diagram showing a graphical representation of stored data states. In FIG. 4, the graph shows the relationship between the size of data at a designated label (vertical axis) and the storage locations of all 64 stored states (horizontal axis). Each state gives a vertical position corresponding to its binary magnitude and increases in horizontal position according to the order in which successive states occur. The label that should be displayed on the graph is
It is selected by specifying the graph label (GRAPIIED LABEL). FIG. 4 shows a case where label F is selected. The vertical axis scaling setting is
The upper limit (UPPERLIMIT) and lower limit (
It is controlled by specifying LOFERLI (formerly T).

These upper and lower limits are specified as relatively or dynamically changed according to logarithmic automatic range control.

Therefore, part of the graph can be easily enlarged to full scale display. 20 points corresponding to the lines observed in the list display shine brightly. This brightness-enhanced part is also RO
In response to control by the LL key, their corresponding absolute values are read in the list display.

FIG. 5 is a diagram showing a display list in comparison mode. In the figure, the trace comparison tabulates and lists the differences between the data in the "latest measurements" and the data in the "stored measurements."

This listing is done in the same format as in list display. The two measurement results are output and displayed as an exclusive OR. In other words, if the bits are the same, O,
If they are not equal, they are displayed as 1. “03” in octal is “ooo” in binary.

11", and the two focuses on the right indicate that the two measurements are different. Trace comparison also exposes the "compared traces" mode, in which the latest measurement value and the stored measurement value are compared. Rerun the measurements until 5TOP- is equal or no longer equal.
Alternatively, it is performed according to the 5TOP≠ key.

(Trace mode) There are three types of trace modes. "l-Race" causes a single current measurement to be performed. “Continuous trace” continuously repeats the execution of the latest measurement. A "compared trace" is a repeated execution of the latest measurement until the desired comparison value is obtained for the stored measurements.

(Clock/enable output and trigger output) The trigger output also works as a trigger pulse for driving external measuring instruments such as an oscilloscope. 50 for each trace location found
A trigger pulse of nsec is generated. The clock enable output is useful for gating the clock or interrupting the device under test. A high level signal indicates that the instrument is searching for a trace location. The trigger output remains a high level signal until the desired trace position is reached or the stop key is pressed. When "Display format specification" is displayed, clock enable output and trigger output are not output.

(Specification of Keyboard and Conditions) FIG. 6 shows an input keyboard. In the figure, the keys are divided into four blocks according to function.

Measurement display section (CURRENT MEASUREMENT)
DISPLAY).

Entry Department (IENTRY), Editorial Department (EDIT)
and four blocks of the execution section (EXECUTE 5TORE).

When the power is turned on, an arbitrary display is displayed, and then 1 is automatically displayed.
A list is displayed in hex format.

By operating the ROLL DISPLAY key,
Any part of the 64 stored states can be displayed. For example, the number of display states on one screen is 20.

By pressing the FORMAT 5Pf ICIFICATION key, the display format setting screen shown in Figure 1 will be displayed.
Displayed on RT. The cursor on CIIT is moved by operating the CIJR3OR key in the editorial department, and the inverted video field (first
The boxed area in FIGS. 4 to 4) flashes to indicate selectable entry fields. First, the cursor is located at the entry field corresponding to the clock transition (CLO(J5LOPE), and (→-) is displayed in the entry field, and the entry field flashes. Press the FIELD 5 ELECT key repeatedly. Accordingly, in the entry field there is a (+)
, (-) are displayed alternately. Clock transitions are set by indicating the desired clock transitions. 1st
The figure shows the case where the clock transition is set to (→·).

Next, press the down arrow CIJR3OR key once.
The cursor moves to the left end of the square corresponding to box 4 in FIG. Desired labeling is done by operating alpha keys 8 to F in the entry section. Next, pressing the down arrow CUR3OR key moves the cursor into the square corresponding to the logical loss to the label. FIIE
By operating the DSELECT key, the logical polarity changes (→-)
or =). Next, by operating the down arrow key, the cursor is moved within the square corresponding to the base number to the label. By repeatedly pressing the FIELD 5lliLECT key, IIEX, BIN, OCT,
They are displayed repeatedly in the order of DEC(7). By displaying the desired radix, the radix is set. FIG. 1 shows a case where the base numbers of labels A and D are set to hexadecimal, and the base number of label F is set to binary.

The trace conditions can be edited by operating the TRACE 5PIEC4FICATION key and selecting the trace condition display shown in FIG. This editing is accomplished in the same manner as the display format designation described above is edited. For example, at the label ^ a single or sequence trigger condition, an indication of trace position, a restart condition,
The data to be stored is specified.

(Detailed Description) FIG. 7 is a block diagram of the logic analyzer of the present invention. The microprocessor module 800 includes a printer 1300 . Self-test probe drive module 12
00. A keyboard 1100 is connected. Further, a display drive module 9001, a display control module 700, and a capture system section 250 are connected to the microprocessor module 800 via a communication bus 600.

Acquisition system section 250 includes measurement control module 400. Index module 300. The state recognition module 20 is composed of a state recognition module 200.
0 is connected to a data probe 100. By operating the keyboard 1100, the display format, qualifying conditions, trigger conditions, etc. are set. The data probe 100 is divided into four (8-bit) data points and a clock board. The threshold of each bond is set to a TTL logic threshold or a dark value in the range of -10v to -10v. The data probe 100 converts and outputs the large catstate into a logic level signal related to the dark value.

Clock signals and logic level input data states from data probe 100 are input to state recognition module 200 . The state recognition module 200 samples and latches the logic level input data state 1 in response to selected clock transitions, and delivers the sampled data state to the high speed acquisition system HAS 500. . The indexing module 300 accesses the sampled data stage 1 via the acquisition system bus 500 and performs the set conditions (
(trigger condition, qualification condition, sequence condition, etc.) and the sampled data state, and trace position 9
Outputs signals determining selective store events, stay-count events, etc. Measurement control module 400 also accesses sampled data states via fast acquisition system path 500 and index module 30 .
state count value 5 time count value in response to the signal from 0;
data storage) - etc. The stored data state is transmitted to the display control module 700 via the communication path 600.
, is sent to the microprocessor module 800 and the display driving module 900 in a set format (j?
Displayed on T 1000. Printer 13 if desired
00 is printed.

FIG. 8 is a diagram showing the address contents of the memory in the device of the present invention.

Addresses 0 to F07 are RA of the display drive module 900
Gate memory, addresses 1000 to 1110 are printer 1300, keyboard 1100. Memory of self-test probe drive module 1200, address 1800 ~ IF
The FF address is the memory of the measurement control module 400, 400
Addresses 0 to 47FI' are ROM memory in the microprocessor module 800, addresses 6000 to 7FI
The 'I' address is also a ROM memory in the microprocessor module 800.

7 and 8, the communication bus 600
Sampled data states, etc. stored in the memory of the state counting measurement and measurement control module 400 are accessed by addresses between 00 and IFFF.

FIG. 9 is a diagram showing the relationship between physical addresses and logical addresses in the memory of FIG. 8.

FIG. 10 is a detailed block diagram of the acquisition system section 250 in FIG. In FIG. 10, data states converted to logic levels by data probe 100 are input to launch circuit 230 via probe interface 210 in state recognition module 200. In FIG. Sample clock generator 220 generates a sample clock in response to selected clock transitions. U・7 times l
? The 8230 samples and registers the data state in response to the sample clock. The sampled data states are captured by the indexing module 300 via the acquisition system bus 500.
The sampled states of acquisition system bus 500 are first compared to qualifying state conditions stored in multiple pattern recognition unit 315, thereby detecting trace locations. The digital pattern trigger circuit included in the multiple pattern recognition unit 315 includes:
For example, there is one described in Japanese Patent Publication No. 57-19464 "Trigger Signal Generation Circuit".

FIG. 11 shows the multiple pattern recognition unit 315 of FIG.
FIG. 2 is a more detailed block diagram of FIG. In the figure, the multiple pattern recognition unit 315 is equipped with a plurality of 4-bit memories to detect up to eight qualifier state conditions, and each qualifier state 1-condition is defined by a binary number of LO, Determined by format.

Referring again to FIG. The pattern selector 325 is
One of the eight AME line outputs from multiple pattern recognition unit 315 is selected and the selected output is provided to state counter 345. Counter 345 calculates the number of occurrences of the selected qualifying state condition, and in response to the number of occurrences of the selected qualifying state condition reaching a certain number, sequence logic circuit 35
0 and generates an output signal to high speed control unit 460. In response to the output signal, the sequence logic circuit 350 outputs an instruction signal to the pattern selector 325 to select the next state. Pattern selector 325 selects the next state in response to the instruction signal, and counter 345
calculates the qualifier state condition a certain number of times,
High speed control unit 460 and sequence logic circuit 35
Outputs a signal to 0. Therefore, the state set as the qualifier state condition is stored in the data memory 410. The states or all states that are stored in the counting memory 420 and satisfy the qualification conditions in the upper right corner of the multi-pattern recognition unit are stored in the remaining locations of the storage device. The above operation is performed until the sequence condition set in the sequence logic circuit 350 is satisfied. If the sequence condition is set by six states, repeat until the first state occurs. When the restart condition 1. occurs during the sequence, the restart operation is controlled by the restart unit 7+.310.

FIG. 12 is a block diagram showing a simplified sequence trigger circuit. In the figure, multiple pattern recognition unit 316 has the functions of multiple pattern recognition unit 315 and pattern selector 325. Sequence logic circuit 351 has the functionality of sequence logic circuit 350, except that a final trigger is output upon completion of a state sequence. Further, 354 is a programming means. Multiple pattern recognition Uniso) 31
Another way to achieve 6 is to provide 3 selector bits, which are the most significant bits in the address.
Thereby, when the comparator compares the ordinal state conditions of the state sequence, the comparison is made according to each segment of the memory.

Referring again to FIG. A trace selector 320 controls selective l-race. l-race counter 340
counts and detects the occurrence of the fourth state, and outputs a trace event flag corresponding to 1 to the trigger signal.

The restart unit 71-310 causes the sequence logic circuit 350 to restart the increasing operation of the STAY 1-sequence following detection of a selected restart state condition. Restart stay 1-310 is disabled by sequence logic 350 for the data state corresponding to break-even. The logic circuit 350 restarts the restart stage l- in all the stages.
If the conditions are set so that

The stay-count unit 71, 305 strobes a counter in the measurement control module 400 upon detection of each selected state condition to be counted.

FIG. 13 shows the measurement control module 40 shown in FIG.
0 is a more detailed block diagram of FIG. The event flags from FIG. 10 are input to the high speed control unit 71, 460 and it is determined which sampled states in the acquisition system bus 500 are to be stored. In response to the event flag, the high-speed control unit 460 stores a sample train in the data memory 10 and the amires position of the counting memory 420 corresponding to the set i-race position.
1. Stop writing with the state count value and time count value stored. Data memory 410. Counting memory 4
The twenty addresses are specified by address multiplexer 462. Also, data memory 410. Counting memory 4
The data in the communication lotus 20 is output to the communication lotus 600 via the lotus buffer 470. Data memory 410 includes spare memory, and in the compare mode, previously stored data in data memory 410 is compared with the most recently stored data by high speed control UNISO 1-460. The comparison is based on the exclusive logic of both data. This is done by taking the . The comparison results are input to display 1000 via communication bus 600. The comparison results shown in FIG. 5 show that both data are identical. When a stop condition is set, if the previously stored data and the latest stored data are different, writing to the data memory 410 is stopped.

FIG. 14 shows the data format of data memory 410 shown in FIG. In the figure, the sample 1-condition that causes a break event is at position 1~(N~1
) are stored sequentially. Upon detection of the "N-1" event flag, the sample to steal one condition is written to the remaining memory locations sequentially, so that when the memory is full, it is written over the oldest data. The memory trace location address, including the state that caused the final trigger, is stored in a register, and the sampled state is written to the appropriate number of remaining storage locations. For example, if the trace is defined as "end" by detecting the trace position, the sample I-" state will not be written after the trace position. The order in which stored data is generated is determined by the communication bus shown in FIG. Easily reconstructed by trace position atresno recovery appearing at 6001. Synchronizer 4 with count selection function
50 controls a measurement counter 430, the contents of which are stored in the count memory 420 by updating the memory address. The low speed interface capability provided by the low speed control unit 480 allows the high speed control unit 460 to select and latch data for the program interface and communication hub 600 interface.

Strobe generator 440 shown in FIGS. 10 and 13
Generates a sequence of scopes. When the strobe is introduced into a series of de-clutches (not shown) and timing logic 128 (not shown), it causes its functions to be performed in order. In reality, a large number of samples are in various stages being processed simultaneously at one time.

Definition of Active Channels Referring again to FIG. The symbol "!" appears under the assigned input data channel in the display format specification. Approximately once every 1 ms, the sampled state is compared to the "last sample" bathopore. The state detects any bit change by exclusive OR. The result is then ANDed with the Sanfurt state input to the active buffer and the "last sample" buffer. After 100 samples the active buffer is sampled for display purposes. The absence of "!" here indicates that the bond clip has left l1Il&, and also indicates that the channel is inconvenient in some other way. It is therefore very convenient to use.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the designation of the display format of the logic analyzer of the present invention. FIG. 2 is a diagram showing trace condition display of the logic analyzer of the present invention. FIG. 3 is a diagram showing a list display of stored data states of the logic analyzer of the present invention. FIG. 4 is a diagram showing a graph display of the stored take state of this QUJJ noc+ thick analyzer. FIG. 5 is a diagram showing a display list in comparison mode of the logic analyzer of the present invention. Figure 6 shows the logic of the present invention.
The figure which shows the input keyboard of an analyzer. FIG. 7 is a block diagram of the logic analyzer of the present invention. FIG. 8 is a diagram showing the contents of the memory of the logic analyzer of the present invention. 9th
The figure is a diagram showing the address relationship of the logic analyzer of the present invention. FIG. 10 is a detailed block diagram of the acquisition system portion 250 of FIG. 7. FIG. 11 shows the multiple pattern recognition unit 315 of FIG.
A more detailed block diagram. FIG. 12 is a block diagram of the sequence trigger circuit of the logic analyzer of the present invention. FIG. 13 is a more detailed block diagram of the measurement control module 400 of FIG. FIG. 14 is a diagram showing the data format of data memory 410 shown in FIG. 10. FIG. 15 is a diagram showing a label format file of the logic analyzer of the present invention. FIG. 16 is a diagram showing the flow of the display formatting logic operation of the logic analyzer of the present invention. 100: data probe, 200 state recognition module, 300: index module, 400: measurement control module, 250: acquisition system section. 700: Display control module, 800: Microprocessor module, 900: Display drive module. 1ooo: CRT, 1too: Keeper l package 120
0: Self test (probe drive module, 130
0:Printer Applicant Yokogawa Heuret Paso Card Co., Ltd. Agent Patent Attorney Tsugu Hasegawa Male 1: 1 Continued from page 10 Inventor Gorton ny Greermenley
Rev0 Inventor: Steep Neesi Ameeno-Don Inventor: F. Duncan Terry 1615 Cura Place, Colorado Springs, Colorado, United States 3605 Pateiringen, Colorado Springs, Colorado, United States Apartment 20 2760 Amepen Code Drive, Meridian, Idaho, United States

Claims (1)

[Claims] An input means for inputting a plurality of digital signals, a storage means for storing the digital signals, and a display for displaying points related to values of the digital signals stored in the storage means and addresses of the storage means on rectangular coordinates. A logic analyzer comprising means.