JPS6335416Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a logic analyzer, and more particularly to a display setting section of a logic analyzer. Traditionally, logic analyzers capture and store digital input signals and display them in a preset format. In order to set various display formats, a large number of input keys are required, and the setting operation is also extremely complicated.

The present invention was developed in view of the above-mentioned drawbacks, and an object of the present invention is to provide a logic analyzer that can set various display formats through simple operations.

The present invention will be explained below using examples.

(Designation of display format) For example, 32 channels of digital input data are distributed to predetermined parameters and the data is formatted.
FIG. 1 is a diagram showing the designation of the display format of the logic analyzer of the present invention, which is displayed on a CRT. Data of each adjacent channel is assigned to one of six labels (LABEL) A to F.
Channel data assigned to the same label forms a group and behaves as a single parameter. In FIG. 1, the rectangular areas indicate fields that can be selectively input. In Figure 1, the 16 bits of the address bus, which is the channel for PODs 3 and 4, are labeled A, and the 16 bits for POD 2 are labeled A.
Eight bits of the data bus, which is the channel of , are assigned to label D. Also, 1 bit of pot 1 is assigned to label F, and the remaining 7 bits are not assigned (represented by symbol X). Other specifications and data manipulations are performed based on the label. In the figure, the logical polarities of labels A, D, and F are positive (+).
A case in which the logic polarity is positive is determined to be logic 1. NUMERICAL BASE
are defined in hexadecimal (HEX), hexadecimal, and binary (BIN) respectively. The base number can also be defined in octal (OCT) or decimal (DEC). Also, the positive or negative clock transition (CLOCK SLOPE) when the input data is sampled.
is shown. In FIG. 1, the case where the clock transition is positive is shown. That is, it is indicated by (+).

FIG. 16 is a diagram showing the flow of logical operations for display formation in the logic analyzer of the present invention, and FIG. 15 is a diagram showing a label display format file of the logic analyzer of the present invention. 16th
In the figure, when signals representing label assignment, radix, etc. are input to microprocessor 800 via keyboard 1100, a label display format file as shown in detail in FIG. 15 is constructed. It contains parameters that specify the display format. Furthermore, the concatenation definition is used to process stored or written data states (stored data states) in the ASCII display data file and the graph display data file that are connected in the order of A, B, and C. Meanwhile, input data states captured by capture system 250 are stored in storage devices 410 and 420. The stored input data state is transmitted to the display control module 700 in a format corresponding to the two display files.
is driven, and a corresponding format is displayed on the display unit (CRT) 1000.

(Trace Conditions) FIG. 2 is a diagram showing trace conditions, and an overview thereof will be described first. As explained in FIG. 1, the input data for each channel is sampled at specified clock transitions for each assigned label. The trace conditions determine the qualification conditions for which sampled data should be stored for display and also determine which sampled data should be counted for enumeration measurements. Ru. The qualification conditions include a clock qualification condition in which data is written in memory in synchronization with a clock when a desired condition is met (for example, when a digital input signal or other external signal reaches a predetermined state), and the desired data. There are data qualification conditions such as writing only the pattern into memory. In addition to the above-mentioned trace conditions, there are conditions specifying selective tracing and counting measurement. The assigned input data is defined as any combination of 1, 0, and X (irrelevant) when the base is binary. Also, the base is octal, 10
In case of base or hexadecimal, it is defined by alphanumeric characters and X.

Selective tracing is possible because the trace position can be selected to be START, CENTER, or END in response to input data that satisfies a predetermined state sequence. State sequence conditions for up to seven states can be set, and intermediate states not included in the sequence conditions are ignored.

The simplest state sequence is a single state condition.

Branch, loop, or nested states can also be directly analyzed by properly defining the state sequence. Further, each state condition in the state sequence can be specified to occur from 1 to 65536 times before the state condition is satisfied. This makes it possible to analyze the nth path of a loop that starts with a predetermined state condition. The clock delay is n for either state.
This is achieved by defining the second occurrence state.

If the predetermined restart state condition occurs before the state sequence is satisfied, the trace logic repeats the sequence of operations again until the state sequence is satisfied. If a condition is set to restart when all states other than those defined in the state sequence occur, no states must exist between the defined state sequences. If another start occurs between the defined states, it will be restarted.

Next, trace conditions will be explained in detail using FIG. 2. In the figure, labels, base numbers, etc. correspond to those in FIG. In Figure 2, the state sequence conditions are that the state with label A is 03CF twice, 03E2
The case is shown in which the trace is triggered and traced based on the occurrence of 03E3 three times and one occurrence of 00E1, followed by one occurrence of 03E3. In addition, labels D and F are
Therefore, it is not related to sequence conditions. Further, the trace position is set to the beginning (START). This setting is made using the FIELD SELECT key shown in FIG. When the sequence conditions of FIG. 2 are set, writing stops after 64 data states including label A 03E3 and satisfying the qualifying conditions that have occurred since then have been written into the storage device. In this case, data such as 03E3 and its corresponding labels D and F are displayed at the first position, and the stored states written after that are displayed subsequently. If the trace position is set to the center (CENTER), the data states before and after are stored around 03E3, and then
Writing stops. End trace position (END)
If set to , writing stops when 03E3 occurs, and the previously written data state is displayed. Here, the qualification condition is a data qualification condition that stores only 03E1 for label A, and a data qualification condition for storing only 03E1 for labels D and F.
This is a clock qualification condition that stores data synchronized with the clock when the clock becomes 03E1. You can specify up to 7 states to be stored. By selectively storing only the desired sample states, unnecessary states can be omitted, reducing the memory capacity (64 in this example).
rows can be memorized) can be enlarged figuratively. Further, the specified state can be set to be stored every time the specified state occurs N times (OCCUR). Furthermore, the time between the 64 stored states and the number of state occurrences are measured, and the next 2 states are measured.
Displayed by one of the formats.

Absolute format: Count from trace position Relative format: Count from previous stored state Time counting is done and displayed by counting the number of internal clock occurrences between sequentially stored states. is done in seconds. Also, state counting counts the number of states that occur between sequentially stored states. The counting is done on the basis of the number of clocks. Note that the restart condition (RESTART) in the illustrated case is 03E4, and if 03E4 occurs during the sequence, the trigger condition is restarted and starts from the detection of 03CF.

(Internal storage of measurements) Complete measurements of 64 sampled states are stored internally, and the measurements satisfy the display format, trace conditions, and state conditions that define the display specification and state sequence. Contains sampled states. The most recent measurements are stored and become stored measurements for later analysis. In trace comparison mode, the results of previously stored traces are compared with the latest measurements and available. Note that the trace comparison will be described in more detail below.

(Display specification) There are three types of display formats: list display, graph display, and comparison mode display.

FIG. 3 is a diagram showing a list display of stored data states. In the figure, the list is a listing of the stored states in the order in which they occur.
20 states (1 state per line) simultaneously
Appears on the CRT display screen. The ROLL key, which will be described later, allows scanning of 64 stored states.
Each line displays the line number, the states and state count values stored in alphabetical order on the assigned label according to their radix, and, if selected, the time count value. In this case, label A indicates that data in states such as 03E3, 03E4, 03E1, etc. is stored due to the setting of trace conditions.

FIG. 4 is a diagram showing a graphical representation of stored data states. In Figure 4, the graph is
The size of the data at the specified label (vertical axis) and
Shows the relationship between all 64 stored states and storage locations (horizontal axis). Depending on each state, the second
A vertical position is given corresponding to the size of the digit, and a horizontal position increases according to the order in which successive states occur. The label to be graphed is selected by specifying GRAPHED LABEL. FIG. 4 shows a case where label F is selected. The vertical axis scaling setting is controlled by specifying the upper limit (UPPER LIMIT) and lower limit (LOWER LIMIT) on the vertical axis. These upper and lower limits are specified as relatively or dynamically changed according to logarithmic automatic range control. Therefore, part of the graph can be easily enlarged to full scale display. 20 points corresponding to the lines observed in the list display will shine brightly.
This brightness-enhanced portion is also responsive to control by the ROLL key, and their corresponding absolute values are read in the list display.

FIG. 5 is a diagram showing a display list in comparison mode. In the figure, the trace comparison is the “latest measured value”
Table and list the differences between the data in and the data in "stored measurements". This listing is performed in the same format as in list display. The two measurement results are output and displayed as an exclusive OR. That is, if the bits are the same, they are displayed as 0, and if they are not equal, they are displayed as 1. Octal "03" corresponds to binary "000011", and the two right bits indicate the difference in the two measurements. Trace comparison also exposes a "compared trace" mode in which measurements are re-performed until the most recent measurement and the stored measurement are equal or no longer equal.
This is done according to the STOP≠ key.

(Trace mode) There are three types of trace modes. "trace"
causes a single most recent measurement to be performed. “Continuous trace” continuously repeats the execution of the latest measurement.
A "compared trace" is a repeated execution of the latest measurement until the desired comparison value is obtained for the stored measurements.

(Clock enable output and trigger output) The trigger output also works as a trigger pulse for driving external measuring instruments such as an oscilloscope. A 50nsec. trigger pulse is generated every time a trace position is found. The clock enable output is useful for gating a clock or interrupting the device under test. Due to the high level signal,
It is shown that the measuring instrument is performing a trace position search operation. The trigger output remains a high level signal until the trace position is found or the stop key is pressed. When “Display format specification” is displayed, clock enable output and trigger output are not output.

(Specification of Keyboard and Conditions) FIG. 6 shows an input keyboard. In the figure,
The keys are divided into four blocks according to function.
Measurement display section (CURRENT MEASUREMENT)
DISPLAY), entry section (ENTRY), editing section (EDIT), and execution section (EXECUTE STORE)
There are 4 blocks. When the power is turned on, an arbitrary display is made, and then a hexadecimal format list is automatically displayed.

By operating the ROLL DISPLAY key,
Any part of the 64 stored states can be displayed. For example, the number of display states on one screen is 20.
It is. By pressing the FORMAT SPECIFICATION key, the display format setting screen shown in FIG. 1 is displayed on the CRT. The cursor on the CRT is moved by operating the CURSOR key in the editorial department.
Inverted video field on the display surface corresponding to the cursor position (boxed area in Figures 1 to 4)
will flash to indicate the selectable entre field. Initially, the cursor is positioned at the entry field corresponding to the clock transition (CLOCK SLOPE), a (+) is displayed in the entry field, and the entry field blinks. By repeatedly pressing the FIELD SELECT key, the entries in the entry field are
(+) and (-) are displayed alternately. Clock transitions are set by displaying the desired clock transitions. FIG. 1 shows the case where the clock transition is set to (+). Then the down arrow
Press the CURSOR key once, and the pot 4 in Figure 1 will be displayed.
The cursor moves to the left edge of the square corresponding to . Desired labeling is done by operating the alphabet keys A to F in the entry section. Next, pressing the down arrow CURSOR key moves the cursor into the square corresponding to the logical polarity of label A. The logical polarity is set to (+) or (-) by operating the FIED SELECT key. Next, use the down arrow key to move the cursor to label A.
Move into the square corresponding to the base of . FIELD
By repeatedly pressing the SELECT key,
HEX, BIN, OCT, DEC are displayed repeatedly in this order. By displaying the desired radix, the radix is set. In FIG. 1, the radix of labels A and D is set to hexadecimal, and the radix of label F is set to binary.

Trace conditions can be edited by operating the TRACE SPECIFICATION key and selecting the trace condition display shown in FIG. This editing is accomplished in the same manner as the display format designation described above is edited. For example, label A specifies a single or sequence trigger condition, a trace position, a restart condition, data to be stored, and the like.

(Detailed Description) FIG. 7 is a block diagram of the logic analyzer of the present invention. microprocessor module 8
00 includes a printer 1300, a self-test probe drive module 1200, and a keyboard 1100.
is connected. Further, the microprocessor module 800 is connected to a display drive module 900 and a display control module 700 via a communication bus 600.
and a capture system 250 are connected. Acquisition system section 250 includes measurement control module 40
0, an index module 300, and a state recognition module 200, and the state recognition module 200 includes a data probe 100.
is connected. By operating the keyboard 1100, the display format, qualifying conditions, trigger conditions, etc. are set. Data probe 100 is divided into four 8-bit data pods and a clock pod. The threshold for each pot is set to a TTL logic threshold or a threshold within the range of +10v to -10v. The data probe 100 converts and outputs an input state into a logic level signal related to the threshold value.

The clock signal and logic level input data states from data probe 100 are input to state recognition module 200. State recognition module 200 samples and latches logic level input data states in response to selected clock transitions and provides high speed capture system bus 50.
Sends a data state sampled to 0 (sampled data state). The index module 300 accesses the sampled data state via the acquisition system bus 500, compares the sampled data state with set conditions (trigger condition, qualifying condition, sequence condition, etc.), and selects a trace position. Store events, state counts. Outputs a signal that determines an event, etc. Measurement control module 400 also accesses sampled data states via high speed acquisition system bus 500 and index module 30.
In response to the signal from 0, the state count value, time count value, data state, etc. are stored. The stored data state is transmitted to the display control module 700, the microprocessor module 800, and the display drive module 900 via the communication bus 600.
and displayed on the CRT 1000 in the set format. It is printed on the printer 1300 as desired.

FIG. 8 is a diagram showing the contents of memory addresses in the device of the present invention.

Addresses 0 to F07 are display drive module 900
RAM memory, addresses 100 to 1110 are memory of the printer 1300, keyboard 1100, self-test probe drive module 1200, addresses 1800 to 1FFF are memory of the measurement control module 400, addresses 4000 to 47FF are memory of the microprocessor module 800. ROM memory, 6000
Addresses from address to 7FFF are also ROM memories in the microprocessor module 800.

In FIGS. 7 and 8, the communication bus 600
The sampled data states etc. stored in the memory of the state counting measurement and measurement control module 400 are accessed by addresses between 1800 and 1FFF.

FIG. 9 is a diagram showing the relationship between physical addresses and logical addresses in the memory of FIG. 8.

FIG. 10 shows the capture system section 25 in FIG.
0 is a detailed block diagram of 0. In Figure 10,
The data state converted to a logic level by the data probe 100 is transferred to the state recognition module 20.
0 to the latch circuit 230 via the probe interface 210 in the probe interface 210 . Sample clock generator 220 generates a sample clock in response to selected clock transitions. Latch circuit 2
30 samples and latches the data state in response to the sample clock. Sampled data states are input to index module 300 and measurement control module 400 via acquisition system bus 500. Indexing module 300 first compares the sampled state of acquisition system bus 500 to qualified state conditions stored in multiple pattern recognition unit 315, thereby detecting trace locations. The multiple pattern recognition unit 3
An example of the digital pattern trigger circuit included in No. 15 is the one described in Japanese Patent Publication No. 57-19464 entitled "Trigger Signal Generation Circuit".

FIG. 11 is a more detailed block diagram of the multiple pattern recognition unit 315 of FIG. In the figure, the multiple pattern recognition unit 315 includes a plurality of 4-bit memories to detect up to eight qualifying state conditions, where each qualifying state condition has a binary format of 1, 0, and X inputs. It is determined by

Referring again to FIG. pattern selector 3
25 is the signal from the multiple pattern recognition unit 315.
Select one of the eight AME line outputs and provide the selected output to state counter 345.
Counter 345 calculates the number of occurrences of the selected qualifying state condition and, in response to the number of occurrences of the selected qualifying state condition reaching a certain number, sequence logic circuit 35
0 and output signals to high speed control unit 460. In response to the output signal, the sequence logic circuit 350 outputs an instruction signal to the pattern selector 325 to select the next state. The pattern selector 325 selects the next state in response to the instruction signal, the counter 345 calculates the qualifying state condition a specified number of times, and the high speed control unit 460 and the sequence logic circuit 350
Outputs a signal to. Therefore, the state set as the qualification condition is:
Each time a specified number of occurrences occurs, the states are stored in the data memory 410 and the counting memory 420, and the states or all states that satisfy the qualification conditions of the multiple pattern recognition unit are stored in the remaining locations of the storage device. The above operation is performed by the sequence logic circuit 350.
The process continues until the sequence conditions set in . If the sequence condition is set by M states, repeat until the M-1th state occurs. When a restart condition state occurs during the sequence, the restart unit 31
The restart operation is controlled by 0.

FIG. 12 is a block diagram showing a simplified sequence trigger circuit. In the figure, multiple pattern recognition unit 316 has the functions of multiple pattern recognition unit 315 and pattern selector 325. Sequence logic circuit 351
has the functionality of the sequence logic circuit 350, except that the final trigger is output upon completion of the state sequence. Also, 354
is a program means. Another way to implement multiple pattern recognition unit 316 is to have three selector bits, the most significant bits in the address, so that when the comparator compares the sequential state conditions of the state sequence, each segment of memory The comparison is made according to.

Referring again to FIG. Trace selector 3
20 controls selective tracing. The trace counter 340 counts and detects the occurrence of the Mth state, and outputs a trace event flag corresponding to a trigger signal.

The restart unit 310 causes the sequence logic circuit 350 to restart the satisfying operation of the state sequence following detection of a selected restart state condition. Restart unit 310 is disabled by sequence logic 350 for data states corresponding to a break event. When conditions are set by the logic circuit 350 so that the restart state occurs in all the stages, the state sequence is satisfied when there is no unspecified intermediate state. State counting unit 305 strobes a counter in measurement control module 400 upon detection of each selected state condition to be counted.

FIG. 13 is a more detailed block diagram of the measurement control module 400 shown in FIG. 1st
0 and 13, event flags from index module 300 are input to high speed control unit 460 and it is determined which sampled states in acquisition system bus 500 are to be stored. High speed control unit 46
0 stops writing in response to an event flag with the sampled state, state count value, and time count value stored at the address location of the data memory 410 and count memory 420 corresponding to the set trace position. data memory 41
0, the address of counting memory 420 is specified by address multiplexer 462. Further, the data in the data memory 410 and the counting memory 420 are outputted to the communication bus 600 via the bus buffer 470. Data memory 410 includes spare memory, and in the compare mode, previously stored data in data memory 410 is compared with the most recently stored data by high speed control unit 460. Comparison is exclusive logic of both data
This is done by taking an OR. The comparison results are input to display 1000 via communication bus 600. The comparison results shown in FIG. 5 show that both data are identical. When a stop condition is set, if the previously stored data and the latest stored data are different, writing to the data memory 410 is stopped.

FIG. 14 shows the data memory 4 shown in FIG.
In the figure, the sampled states which cause a break event are stored in sequence from position 1 to (N to 1).
Upon detection of the event flag, the sampled state conditions are written sequentially to the remaining memory locations so that when the memory is full, the oldest data is written over. The address of the trace location in memory containing the state that caused the final trigger is stored in a register, and the sampled state is written to the appropriate numbered location among the remaining storage locations. For example, if on detection of the trace location the trace is defined to be "end", then
No sampled states are written after the trace location. The chronological order of the stored data is easily reconstructed by recovering the trace location address as it appears on the communication bus 600 shown in FIG. 9. Synchronizer 4 with count selection function
The counter 450 controls the measured value counter 430, the contents of which are updated in the count memory 4 by updating the memory address.
20. The low speed interface capability provided by the low speed control unit 480 allows
A high speed control unit 460 is programmable and can select and latch data for the communication bus 600 interface.

Strobe generator 440, shown in FIGS. 10 and 13, generates a sequence of strobes.
When the strobe is introduced into a series of data latches (not shown) and timing logic (not shown), it performs its functions in an orderly manner. In practice, a large number of sampled states are in various stages being processed simultaneously at one time.

Definition of Active Channel Referring again to Figure 1. The symbol "!" appears below an assigned input data channel in the display format specification. Approximately once every 1ms the sampled state is compared to the "last sample" buffer. The state detects any bit change by exclusive OR. And the result is
It is ANDed with the filled state inputs to the active buffer and the "last sample" buffer. After 100 samples the active buffer is sampled for display purposes. The absence of "!" here indicates that the potted clip has left, and also indicates that the channel is inconvenient in some other way. It is therefore very convenient to use.
As described above, according to the present invention, it is possible to provide a logic analyzer that can set various display formats with simple operations.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the designation of the display format of the logic analyzer of the present invention. FIG. 2 is a diagram showing trace condition display of the logic analyzer of the present invention. FIG. 3 is a diagram showing a list display of stored data states of the logic analyzer of the present invention. FIG. 4 is a diagram showing a graphical representation of the stored data state of the logic analyzer of the present invention. FIG. 5 is a diagram showing a display list in the comparison mode of the logic analyzer of the present invention. FIG. 6 is a diagram showing the input keyboard of the logic analyzer of the present invention. Figure 7 is a block diagram of the logic analyzer of the present invention. FIG. 8 is a diagram showing the contents of the memory of the logic analyzer of the present invention. FIG. 9 is a diagram showing the address relationship of the logic analyzer of the present invention. FIG. 10 is a detailed block diagram of the capture system section 250 of FIG. 1st
Figure 1 shows the multiple pattern recognition unit 31 in Figure 10.
A more detailed block diagram of 5. FIG. 12 is a block diagram of the sequence trigger circuit of the logic analyzer of the present invention. FIG. 13 is a more detailed block diagram of the measurement control module 400 of FIG. 10. FIG. 14 is a diagram showing the data format of data memory 410 shown in FIG. 10. FIG. 15 is a diagram showing a label format file of the logic analyzer of the present invention. 16th
The figure shows the flow of the display formatting logic operation of the logic analyzer of the present invention. 100: Data probe, 200: State recognition module, 300: Index module, 400: Measurement control module, 250: Acquisition system section, 700: Display control module, 80
0: Microprocessor module, 900: Display drive module, 1000: CRT, 110
0: Keyboard, 1200: Self-test probe drive module, 1300: Printer.

Claims (1)

[Claims for Utility Model Registration] A logic analyzer that stores a digital input signal based on a clock signal and displays the stored signal on a display according to conditions set by an input key, a signal output circuit that outputs a first signal for displaying an entry field, a symbol, and a cursor; and a signal output circuit that responds to an operation of a cursor key;
a first control circuit that controls the signal output circuit so that the cursor moves within the entry field; a storage device that stores a plurality of symbols corresponding to one input key; and the same input key. Each time you operate, the corresponding memorized symbol will be
and a second control circuit that controls the cursor to be displayed at a position corresponding to the cursor.