CA1151329A - Method of displaying logic signals for a logic signal measurement apparatus - Google Patents
Method of displaying logic signals for a logic signal measurement apparatusInfo
- Publication number
- CA1151329A CA1151329A CA000357589A CA357589A CA1151329A CA 1151329 A CA1151329 A CA 1151329A CA 000357589 A CA000357589 A CA 000357589A CA 357589 A CA357589 A CA 357589A CA 1151329 A CA1151329 A CA 1151329A
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- Canada
- Prior art keywords
- logic
- displaying
- logic signals
- display
- signals
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R13/00—Arrangements for displaying electric variables or waveforms
- G01R13/40—Arrangements for displaying electric variables or waveforms using modulation of a light beam otherwise than by mechanical displacement, e.g. by Kerr effect
- G01R13/404—Arrangements for displaying electric variables or waveforms using modulation of a light beam otherwise than by mechanical displacement, e.g. by Kerr effect for discontinuous display, i.e. display of discrete values
- G01R13/408—Two or three dimensional representation of measured values
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R13/00—Arrangements for displaying electric variables or waveforms
- G01R13/20—Cathode-ray oscilloscopes
- G01R13/22—Circuits therefor
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/32—Monitoring with visual or acoustical indication of the functioning of the machine
- G06F11/321—Display for diagnostics, e.g. diagnostic result display, self-test user interface
- G06F11/322—Display of waveforms, e.g. of logic analysers
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Human Computer Interaction (AREA)
- Quality & Reliability (AREA)
- General Engineering & Computer Science (AREA)
- Tests Of Electronic Circuits (AREA)
- Controls And Circuits For Display Device (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Testing, Inspecting, Measuring Of Stereoscopic Televisions And Televisions (AREA)
Abstract
Abstract:
The present invention relates to a method of displaying logic signals for a logic signal measurement apparatus. The method is comprised of the steps of storing input logic signals in a memory; displaying one part of the stored logic signals on a display; and displaying an indication information on the display simultaneously with the selected one part of the stored logic signals for indicating the relation of the selected one part in the entire stored logic signals.
The present invention relates to a method of displaying logic signals for a logic signal measurement apparatus. The method is comprised of the steps of storing input logic signals in a memory; displaying one part of the stored logic signals on a display; and displaying an indication information on the display simultaneously with the selected one part of the stored logic signals for indicating the relation of the selected one part in the entire stored logic signals.
Description
METHOD OF DISPLAYING LOGIC SIGNALS
FOR A LOGIC SIGNAL MEASUREMENT APPARATUS
BACKGROUND AND SUMMARY OF THE INVENTION
In accordance with an aspect of the invention there is provided a method of displaying logic signals for a logic signal measurement apparatus, comprising the steps of storing a set of logic input signals in memory means;
displaying a selected part of said set of stored logic signals on display means; and displaying memory capacity indication information simultaneously with said selected part of said logic signals on said display means, said memory capacity indication information indicating the relation of said selected part to said set of stored logic signals.
The recent progress in digital technology makes measurement of digital signals increasingly important like that of analog signals. Logic signal measurement apparatus or logic analyzers are particularly suited for adjustment and maintenance of digital equipment such as digital computers, desktop calculators, computer terminals, digital control units, etc. The capabilities of logic analyzers for measuring logic signals before a triggering .,,~
signal and for generating a trigger signal when input logic signals agree with a predetermined logic pattern are convenient for measuring logic level as well as time relationship of logic signals in data and address buses of a digital equipment under test.
Logic analyzers are designed to store a plurality of logic signals in memory means such as IC memories before displaying such stor~d logic signals on suitable display means such as a cathode-ray tube. Among various other modes, logic analyzers have a parallel timing mode for displaying the stored logic signals in a timing diagram. Memory capacity of logic analyzers can be expanded rather easily for acquiring a larger number of logic signals, but a finite display area of the display means decreases the resolution when the entire stored data are displayed at once, thereby restricting the number of logic signals to be displayed in a timing diagram.
Memory capacity of conventional logic analyzers depends upon the available display area of the display means and the required resolution. In other words, one disadvantage of conventional logic analyzers is the incapability of storing large bits of input logic signals to display in a timing diagram.
The detailed observation of one part of the stored logic signals is made by expanding the display timebase. Two approaches are available for expanding the timebase: one is to increase the gain of the horizontal amplifier with controlling d.c. level for selecting the part to be magnified like an oscilloscope, while the other is to vary the display clock frequency to control the address signal of the memory means for selecting the magnifying location. The latter technique may be more convenient than the former because the magnification factor and magnifying location can be controlled digitally. In addition, the relation between the magnified and unmagnified portions as well as the relation between the magnified portion and the trigger point can conveniently be displayed by digital means. Some conventional oscilloscopes have a display mode for displaying a selected partial waveform to be magnified with higher intensity from the rest of the X
waveform before displaying the magnified waveform, but both magnified and unmagnified waveforms cannot be displayed simultaneously. Although some oscilloscopes have an alternate mode capable of displaying both of these waveforms, this technique cannot be applied to logic analyzers having a large number of input channels and a limited display area. It should be noted that conventional oscilloscopes normally have two input channels while logic analyzers have 8, 16, 32 or more input channels. In addition, no digital information representing the magnification factor and magnifying location is available in a magnifying method by controlling the gain of the horizontal amplifier. Conventional oscilloscopes display the input signal only after a trigger point, therefore no need arises for indicating the relation between the input part to be magnified and the trigger point.
Some conventional logic analyzers use a marker in the unmagnified mode to indicate the start point of the part of the input signal to be magnified. A large number of input channels makes it impossible to display simultaneously the magnified partial input as well as the positional relation of the input before and after magnification.
It is, therefore, one object of this invention to provide a method of displaying logic signals for a logic signal measurement apparatus wherein one part of the logic signals stored in memory means is displayed with magnified scale while simultaneously displaying the indication information for indicating the relation of the magnified part with respect to the entire logic signals.
It is another object of this invention to provide a method of displaying logic signals for a logic signal measurement apparatus capable of storing more bits than conventional storage bits which are determined by the display area and resolution of display means.
It is still another object of this invention to provide a method of displaying logic signals for a logic signal measurement apparatus for simultaneously displaying the magnified display and the indication information indicating the relation of the signal before and after X
magnification.
The indication information used in the method according to this invention is a linear bar (or an indication bar) of a certain length representing the total memory capacity of memory means with an indication for indicating what part of the logic signals in the memory means is actually displayed.
It should be noted, however, that the indication bar is narrow enough to be displayed with a plurality of logic signal waveforms.
BRIEF DESCRIPTION OF THE DRAWINGS:
Fig. 1 is a block diagram of a logic signal measure-ment apparatus to which this invention is applied;
Figs. 2 through 8 show examples of displays on the display unit in Fig.1 for describing this invention; and Fig. 9 and 10 are flow charts for describing this invention.
The reference numerals in these drawings represent:
10 : data probe 12 : input circuit 14 : high speed memory 16 : word recognizer (WR) 18 : clock generator 22 : keyboard 24 : CPU
26 : bus 28 : programmable counter 30 : CPU RAM
32 : ROM
34 : display RAM
36 : display unit 38 : display formatter 40 : Power Supply The present invention will be described in detail hereinafter by reference to the accompanying drawings in which Fig. 1 is a simplified block diagram of a logic analyzer used in this invention. Data probe 10 includes eight active or passive probes each connected between an input terminal for eight channels (channel 0 to 7) and respective probe tip.
~.~5~329 The output of data probe 10 is applied to both high speed memory 14 and word recognizer ~WR) 16 through input circuit 12. WR 16 receives logic signals from terminal 20 and also a reset signal from bidirectional bus 26. The output of WR
16 is applied to programmable counter 28 whose output is then applied to high speed memory 14. As is apparent from Fig. 1, connected to bus 26 are memory 14, clock generator 18, programmable counter 28, central processing unit (CPU) 24, keyboard 22, read only memory (ROM) 32, CPU random access 10 memory (RAM) 30 and display RAM 34. The output of display RAM 34 is applied to raster display unit 36 for displaying it through video display driving circuit 38. Although not shown in Fig. 1, clock generator 18 and power supply 40 are coupled to all or some of the aforementioned blocks.
In cperation, a display as s~n in Fig. 2 appears on the display screen of display unit 36 when power switch is turned on. The display "PRL TIMING" in Fig. 2 means a parallel timing display mode of parallel logic input signals. The present logic analyzer further includes parallel and serial 20 state modes and a signature mode. "<HEX>" means the hexa-decimal parameter setting out of the other available binary, octal and decimal parameter settings. "SMPL" means that the input logic signals are being sampled on the edges of the clock signal. In addition to the "SMPL" mode, there is a 25 "LATCH" mode which is identical to the "SMPL" mode except that any signal transitions such as narrow noise tglitches) during a clock signal interval change the next logic bit. "POST"
means that logic signals after the trigger signal are selected. Other than the "POST" mode, "PRE" mode of 30 operation is also available for selecting logic signals only before the trigger signal. "POS" means the positive logic imo~e but th~- negative logic mode can also be selected. "DATA ~ =
XX" at the second line on the display screen in Fig. 2 shows that the operator should set in WR 16 at the location "XX"
35 an input logic signal combination (characteristic value) in hexadecimal ~ means hexadecimal) to be provided to data probe 10. For setting numbers in binary, octal or decimal, the display will be ~ , ~ , or a respectively. "DLY
= 000~ indicates that the operator set the programmable counter 28 to logic delay for setting a characteristic value at the location "00~0" in hexadecimal. "EXT ~ = X"
at the third line on the display screen shows the logic signal combination to be applied to terminal 20, and the operator sets a hexadecimal number at the location "X".
"SMPL = 50 ns" shows that the sampling period is 50 ns.
Numbers 0 through 7 at the left side of a plurality of hori-zontal lines represent the channel numbers.
Now, the operator pushes keyboard 22 to select necessary parameters. CPU 24, then, processes the signalentered from keyboard 22 in accordance with the instructions stored in ROM 32 and transfers the parameter information to display RAM 34. The information stored in display RAM 34 is recalled (or refreshed) periodically for being displayed on display unit 36 after conversion into a television signal by video display driving circuit 38. Let us assume that the operator entered the following parameters: the logic combination of WR 16 to data probe 10 being "3F", neglecting the signal from external terminal 20 ~thereby leaving the display at right of "EXT ~ " to "X"), and digital delay and sampling period being respectively "2A6F" and "5~s." The display as shown in Fig. 3 will result if the start button keyboard 22 is pushed.
The logic level of the input signal detected by data probe 10 is converted to a desired level such as TTL
(transistor transistor logic), ECL (emitter coupled logic), etc. by input circuit 12 comprising comparators for making judgment of the input logic level thereto. The waveform shaped logic signal from input circuit 12 is applied to high speed memory 14 and WR 16. Memory 14 stores the output from input circuit 12 in synchronism with the clock pulse (having a period of 5 ~s or a frequency of 200 kHz in this particular embodiment) from clock oscillator 18. When the input signal agrees with the logic combination "3F" set in WR 16, a first control signal is generated by WR 16 to be supplied to counter 28. This first control signal initiates counter 28 to count 3Z~
the clock pulses. The memory capacity per channel is 252 bits in this particular embodiment. The "POST" trigger mode is designed to store 12 bits preceeding the trigger pulse. Thus, counter 28 counts 2A6F (equivalent to 10863 in decimal) +
(252 - 12) (both decimal) before generating a second control signal to be applied to memory 14. If "PRE" trigger mode were selected, 12 bits after the trigger signal are also stored and counter 28 counts "2A6F" + 12 (decimal) before generating the aforementioned second control signal. The digital delay time in this particular example is 5~s x 2A6F =
53.15 ms in decimal. Both WR 16 and programmable counter 28 are controlled by keyboard 22 by way of CPU 24 and bus 26.
On receiving the second control signal, memory 14 stops storing the input logic signals. This means that memory 14 stores only logic signals before the occurrence of the second control signal. The data stored in memory 14 is transferred to CPU RAM 30. As mentioned hereinbefore, the resolution and display area limitations of raster-display unit 36lallows only 168 bits to be displayed despite the memory capacity of 252 bits per channel. This means that only fraction of the stored data can be displayed on raster display unit 36 (see Fig. 4).
There arises a need to identify the displayed data with respect to the entire stored data corresponding to the memory capacity. A push of a window button in keyboard 22 will display "WDO" representing the window mode, 168 bits of the input data and an indication bar. The entire length of the indication bar represents the maximum memory capacity while the white zone, black zone and "O" represent respectively the displayed part, nondisplayed part of the stored logic signals and the trigger point. These inCormations are pro-cessed by CPU 24 upon receiving instructions therefrom.
If the window button is pushed again, the timebase of the display is expanded as shown in Fig. 6. The magn-ification factor is 168/84 = 2. In this case, each bit ofthe data stored in CPU RAM 30 is transferred to display RAM 34 at every two clock pulses, thereby modifying the contents of display R~ 34. As shown in Fig. 7, another push of the window button will magnify the display waveform by the factor of four with respect to Fig. 5. Each bit of the data stored in CPU RAM 30 is transferred to display RAM 34 at every four clock pulses. A position control in keyboard 22 controls the part to be displayed. The position control signal from keyboard 22 is sensed by CPU 24 which selects the address of CPU RAM 30 in response to the position control signal when the data within CPU RAM 30 is transferred to display RAM 34. Fig. 8 shows how the indication information display varies as the display position is controlled. Fig. 8A
and B are in the "POST" trigger mode while Fig. 8C through G
are in the "PRE" trigger mode.
Fig. 9 is a flow chart for explaining the method of displaying the indicator information according to this invention. When the window mode is selected, the display indicator point moves to the left end of the indication bar in step 50 and CPU 24 judges in step 52 whether the magnifica-tion factor is unity or not. The indication bar is divided into 21 distinctive sections each comprising 12 byte. With the unity magnification factor, the unmagnified mode displays 168 byte (168 bit x 8 channel = 12 bit x 14 section). CPU
24 counts 14 sections in step 54. With any modes other than the unity magnification factor, CPU 24 judges whether or not the magnification factor is 2. If the magnification factor 25 is judged to be 2, 84 byte data (84 bit x 8 channel = 12 bit x 7 section) are displayed and CPU 24 counts 7 sections in step 58. If the magnification factor is not 2, CPU 24 judges in step 60 whether or not the magnification factor is 4. In the magnification factor of 4, 42 byte data (42 bit x 8 channel 30 . 12 bit x 4 section) are displayed with CPU 24 counting 4 sections in step 62. If the magnification factor is not 4, step 64 leads the svstem to automatically perform the magnification mode in step 62, thereby avoiding any system error.
The foregoing description reveals that the display position can be controlled by the position control in key-board 22. Now, CPV 24 senses the display position in step 66 and the subsequent step 68 substracts 12 from the display 3~9 position. Step 70 judges whether the result is positive or negative.
One black section ~ result at the display indicator point in step 72 if it is positive. After displaying the black section, the display indicator point advances to the next section in step 74 before returning to step 68. If the subtraction is negative in step 70, however, step 76 is per-formed to add 12 to the result of the subtraction. A
judgment is made in step 78 whether the addition is equal to 10 zero or not. If it is zero, a plurality of white sections O
will be displayed in step 80. The number of white sections solely depends on the selected magnification factor, which is 14, 7 and 4 respectively for 1, 2 and 4 magnificat.ion factors. After displaying a plurality of white sections, one 15 black section is displayed in step 82 and the display indicator point advances to the next section in step 84. CPU
24 judges in step 86 whether or not the display of the indication information has been completed. The operation returns to step 82 if not completed, but stops if completed.
Returning now to step 78, a first black and white section ~ with black at the left half and white at the right half will be displayed in step 88 if the result of the addition is not zero. The display indicator point advances to the next section in step 90 and displays a white section 25 a in step 92 similar to step 80. Then, a second black and white section ~ with opposite black and white relation to the first black and white section is displayed in step 94.
The display indicator point advances to the next section in step 96 to perform step 86. The indication bar is, there-30 fore, divided into 21 sections including two black and whitesections in step 88 and 94.
Fig. 10 illustrates a flow chart for explaining how a trigger point is displayed. Firstly, CPU 24 detects the trigger point in step 98 for judging in step 100 if the 35 "POST" trigger mode is selected. The display indicator point moves in step 102 to the left end in the "POST" trigger mode while to the right end in step 106 in the "PRE" trigger mode.
A trigger point indication mark "O" is displayed in step 104 L3~
at the trigger point, thereby accomplishing the trigger point ', display.
As described hereinbefore, this invention is intended to display a selectable part of the logic signals stored in the memory simultaneously with the relative position of the selected part in the entire logic signals. A logic analyzer to which this invention is applied stores logic signals exceeding the memory capacity determined by the display area and resolution of the display unit. In addition, the present 10 invention provides the operator with means for conveniently identifying the relative position of the part to be magnified and the memory capacity.
Although one preferred embodiment ls illustrated and described hereinbefore, a person skilled in the art will 15 understand that various modifications can be made without departing from the subject matter of this invention.
FOR A LOGIC SIGNAL MEASUREMENT APPARATUS
BACKGROUND AND SUMMARY OF THE INVENTION
In accordance with an aspect of the invention there is provided a method of displaying logic signals for a logic signal measurement apparatus, comprising the steps of storing a set of logic input signals in memory means;
displaying a selected part of said set of stored logic signals on display means; and displaying memory capacity indication information simultaneously with said selected part of said logic signals on said display means, said memory capacity indication information indicating the relation of said selected part to said set of stored logic signals.
The recent progress in digital technology makes measurement of digital signals increasingly important like that of analog signals. Logic signal measurement apparatus or logic analyzers are particularly suited for adjustment and maintenance of digital equipment such as digital computers, desktop calculators, computer terminals, digital control units, etc. The capabilities of logic analyzers for measuring logic signals before a triggering .,,~
signal and for generating a trigger signal when input logic signals agree with a predetermined logic pattern are convenient for measuring logic level as well as time relationship of logic signals in data and address buses of a digital equipment under test.
Logic analyzers are designed to store a plurality of logic signals in memory means such as IC memories before displaying such stor~d logic signals on suitable display means such as a cathode-ray tube. Among various other modes, logic analyzers have a parallel timing mode for displaying the stored logic signals in a timing diagram. Memory capacity of logic analyzers can be expanded rather easily for acquiring a larger number of logic signals, but a finite display area of the display means decreases the resolution when the entire stored data are displayed at once, thereby restricting the number of logic signals to be displayed in a timing diagram.
Memory capacity of conventional logic analyzers depends upon the available display area of the display means and the required resolution. In other words, one disadvantage of conventional logic analyzers is the incapability of storing large bits of input logic signals to display in a timing diagram.
The detailed observation of one part of the stored logic signals is made by expanding the display timebase. Two approaches are available for expanding the timebase: one is to increase the gain of the horizontal amplifier with controlling d.c. level for selecting the part to be magnified like an oscilloscope, while the other is to vary the display clock frequency to control the address signal of the memory means for selecting the magnifying location. The latter technique may be more convenient than the former because the magnification factor and magnifying location can be controlled digitally. In addition, the relation between the magnified and unmagnified portions as well as the relation between the magnified portion and the trigger point can conveniently be displayed by digital means. Some conventional oscilloscopes have a display mode for displaying a selected partial waveform to be magnified with higher intensity from the rest of the X
waveform before displaying the magnified waveform, but both magnified and unmagnified waveforms cannot be displayed simultaneously. Although some oscilloscopes have an alternate mode capable of displaying both of these waveforms, this technique cannot be applied to logic analyzers having a large number of input channels and a limited display area. It should be noted that conventional oscilloscopes normally have two input channels while logic analyzers have 8, 16, 32 or more input channels. In addition, no digital information representing the magnification factor and magnifying location is available in a magnifying method by controlling the gain of the horizontal amplifier. Conventional oscilloscopes display the input signal only after a trigger point, therefore no need arises for indicating the relation between the input part to be magnified and the trigger point.
Some conventional logic analyzers use a marker in the unmagnified mode to indicate the start point of the part of the input signal to be magnified. A large number of input channels makes it impossible to display simultaneously the magnified partial input as well as the positional relation of the input before and after magnification.
It is, therefore, one object of this invention to provide a method of displaying logic signals for a logic signal measurement apparatus wherein one part of the logic signals stored in memory means is displayed with magnified scale while simultaneously displaying the indication information for indicating the relation of the magnified part with respect to the entire logic signals.
It is another object of this invention to provide a method of displaying logic signals for a logic signal measurement apparatus capable of storing more bits than conventional storage bits which are determined by the display area and resolution of display means.
It is still another object of this invention to provide a method of displaying logic signals for a logic signal measurement apparatus for simultaneously displaying the magnified display and the indication information indicating the relation of the signal before and after X
magnification.
The indication information used in the method according to this invention is a linear bar (or an indication bar) of a certain length representing the total memory capacity of memory means with an indication for indicating what part of the logic signals in the memory means is actually displayed.
It should be noted, however, that the indication bar is narrow enough to be displayed with a plurality of logic signal waveforms.
BRIEF DESCRIPTION OF THE DRAWINGS:
Fig. 1 is a block diagram of a logic signal measure-ment apparatus to which this invention is applied;
Figs. 2 through 8 show examples of displays on the display unit in Fig.1 for describing this invention; and Fig. 9 and 10 are flow charts for describing this invention.
The reference numerals in these drawings represent:
10 : data probe 12 : input circuit 14 : high speed memory 16 : word recognizer (WR) 18 : clock generator 22 : keyboard 24 : CPU
26 : bus 28 : programmable counter 30 : CPU RAM
32 : ROM
34 : display RAM
36 : display unit 38 : display formatter 40 : Power Supply The present invention will be described in detail hereinafter by reference to the accompanying drawings in which Fig. 1 is a simplified block diagram of a logic analyzer used in this invention. Data probe 10 includes eight active or passive probes each connected between an input terminal for eight channels (channel 0 to 7) and respective probe tip.
~.~5~329 The output of data probe 10 is applied to both high speed memory 14 and word recognizer ~WR) 16 through input circuit 12. WR 16 receives logic signals from terminal 20 and also a reset signal from bidirectional bus 26. The output of WR
16 is applied to programmable counter 28 whose output is then applied to high speed memory 14. As is apparent from Fig. 1, connected to bus 26 are memory 14, clock generator 18, programmable counter 28, central processing unit (CPU) 24, keyboard 22, read only memory (ROM) 32, CPU random access 10 memory (RAM) 30 and display RAM 34. The output of display RAM 34 is applied to raster display unit 36 for displaying it through video display driving circuit 38. Although not shown in Fig. 1, clock generator 18 and power supply 40 are coupled to all or some of the aforementioned blocks.
In cperation, a display as s~n in Fig. 2 appears on the display screen of display unit 36 when power switch is turned on. The display "PRL TIMING" in Fig. 2 means a parallel timing display mode of parallel logic input signals. The present logic analyzer further includes parallel and serial 20 state modes and a signature mode. "<HEX>" means the hexa-decimal parameter setting out of the other available binary, octal and decimal parameter settings. "SMPL" means that the input logic signals are being sampled on the edges of the clock signal. In addition to the "SMPL" mode, there is a 25 "LATCH" mode which is identical to the "SMPL" mode except that any signal transitions such as narrow noise tglitches) during a clock signal interval change the next logic bit. "POST"
means that logic signals after the trigger signal are selected. Other than the "POST" mode, "PRE" mode of 30 operation is also available for selecting logic signals only before the trigger signal. "POS" means the positive logic imo~e but th~- negative logic mode can also be selected. "DATA ~ =
XX" at the second line on the display screen in Fig. 2 shows that the operator should set in WR 16 at the location "XX"
35 an input logic signal combination (characteristic value) in hexadecimal ~ means hexadecimal) to be provided to data probe 10. For setting numbers in binary, octal or decimal, the display will be ~ , ~ , or a respectively. "DLY
= 000~ indicates that the operator set the programmable counter 28 to logic delay for setting a characteristic value at the location "00~0" in hexadecimal. "EXT ~ = X"
at the third line on the display screen shows the logic signal combination to be applied to terminal 20, and the operator sets a hexadecimal number at the location "X".
"SMPL = 50 ns" shows that the sampling period is 50 ns.
Numbers 0 through 7 at the left side of a plurality of hori-zontal lines represent the channel numbers.
Now, the operator pushes keyboard 22 to select necessary parameters. CPU 24, then, processes the signalentered from keyboard 22 in accordance with the instructions stored in ROM 32 and transfers the parameter information to display RAM 34. The information stored in display RAM 34 is recalled (or refreshed) periodically for being displayed on display unit 36 after conversion into a television signal by video display driving circuit 38. Let us assume that the operator entered the following parameters: the logic combination of WR 16 to data probe 10 being "3F", neglecting the signal from external terminal 20 ~thereby leaving the display at right of "EXT ~ " to "X"), and digital delay and sampling period being respectively "2A6F" and "5~s." The display as shown in Fig. 3 will result if the start button keyboard 22 is pushed.
The logic level of the input signal detected by data probe 10 is converted to a desired level such as TTL
(transistor transistor logic), ECL (emitter coupled logic), etc. by input circuit 12 comprising comparators for making judgment of the input logic level thereto. The waveform shaped logic signal from input circuit 12 is applied to high speed memory 14 and WR 16. Memory 14 stores the output from input circuit 12 in synchronism with the clock pulse (having a period of 5 ~s or a frequency of 200 kHz in this particular embodiment) from clock oscillator 18. When the input signal agrees with the logic combination "3F" set in WR 16, a first control signal is generated by WR 16 to be supplied to counter 28. This first control signal initiates counter 28 to count 3Z~
the clock pulses. The memory capacity per channel is 252 bits in this particular embodiment. The "POST" trigger mode is designed to store 12 bits preceeding the trigger pulse. Thus, counter 28 counts 2A6F (equivalent to 10863 in decimal) +
(252 - 12) (both decimal) before generating a second control signal to be applied to memory 14. If "PRE" trigger mode were selected, 12 bits after the trigger signal are also stored and counter 28 counts "2A6F" + 12 (decimal) before generating the aforementioned second control signal. The digital delay time in this particular example is 5~s x 2A6F =
53.15 ms in decimal. Both WR 16 and programmable counter 28 are controlled by keyboard 22 by way of CPU 24 and bus 26.
On receiving the second control signal, memory 14 stops storing the input logic signals. This means that memory 14 stores only logic signals before the occurrence of the second control signal. The data stored in memory 14 is transferred to CPU RAM 30. As mentioned hereinbefore, the resolution and display area limitations of raster-display unit 36lallows only 168 bits to be displayed despite the memory capacity of 252 bits per channel. This means that only fraction of the stored data can be displayed on raster display unit 36 (see Fig. 4).
There arises a need to identify the displayed data with respect to the entire stored data corresponding to the memory capacity. A push of a window button in keyboard 22 will display "WDO" representing the window mode, 168 bits of the input data and an indication bar. The entire length of the indication bar represents the maximum memory capacity while the white zone, black zone and "O" represent respectively the displayed part, nondisplayed part of the stored logic signals and the trigger point. These inCormations are pro-cessed by CPU 24 upon receiving instructions therefrom.
If the window button is pushed again, the timebase of the display is expanded as shown in Fig. 6. The magn-ification factor is 168/84 = 2. In this case, each bit ofthe data stored in CPU RAM 30 is transferred to display RAM 34 at every two clock pulses, thereby modifying the contents of display R~ 34. As shown in Fig. 7, another push of the window button will magnify the display waveform by the factor of four with respect to Fig. 5. Each bit of the data stored in CPU RAM 30 is transferred to display RAM 34 at every four clock pulses. A position control in keyboard 22 controls the part to be displayed. The position control signal from keyboard 22 is sensed by CPU 24 which selects the address of CPU RAM 30 in response to the position control signal when the data within CPU RAM 30 is transferred to display RAM 34. Fig. 8 shows how the indication information display varies as the display position is controlled. Fig. 8A
and B are in the "POST" trigger mode while Fig. 8C through G
are in the "PRE" trigger mode.
Fig. 9 is a flow chart for explaining the method of displaying the indicator information according to this invention. When the window mode is selected, the display indicator point moves to the left end of the indication bar in step 50 and CPU 24 judges in step 52 whether the magnifica-tion factor is unity or not. The indication bar is divided into 21 distinctive sections each comprising 12 byte. With the unity magnification factor, the unmagnified mode displays 168 byte (168 bit x 8 channel = 12 bit x 14 section). CPU
24 counts 14 sections in step 54. With any modes other than the unity magnification factor, CPU 24 judges whether or not the magnification factor is 2. If the magnification factor 25 is judged to be 2, 84 byte data (84 bit x 8 channel = 12 bit x 7 section) are displayed and CPU 24 counts 7 sections in step 58. If the magnification factor is not 2, CPU 24 judges in step 60 whether or not the magnification factor is 4. In the magnification factor of 4, 42 byte data (42 bit x 8 channel 30 . 12 bit x 4 section) are displayed with CPU 24 counting 4 sections in step 62. If the magnification factor is not 4, step 64 leads the svstem to automatically perform the magnification mode in step 62, thereby avoiding any system error.
The foregoing description reveals that the display position can be controlled by the position control in key-board 22. Now, CPV 24 senses the display position in step 66 and the subsequent step 68 substracts 12 from the display 3~9 position. Step 70 judges whether the result is positive or negative.
One black section ~ result at the display indicator point in step 72 if it is positive. After displaying the black section, the display indicator point advances to the next section in step 74 before returning to step 68. If the subtraction is negative in step 70, however, step 76 is per-formed to add 12 to the result of the subtraction. A
judgment is made in step 78 whether the addition is equal to 10 zero or not. If it is zero, a plurality of white sections O
will be displayed in step 80. The number of white sections solely depends on the selected magnification factor, which is 14, 7 and 4 respectively for 1, 2 and 4 magnificat.ion factors. After displaying a plurality of white sections, one 15 black section is displayed in step 82 and the display indicator point advances to the next section in step 84. CPU
24 judges in step 86 whether or not the display of the indication information has been completed. The operation returns to step 82 if not completed, but stops if completed.
Returning now to step 78, a first black and white section ~ with black at the left half and white at the right half will be displayed in step 88 if the result of the addition is not zero. The display indicator point advances to the next section in step 90 and displays a white section 25 a in step 92 similar to step 80. Then, a second black and white section ~ with opposite black and white relation to the first black and white section is displayed in step 94.
The display indicator point advances to the next section in step 96 to perform step 86. The indication bar is, there-30 fore, divided into 21 sections including two black and whitesections in step 88 and 94.
Fig. 10 illustrates a flow chart for explaining how a trigger point is displayed. Firstly, CPU 24 detects the trigger point in step 98 for judging in step 100 if the 35 "POST" trigger mode is selected. The display indicator point moves in step 102 to the left end in the "POST" trigger mode while to the right end in step 106 in the "PRE" trigger mode.
A trigger point indication mark "O" is displayed in step 104 L3~
at the trigger point, thereby accomplishing the trigger point ', display.
As described hereinbefore, this invention is intended to display a selectable part of the logic signals stored in the memory simultaneously with the relative position of the selected part in the entire logic signals. A logic analyzer to which this invention is applied stores logic signals exceeding the memory capacity determined by the display area and resolution of the display unit. In addition, the present 10 invention provides the operator with means for conveniently identifying the relative position of the part to be magnified and the memory capacity.
Although one preferred embodiment ls illustrated and described hereinbefore, a person skilled in the art will 15 understand that various modifications can be made without departing from the subject matter of this invention.
Claims (7)
1. A method of displaying logic signals for a logic signal measurement apparatus, comprising the steps of:
storing a set of logic input signals in memory means; displaying a selected part of said set of stored logic signals on display means; and displaying memory capacity indication information simultaneously with said selected part of said logic signals on said display means, said memory capacity indication information indicating the relation of said selected part to said set of stored logic signals.
storing a set of logic input signals in memory means; displaying a selected part of said set of stored logic signals on display means; and displaying memory capacity indication information simultaneously with said selected part of said logic signals on said display means, said memory capacity indication information indicating the relation of said selected part to said set of stored logic signals.
2. A method of displaying logic signals for a logic signal measurement apparatus according to claim 1, wherein said memory capacity indication information is a bar graph the total length of which represents the entire set of stored logic signals.
3. A method of displaying logic signals for a logic signal measurement apparatus according to claim 2, wherein said bar graph is modulated to indicate said selected part in relationship to the entire set of stored logic signals.
4. A method of displaying logic signals for a logic signal measurement apparatus to claim 1 further comprising the step of:
selecting from said set of stored logic signals a part thereof to be displayed.
selecting from said set of stored logic signals a part thereof to be displayed.
5. A method of displaying logic signals for a logic signal measurement apparatus according to claim 1 further comprising the step of:
changing the magnification factor of the displayed logic signals by changing the memory capacity of said memory means for the logic signal to be displayed.
changing the magnification factor of the displayed logic signals by changing the memory capacity of said memory means for the logic signal to be displayed.
6. A method of displaying logic signals for a logic signal measurement apparatus according to claim 5 further comprising the step of:
indicating with numerals the capacity of said memory means for logic signal to be displayed.
indicating with numerals the capacity of said memory means for logic signal to be displayed.
7. A method of displaying logic signals for a logic signal measurement apparatus according to claim 1 further comprising the step of:
displaying trigger information simultaneously with said indication information on said display means.
displaying trigger information simultaneously with said indication information on said display means.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP100659/79 | 1979-08-07 | ||
| JP54100659A JPS5827465B2 (en) | 1979-08-07 | 1979-08-07 | Logic signal display method on logic signal measuring instrument |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1151329A true CA1151329A (en) | 1983-08-02 |
Family
ID=14279925
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000357589A Expired CA1151329A (en) | 1979-08-07 | 1980-08-05 | Method of displaying logic signals for a logic signal measurement apparatus |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPS5827465B2 (en) |
| CA (1) | CA1151329A (en) |
| DE (1) | DE3029839A1 (en) |
| FR (1) | FR2463456A1 (en) |
| GB (1) | GB2066030B (en) |
| NL (1) | NL187087C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10845389B2 (en) | 2018-03-05 | 2020-11-24 | Rohde & Schwarz Gmbh & Co. Kg | Measurement device and method for visualization of multiple channels |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2114306B (en) * | 1981-12-28 | 1985-07-31 | Sony Tektronix Corp | Logic analyser |
| JPS58140899A (en) * | 1982-02-16 | 1983-08-20 | ソニ−・テクトロニクス株式会社 | Logic signal indication |
| DE3511602A1 (en) * | 1985-03-27 | 1986-10-02 | CREATEC Gesellschaft für Elektrotechnik mbH, 1000 Berlin | Signal-processing device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3859556A (en) * | 1972-11-15 | 1975-01-07 | Nicolet Instrument Corp | Digital measurement apparatus with improved expanded display |
-
1979
- 1979-08-07 JP JP54100659A patent/JPS5827465B2/en not_active Expired
-
1980
- 1980-07-29 NL NL8004331A patent/NL187087C/en not_active IP Right Cessation
- 1980-07-31 GB GB8025045A patent/GB2066030B/en not_active Expired
- 1980-08-01 FR FR8017320A patent/FR2463456A1/en active Granted
- 1980-08-05 CA CA000357589A patent/CA1151329A/en not_active Expired
- 1980-08-06 DE DE19803029839 patent/DE3029839A1/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10845389B2 (en) | 2018-03-05 | 2020-11-24 | Rohde & Schwarz Gmbh & Co. Kg | Measurement device and method for visualization of multiple channels |
Also Published As
| Publication number | Publication date |
|---|---|
| FR2463456B1 (en) | 1985-01-04 |
| GB2066030B (en) | 1983-05-11 |
| DE3029839C2 (en) | 1987-07-30 |
| JPS5624579A (en) | 1981-03-09 |
| GB2066030A (en) | 1981-07-01 |
| NL187087B (en) | 1990-12-17 |
| DE3029839A1 (en) | 1981-04-09 |
| NL8004331A (en) | 1981-02-10 |
| NL187087C (en) | 1991-05-16 |
| FR2463456A1 (en) | 1981-02-20 |
| JPS5827465B2 (en) | 1983-06-09 |
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| MKEX | Expiry |