JPS5827465B2 - Logic signal display method on logic signal measuring instrument - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a logic signal measuring instrument having a storage means for storing a logic input signal and a display means for displaying a part of the stored logic signal. The present invention relates to a logic signal display method for simultaneously displaying instruction information indicating which portion of a stored logic signal a display portion corresponds to.

BACKGROUND OF THE INVENTION Digital technology has recently become increasingly popular for measuring digital and analog signals.

Logic signal measuring devices, ie, logic analyzers, are particularly suitable for adjusting and maintaining digital equipment such as computers, desk calculators, computer vehicle terminals, digital control devices, and the like.

The logic analyzer as described above measures the logic signal before the trigger signal and generates the trigger signal when a combination of logic signals matches a predetermined logic pattern.
It is useful for measuring time relationships as well as logic levels of logic signals on buses, address buses, and circuits under test.

The logic analyzer stores a plurality of logic signals in a storage means (e.g., I
C memory), and the stored logic signals are read out and displayed on a suitable display means (for example, a cathode ray tube).

One of the display modes of the logic analyzer is a parallel timing mode that displays timing diagrams of stored parallel logic signals.

Although it is relatively easy to increase the storage capacity of a logic analyzer, the limited display area and resolution of the display means limits the timing diagrams that can be displayed.

Therefore, the storage capacity of conventional logic analyzers was determined by the display area and the resolution of the display means.

First, conventional logic analyzers have the disadvantage of not being able to store logic input signals having a large number of bits when displaying stored parallel logic signals in timing diagrams.

On the other hand, in order to observe a portion of the stored logic signal in detail, it is necessary to expand the time axis of the display.

There are two methods for time axis expansion.One is similar to an oscilloscope, where the expansion rate is controlled by the gain of the horizontal amplifier, and the expansion position is controlled by changing the DC level of the horizontal amplifier. In this method, the magnification rate is controlled by changing the frequency of the display clock signal, and the magnification position is controlled by the address signal of the storage means.

The latter method is more convenient than the former method because the magnification factor and position can be digitally controlled and directed.

Furthermore, the latter method is advantageous because it allows the operator to digitally indicate the relationship between the magnified portion and the non-magnified portion, as well as the relationship between the magnified portion and the trigger time.

Conventional oscilloscopes have a mode that displays an enlarged waveform after increasing the brightness of the area to be enlarged, but in this mode, it is not possible to display the enlarged waveform and the waveform before enlargement at the same time.

On the other hand, some oscilloscopes have an alternate (or ALT) mode that can display both the unenlarged waveform and the enlarged waveform, but since the logic analyzer has a large number of input channels and the display area is limited, the above mode is It cannot be applied to logic analyzers.

By the way, the number of input channels of a conventional oscilloscope is 2.
However, the number of input channels of the logic analyzer is 8.16.
, or 32.

Furthermore, in the method of controlling and expanding the gain of a horizontal amplifier,
Digital information regarding the magnification rate and magnification position cannot be obtained.

However, since conventional oscilloscopes display the input branch shape after the trigger point, it is natural that there is no need to indicate the relationship between the enlarged position and the trigger point.

By the way, conventional logic analyzers can indicate the starting point of the part to be enlarged by using a marker in the display before enlargement, but because the number of input channels is extremely large, the positional relationship before and after enlargement is displayed together with the enlarged display. cannot be displayed at the same time.

Therefore, an object of the present invention is to provide a logic signal measuring instrument that simultaneously displays an enlarged display of a portion of a logic signal stored in a storage means and instruction information indicating the relationship between the entire recorded logic signal and the displayed portion. An object of the present invention is to provide a signal display method.

An object of the present invention is to provide a logic signal display method for a logic signal measuring instrument that can store more bits than the conventional storage bit number determined by the display area and resolution of the display means.

A further object of the present invention is to provide a logic signal display method for a logic signal measuring instrument that simultaneously displays enlarged display and instruction information indicating the relationship after enlargement with respect to before enlargement.

The instruction information used in the method of the present invention is a linear band (or instruction bar) with a length corresponding to the capacity of the storage means, and the instruction bar indicates which part of the storage means is indicating the logic signal. instruct.

Since the width of the instruction bar is narrow, instruction information can be displayed along with multiple logic signal waveforms.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram schematically showing a logic analyzer used in the present invention.

1, data probe 10 is connected to channel O.
70 is an active or passive probe having a total of 8 channels of input terminals and 8 tips connected to these input terminals.

The output of the data probe 10 is applied via an input circuit 12 to a high speed storage device 14 and a word recognizer (logical combination detector, hereinafter abbreviated as WR) 16.

WR 16 receives logic signals from terminal 20 and also receives set signals from bidirectional bus 26.

The output of WR 16 is recorded in programmable counter 28, and the output of counter 28 is recorded in high speed memory 14.

As is clear from the drawing, a storage device 14, a clock generator 18, a phragma pull counter 28, a central processing unit (
A keyboard 22, a read-only memory (hereinafter referred to as ROM) 32, a CPU random access memory (hereinafter referred to as RAM) 30, and a display RAM 34,
Each is connected to a bus 26.

The output of the display RAM 34 is printed and displayed on the raster display device 36 via the video display drive circuit 38.

Although not shown in the drawing, the clock generator 18 and power supply 40 are connected to each of the blocks described above.

Now, when the power switch is turned on, a display as shown in FIG. 2 appears on the display surface of the display device 36.

In the display of Figure 2, rPRL TIMINGj indicates that parallel logic input signals are displayed in parallel timing mode, but the logic analyzer also has display modes of parallel and serial spout modes, and signature mode. be.

r<HEX>j indicates that the parameter setting is performed in hexadecimal notation, but parameter setting can also be done in binary, octal, or decimal notation.

rsMPLJ indicates that the input logic signal is sampled on the edges of the clock signal.

The rsMPLJ mode has an rLATcHJ mode that is identical to the rsMPLJ mode except that changes in the input between clock signals (eg, glitches) are indicated by inverting the next logical bit.

rPO8TJ indicates that the logic signal after the trigger signal is selected.

After this, rP selects the logic signal before the trigger signal.
There is a REJ mode.

rPO8J indicates positive logic mode, but
Of course, negative logic mode can also be selected.

"rDATAIE-XX" on the second stage of the display screen shown in Figure 2.
, the operator says ``Insert the data probe 10 at
The combination of logical input signals (i.e., characteristic values) input to
It indicates that it should be set to WR16 in hexadecimal (mai means hexadecimal).

In addition, when setting in decimal number 2, 8.
A mouth display appears.

rDLY[E=θθθθ] indicates that the programmable counter 28 is set to logic delay, and the operator
Set the characteristic value in hexadecimal at the location “θθ”.

rEXTIE=XJ on the third row of the display screen indicates a combination of logic signals applied to the terminal 20, and the operator sets the combination at the "x" location.

rSMPL=50nsj has a sampling period of 50n
s, and the numbers O to 7 on the left side of multiple horizontal lines
is the channel number.

Now, when the operator presses a button on the keyboard 22 to select a necessary parameter, the CPU 24 processes the signal input to the keyboard 22 according to the commands stored in the ROM 32, and transfers the parameter information to the display RAM 34.

The information stored in the display RAM is called out periodically, converted into a television video signal by the video display device drive circuit 38, and displayed on the display device 36.

For example, suppose that the operator sets the parameters as follows.

That is, the logical combination of WR16 is set to the data probe 10 as "3FJ, so that the signal from the external terminal 20 is ignored. Therefore, J'EXT [the display on the right side of EJ is the residue of "x]\
), digital delay and sampling period are set to ``2A'', respectively.
After setting 6Fj and "5μS", press the start button on the keyboard 22, and the display as shown in FIG. 3 will appear.

Since the logic level of the input signal detected by the data probe 10 is determined by the input circuit 12 from the comparator that determines the logic input level, the output of the input circuit 12 is TTL (
) run raster transistor logic), ECL (emitter coupled logic), etc.

The shaped logic signal from input circuit 12 is now applied to high speed storage 14 and WR 16.

The storage device 14 receives the clock signal from the clock oscillator 18.
Pulse (in this example, period 5μS (frequency 200KH)
z), the output of the input circuit 12 is stored.

Since WR16 is set to "3F", if the logical combination of input signals is "3F", WR16 is set to counter 28.
A first control signal is generated.

This first control signal causes counter 28 to begin counting clock pulses.

The storage capacity per channel in this embodiment is 252 bits, and in the rPO8TJ trigger mode, the 12
Since bits are also stored, the counter 28 is 2A6A (10
10863) + (252-12) (decimal)
is counted and a second control signal is printed in the storage device 14.

If the rPREJ l-trigger mode is selected, the 12 bits after the trigger are also stored, so the counter 28
counts r2A6FJ +12 (decimal number) and generates the second control signal.

In this case, the digital delay time is 5μ5×2A6F=5
It is 3.15 (decimal number) ms.

WR16 and phlograma pull counter 28 are CPU
24 and bus 26 via keyboard 22 .

When the storage device 14 receives the second control signal, the storage device 1
4 stops the storage operation of the logic input signal.

In this way, the storage device 14 stores the logic signal before the second control signal is generated.

The data stored in the storage device is stored in the CPU RAM3.
Transferred to 0.

As mentioned above, the storage capacity per channel is 252 bits, but raster display device 36 can only display 168 bits due to resolution and display area constraints.

Therefore, only a portion of the stored data is displayed on the raster display 36 (see FIG. 4).

Display data is stored data (equal to storage capacity)
If you want to know which part of the screen it corresponds to, press the window button on the keyboard 22, and as shown in Figure 5, "WDO" indicating the window mode, the number of display bits (168 bits), and An instruction bar, which is linear instruction information, is displayed.

The total length of the instruction bar corresponds to the storage capacity, the white part is the displayed part, the black part is the not displayed part, and the "0" part is the part that is not displayed.
” indicates the trigger point.

This information is sent to the CPU according to instructions from the ROM32.
24.

Next, pressing the window button again will enlarge the time axis of the display as shown in FIG.

The magnification ratio is 168/84=2.

In this case, each bit of data stored in CPU RAM 30 is transferred to display RAM 34 every two clock pulses, changing the contents of display RAM 34.

When the window button is pressed again, the display will be as shown in Figure 7.The displayed waveform will be enlarged four times compared to that shown in Figure 5, so each bit of data stored in CPU RAM 30 will take four clocks. - Transferred to the display RAM 34 for each pulse.

The display portion is controlled by a single position control on the keyboard 22.

A position control signal from keyboard 22 is detected by CPU 24, and CPU 24 selects an address in CPU RAM 30 in response to the position control signal when data in CPU RAM 30 is transferred to display RAM 34.

FIG. 8 shows changes in the display of instruction information when the display position is controlled.

8A and 8B are the rPO8T') rigging mode, and FIGS. 8C to 8G are the rPREJ) rigging mode.

FIG. 9 is a flowchart for explaining a method of displaying instruction information according to the present invention.

When the window mode is selected, the display instruction point moves to the left end of the instruction bar (step 50), and in step 52, the CPU 24 determines whether the magnification rate is 1.

The instruction bar is divided into 21 sections, and each section has 12 sections.
Consists of bytes.

When the expansion rate is 1, the non-expansion mode is 168 bytes) (1
68 bits x 8 channels - 12 bits x 14 sections), the CPU 24 counts 14 sections at step 54.

If the magnification rate is not 1, step 56 sets the magnification rate to 2.
The CPU 24 determines whether or not.

As a result of the judgment, when the magnification rate is 2, the magnification rate 2 mode is 84 bytes [84 bits x 8 channels - 12 bits x
7 divisions), the CPU 24 coefficients the 7 divisions in step 58.

If the magnification rate is not 2, the CPU 24 determines whether the magnification rate is 4 in step 60.

When the magnification rate is 4, the mode with magnification rate 4 is 42 bytes (
42 bits x 12 bits out of 8 channels x 4 sections), the CPU 24 counts 4 sections at step 62.

If the magnification factor is not 4, the magnification mode automatically goes to step 62 via step 64 to avoid system malfunction.

As described above, the display position is controlled by position control of the keyboard 22.

Now, the CPU 24 detects the display position in step 66, and subtracts 12 from the display position in step 68.

The result of the subtraction is determined to be positive or negative in step 70.

If the subtraction result is positive, one black section - is displayed at the position of the display instruction point (step 72).

After displaying the black section, the display instruction point moves to the next section (step 74), and the process returns to step 68.

If the subtraction result is negative in step 70, the process goes to step 76, where 12 is added to the subtraction result.

In step 78, it is determined whether the addition result is zero, and if it is zero, a plurality of white section openings are displayed in step 80.

The number of white sections is determined by the magnification rate, but as mentioned above, when the magnification rate is 1.2.4, the number of white sections is 14° and 7.4, respectively.
It is.

After displaying a plurality of white sections, one black section is displayed in step 82, and the display pointing point moves to the next section (step 84).

Check whether the display of instruction information is completed in step 86.
The PU 24 makes a determination, and if it is not completed, step 82
and if completed, stop the operation.

Now, returning to step 78, if the force calculation result is zero, the first black and white division A is displayed in step 88.

The first black and white segment has a black portion on the left and a white portion on the right.

In step 90, the display instruction point moves to the next section, and similarly to step 80, the white section opening is displayed in step 92.

Next, in step 94, one second black and white section 4 is displayed.

The second black-and-white section is the reverse of the white and black portions of the first black-and-white section.

In step 96, the display point is moved to the next section, and the process proceeds to step 86.

Accordingly, the display bar is divided into 21 sections, with 2 sections containing black and white portions (steps 88 and 94).

FIG. 10 is a flowchart illustrating a method of displaying trigger points.

First, the CPU 24 detects the trigger point (step 98).
, rPO8TJ) Determine whether Riga mode is on (
Step 100) If the "PO8T" trigger mode is selected, the display pointing point moves to the left end of the pointing bar (Step 1
02) rPREJ) 1.1 If the mode is set, the display instruction point moves to the right end of the instruction bar (step 106).

In step 104, a trigger point indication mark (roi) is displayed at the trigger point.

In this way, the display of the trigger point is completed.

As described above, the present invention displays a portion of a logic signal stored in a storage device and simultaneously displays which portion of the stored logic signal the displayed portion corresponds to.

Therefore, the logic analyzer to which the present invention is applied can store more bits of logic signals than the storage capacity determined by the display area and resolution of the display device.

Furthermore, the operator can easily confirm the relationship between the storage capacity and the enlarged portion using the instruction information according to the present invention.

Furthermore, since the instruction information is linear, the width may be narrow and the display area may be small.

Therefore, even if the instruction information and the logic signal are displayed simultaneously on the display means, the display of the instruction information does not interfere with the display of the logic signal.

Although one embodiment of the present invention has been described above, modifications and changes to this embodiment will be obvious to those skilled in the art.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a logic signal measuring device to which the method of the present invention is applied, and FIGS. 2 to 8 briefly show the display displayed on the display device of FIG. 1 in order to explain the present invention in detail. 9 and 10 are flowcharts for explaining the present invention, respectively. 10... Take probe, 12... Input circuit, 1
4... High-speed storage device, 16... Word recognizer (WR), 18... Clock oscillator, 22...
Keyboard, 24...CPU, 26...Bus, 28
...Programmable counter, 30...CPU
RAM. 32...ROM, 34...Display RAM, 36...
Display device, 38...Display formatter 40...
power supply.

Claims (1)

[Claims] 1. Storing a logic input signal in a storage means, selecting a part of the stored logic signal, and adding linear instruction information indicating the relationship between all the stored logic signals and the selected part of the logic signal to the selected part. 1. A method for displaying a logic signal in a logic signal measuring instrument, characterized in that a part of the logic signal is displayed simultaneously on a display means.