GB2066030A - Method of displaying logic signals and a logic signal measurement apparatus - Google Patents

Abstract

Logic signal measurement apparatus has a memory for storing logic signals, a part of which can be selected for display, at a controllable magnification, simultaneously with an indication of the relationship of the selected part to the rest of the logic signals. Preferably, the indication is a bar consisting of black and white zones along its length which represents the entire memory capacity. An indication of the trigger point may also be provided. The logical states of the elements in the parallel memory channels (eight) corresponding to the white part of the bar are displayed in lines 0-7. <IMAGE>

Description

SPECIFICATION Method of displaying logic signals and a logic signal measurement apparatus This invention relates to a method of displaying logic signals and a logic signal measurement apparatus.

The recent progress in digital technology makes measurement of digital signals increasingly important like that of analog signals. Logic signal measurement apparatus or logic analyzers are particularly suited for adjustment and maintenance of digital equipment such as digital computers, desktop calculators, computer terminals, digital control units, etc. The capabilities of logic analyzers for measuring logic signals before a triggering signal and for generating a trigger signal when input logic signals agree with a predetermined logic pattern are convenient for measuring logic level as well as time relationship of logic signals in data and address buses of a digital equipment under test.

Logic analyzers are designed to store a plurality of logic signals in memory means such as IC memories before displaying such stored logic signals on suitable display means such as a cathode-ray tube. Among various other modes, logic analyzers have a parallel timing mode for displaying the stored logic signals in a timing diagram. Memory capacity of logic analyzers can be expanded rather easily for acquiring a larger number of logic signals, but a finite display area of the display means decreases the resolution when the entire stored data are displayed at once, thereby restricting the number of logic signals to be displayed in a timing diagram. Memory capacity of conventional logic analyzers depends upon the available display area of the display means and the required resolution.In other words, one disadvantage of conventional logic analyzers is the incapability of storing large bits of input logic signals to display in a timing diagram.

The detailed observation of one part of the stored logic signals is made by expanding the display timebase. Two approaches are available for expanding the timebase: one is to increase the gain of the horizontal amplifier with controlling d.c. level for selecting the part to be magnified like an oscilloscope, while the other is to vary the display clock frequency with controlling the address signal of the memory means for selecting the magnifying location. The latter technique may be more convenient than the former because the magnification factor and magnifying location can be controlled digitally. In addition, the relation between the magnified and unmagnified portions as well as the relation between the magnified portion and the trigger point can conveniently be displayed by digital means.Some conventional oscilloscopes have a display mode for displaying a selected partial waveform to be magnified with higher intensity from the rest of the waveform before displaying the magnified waveform, but both magnified and unmagnified waveforms cannot be displayed simultaneously. Although some oscilloscopes have an alternate mode capable of displaying both of these waveforms, this technique cannot be applied to logic analyzers having a large number of input channels and a limited display area. It should be noted that conventional oscilloscopes normally have two input channels while logic analyzers have 8, 16, 32 or more input channels. In addition, no digital information representing the magnification factor and magnifying location is available in a magnifying method by controlling the gain of the horizontal amplifier.Conventional oscilloscopes display the input signal only after a trigger point, therefore no need arises for indicating the relation between the input part to be magnified and the trigger point.

Some conventional logic analyzers use a marker in the unmagnified mode to indicate the start point of the part of the input signal to be magnified. A large number of input channels makes it impossible to display simultaneously the magnified partial input as well as the positional relation of the input before and after magnification.

It is, therefore, one object of this invention to provide a method of displaying logic signals for a logic signal measurement apparatus wherein one part of the logic signals stored in memory means is displayed with magnified scale while simultaneously displaying the indication information for indicating the relation of the magnified part with respect to the entire logic signals.

It is another object of this invention to provide a method of displaying logic signals for a logic signal measurement apparatus capable of storing more bits than conventional storage bits which are determined by the display area and resolution of display means.

It is still another object of this invention to provide a method of displaying logic signals for a logic signal measurement apparatus for simultaneously displaying the magnified display and the indication information indicating the relation of the signal before and after magnification.

According to one aspect of the invention there is provided a method of displaying logic signals, comprising the steps of: storing logic input signals in memory means; displaying a selected part of the stored logic signals on display means; and displaying indication information simultaneously with said selected part of said logic signals on said display means, said indication information indicating the relationship of said selected part to the rest of the said stored logic signals.

According to another aspect of the invention there is provided logic signal measurement apparatus having means for storing logic signals, and means for displaying part of the stored signals and an indication of the relationship of the displayed part to the rest of the stored signals.

The indication information used in a preferred embodiment of the invention is a linear bar (or an indication bar) of a certain length representing the total memory capacity of memory means with an indication for indicating what part of the logic signals in the memory means is actually displayed.

It should be noted, however, that the indication bar is narrow enough to be displayed with a plurality of logic signal waveforms.

An embodiment of the present invention will be described in detail hereinafter by reference to the accompanying drawings, in which: Fig. 1 is a block diagram of a logic signal measurement apparatus of the invention; Figs. 2 through 8 show examples of displays on the display unit of the apparatus; and Figs. 9 and 10 are flow charts for describing the operation of the apparatus.

In Fig.1, data probe 10 includes eight active or passive probes each connected between an input terminal for eight channels (channel O to 7) and a respective probe tip. The output of data probe 10 is applied to both high speed memory 14 and word recognizer (WR) 16 through input circuit 12.

WR 16 receives logic signals from terminal 20 and also a reset signal from bidirectional bus 26. The output of WR 16 is applied to programmable counter 28 whose output is then applied to high speed memory 14. As is apparent from Fig. 1, connected to but 26 are memory 14, clock generator 18, prosrammable counter 28, central processing unit (CPU) 24, keyboard 22, read only memory (ROM) 32, CPU random access memory (RAM) 30 and display RAM 34. The output of display RAM 34 is applied to raster display unit 36 for displaying it through video display formatter and driving circuit 38. Although not shown in Fig.

1, clock generator 18 and power supply 40 are coupled to all or some of the aforementioned blocks.

In operation, a display as shown in Fig. 2 appears on the display screen of display unit 36 when power switch is turned on. The display "PRL TIMING" in Fig. 2 means a parallel timing display mode of parallel logic input signals. The present logic analyzer further includes parallel and serial state modes and a signature mode. " < HEX > " means the hexadecimal parameter setting out of the other available binary, octal and decimal parameter settings. "SMPL" means that the input logic signals are being sampled on the edges of the clock signal. In addition to the "SMPL" mode, there is a "LATCH" mode which is identical to the "SMPL" mode except that any signal transitions such as narrow noise (glitches) during a clock signal interval change the next logic bit. "POST" means that logic signais after the trigger signal are selected.Other than the "POST" mode, "PRE" mode of operation is also available for selecting logic signals only before the trigger signal. "POS" means the positive logic mode, but the negative logic mode can also be selected. "DATA 1B1 = XX" at the second line on the display screen in Fig. 2 shows that the operator should set in WR 16 at the location "XX" an input logic signal combination (characteristic value) in hexadecimal ( [ #i ] means hexadecimal) to be provided to data probe 10.For setting numbers in binary, octal or decimal, the display will be 1!31, [ IB, or Ct respectively. "DLY lilil = #" indicates that the operator set the programmable counter 28 to logic delay for setting a characteristic value at the location "#" in hexadecimal. "EXT ED = X" at the third line on the display screen shows the logic signal combination to be applied to terminal 20, and the operator sets a hexadecimal number at the location "X". "SMPL = 5~ ns" shows that the sampling period is 50 ns. Numbers 0 through 7 at the left side of a plurality of horizontal lines represent the channel numbers.

Now, the operator pushes keyboard 22 to select necessary parameters. CPU 24, then, processes the signal entered from keyboard 22 in accordance with the instructions stored in ROM 32 and transfers the parameter information to display RAM 34. The information stored in display RAM 34 is recalled (or re-freshed) periodically for being displayed on display unit 36 after convertion into a television signal by video display driving circuit 38. Let assume that the operator entered the following parameters: the logic combination of WR 16 to data probe 10 being "3F", neglecting the signal from external terminal 20 (thereby leaving the display at right of "EXT IEI" to "X"), and digital delay and sampling period being respectively "2AGF" and "5,us". The display as shown in Fig. 3 will result if the start button of keyboard 22 is pushed.

The logic level of the input signal detected by data probe 10 is converted to a desired level such as TTL (transistor transistor logic), ECL (emitter coupled logic), etc. by input circuit 12 comprising comparators for making judgement of the input logic level thereto. The waveform shaped logic signal from input circuit 12 is applied to high sneed memory 14 and WR 16. Memory 14 stores the output from input circuit 12 in synchronism with the clock pulse (having a period of 5 ys or a frequency of 200 kHz in this particular embodiment) from clock oscillator 18. When the input signal agrees with the logic combination "3F" set in WR 16, a first control signal is generated by WR 16 to be supplied to counter 28.

This first control signal initiates counter 28 to count the clock pulses. The memory capacity per channel is 252 bits in this particular embodiment.

The "POST" trigger mode is designed to store 12 bits preceeding the trigger pulse. Thus, counter 28 counts 2A6F (equivalent to 10863 in decimal) + (252 - 12) (both decimal) before generating a second control signal to be applied to memory 14. If "PRE" trigger mode were selected, 12 bits after the trigger signal are also stored and counter 28 counts "2AGF" + 12 (decimal) before generating the aforementioned second control signal. The digital delay time in this particular example is 5 yes x 2A6F = 53.15 ms in decimal.

Both WR 16 and programmable counter 28 are controlled by keyboard 22 by way of CPU 24 and bus 26. On receiving the second control signal, memory 14 stops storing the input logic signals.

This means that memory 14 stores only logic signals before the occurrence of the second control signal. The data stored in memory 14 is transferred to CPU RAM 30. As mentioned hereinbefore, the resolution and display area limitations of raster display unit 36 allows only 168 bits to be displayed despite the memory capacity of 252 bits per channel. This means that only fraction of the stored data can be displayed on raster display unit 36 (see Fig. 4).

There arises needs to identify the displayed data with respect to the entire stored data corresponding to the memory capacity. A push of a window button in keyboard 22 will display "WDO" representing the window mode, 1 68 bits of the input data and an indication bar. The entire length of the indication bar represents the maximum memory capacity while the white zone, black zone and "0" represent respectively the displayed part, non-displayed part of the stored logic signals and the trigger point. These informations are processed by CPU 24 upon receiving instructions therefrom.

If the window button is pushed again, the timebase of the display is expanded as shown in Fig. 6. The magnification factor is 168/84 = 2. In this case, each bit of the data stored in CPU RAM 30 is transferred to display RAM 34 at every two clock pulses, thereby modifying the contents of display RAM 34. As shown in Fig. 7, another push of the window button will magnify the display waveform by the factor of four with respect to Fig.

5. Each bit of the data stored in CPU RAM 30 is transferred to display RAM 34 at every four clock pulses. A position control in keyboard 22 controls the part to be displayed. The position control signal from keyboard 22 is sensed by CPU 24 which selects the address of CPU RAM 30 in response to the position control signal when the data within CPU RAM 30 is transferred to display RAM 34. Fig. 8 shows how the indication information display varies as the display position is controlled. Where, Fig. 8A and B are in the "POST" trigger mode while Fig. 8C through G are in the "PRE" trigger mode.

Fig. 9 is a flow chart for explaining the method of displaying the indicator information according to this invention. When the window mode is selected, the display indicator point moves to the left end of the indication bar in step 50 and CPU 24 judges in step 52 whether the magnification factor is unit or not. The indication bar is divided into 21 distinctive sections each comprising 12 byte. With the unity magnification factor, the unmagnified mode displays 168 byte (168 bit x 8 channel = 12 bit x 14 section) CPU 24 counts 14 sections in step 54. With any modes other than the unity magnification factor, CPU 24 judges whether or not the magnification factor is 2. If the magnification factor is judged to be 2, 84 byte data (84 bit x 8 channel = 12 bit x 7 section) are displayed and CPU 24 counts 7 sections in step 58.If the magnification factor is not 2, CPU 24 judges in step 60 whether or not the magnification factor is 4. In the magnification factor of 4. 42 byte data (42 bit x 8 channel = 12 bit x 4 section) are displayed with CPU 24 counting 4 sections in step 62. If the magnification factor is not 4, step 64 leads the system to automatically perform the magnification mode in step 62, thereby avoiding any system error.

The foregoing descrition reveals that the display position can be controlled by the position control in keyboard 22. Now, CPU 24 senses the display position in step 66 and the subsequent step 68 substracts 12 from the display position.

Step 70 judges whether the result is positive or negative.

One black section 1 will result at the display indicator point in step 72 if it is positive. After displaying the black section, the display indicator point advances to the next section in step 74 before returning to step 68. If the subtration is negative in step 70, however, step 76 is performed to add 12 to the result of the subtraction. A judgement is made in step 78 whether the addition is equal to zero or not. If it is zero, a plurality of white sections 0 will be displayed in step 80. The number of white sections solely depends on the selected magnification factor, which is 14, 7 and 4 respectively for 1, 2 and 4 magnification factors.

After displaying a plurality of white sections, one black section is displayed in step 82 and the display indicator point advances to the next section in step 84. CPU 24 judges in step 86 whether or not the display of the indication information has been completed. The operation returns to step 82 if not completed, but stops if completed.

Returning now to step 78, a first black and white section 1 ] with black at the left half and white at the right half will be displayed in step 88 if the result of the addition is not zero. The display indicator point advances to the next section in step 90 and displays a white section 0 in step 92 similar to step 80 Then, a second black and white section 08 with opposite black and white relation to the first black and white section is displayed in step 94. The display indicator point advances to the next section in step 96 to perform step 86. the indication bar is, therefore, divided into 21 sections including two black and white sections in steps 88 and 94.

Fig. 10 illustrates a flow chart for explaining how a trigger point is displayed. Firstly, CPU 24 deteects the trigger point in step 98 for judging in step 100 if the "POST" trigger mode is selected.

The display indicator point moves in step 102 to the left end in the "POST" trigger mode while to the right end in step 106 in the "PRE" trigger mode. A trigger point indication mark "0" is displayed in step 104 at the trigger point, thereby accomplishing the trigger point display.

As described hereinbefore, this invention is intended to display a selectable part of the logic signals stored in the memory simultaneously with the relative position of the selected part in the entire logic signals. A logic analyzer to which this invention is applied stores logic signals exceeding the memory capacity determined by the display area and resolution of the display unit. In addition, the present invention provides the operator with means for conveniently identifying the relative position of the part to be magnified and the memory capacity.

Although one preferred embodiment is illustrated and described hereinbefore, a person skilled in the art will understand that various modifications can be made without departing from the subject matter of this invention.

Claims (10)

1. A method of displaying logic signals, comprising the steps of: storing logic input signals in memory means; displaying a selected part of the stored logic signals on display means; and displaying indication information simultaneously with said selected part of said logic signals on said display means, said indication information indicating the relationship of said selected part to the rest of said stored logic signals.

2. A method according to claim 1, wherein said indication information is in the form of a bar graph having a length representing the memory capacity of said memory means or said entire stored logic signals.

3. A method according to claim 2, wherein said bar graph is modulated for indicating said selected part.

4. A method according to any preceding claim, further comprising the step of: selecting the part of the logic signals to be displayed from the stored logic signals.

5. A method according to any preceding claim, further comprising the step of: changing the magnification factor of the displayed logic signals by changing the memory capacity of said memory means for the logic signal to be displayed.

6. A method according to claim 5 further comprising the step of: indicating the capacity of said memory means by a numerical display.

7. A method according to any preceding claim, further comprising the step of: displaying trigger information simultaneously with said indication information on said display means.

8. Logic signal measurement apparatus having means for storing logic signals, and means for displaying part of the stored signals and an indication of the relationship of the displayed part to the rest of the stored signals.

9. A method of displaying logic signals, suostantially as herein described with reference to the accompanying drawings.

10. Logic signal measurement apparatus, substantially as herein described with reference to the accompanying drawings.