JP2002288005A - Trace data extracting method for debug and performance analysis - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem in a conventional trace data extracting method that it is impossible to extract the registered data over a long time to analyze conditions of a LSI and a device. SOLUTION: A trace data storing means 8, an address counter 3 and a recording interval counter 4 are mounted, or an OR circuit 2, an AND circuit 21, a reading condition mode flag 6, a reading command flag 61 and the like of event flags 111-114 are mounted as a control means. The control means writes the condition of a group of registers 121-124 and a recording interval counter value on the storing means 8, in detecting the switching-on of any one of the event flags 111-114, and steps the address counter 3, and resets the recording interval counter 4, and the recording interval counter 4 counts up every cycle when the writing does not exist, whereby the conditions of the group of registers 121-124 only in a cycle during the operation is extracted with the recording interval.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for collecting a register state inside an LSI or a register state inside a device, and more particularly to a functional final debug evaluation of an LSI having a large-scale processing function and analysis of performance problems. And a method of collecting trace data for performing the operation.

[0002]

2. Description of the Related Art Conventionally, when a new LSI is developed, functional debugging is mainly performed by simulating a functional description of the LSI using a test pattern at the design stage.

For example, even in a large-scale LSI for realizing a high-speed processor, a prototype LSI is manufactured after the basic functions are debugged in advance in the design stage. However, in such an LSI, it is necessary to carry out final evaluation close to the actual use environment before mass production in order to identify rare bugs and performance problems. The LSI is evaluated using an operating system and a number of application programs.

In such an evaluation debug, a tracer for sampling a register state is incorporated in an LSI so that analysis can be easily performed when an operation failure or insufficient performance is detected (especially when a clock cycle is extremely small, The method of sampling from an I / O terminal to an external tracer via a probe cannot be collected accurately.

However, in a conventional tracer with a built-in LSI, a series of processing of a problematic program is executed and the data is stored every cycle, despite the limited capacity of the trace data storage unit because of the built-in LSI. In some cases, overflow may occur and only a part of a series of processes can be traced.

[0006]

In the above-described conventional trace data collection method, among the plurality of registers provided in the LSI, the output of the register necessary for state analysis is recorded every cycle in the wrap round. Due to the limitation of the amount of hardware that can be mounted, there is a problem that only register state data at short time intervals can be collected.

An object of the present invention is to extend the trace time of the register state inside the LSI without greatly increasing the hardware scale, and to devise mainly so as not to collect data unnecessary for analysis. Realizes sampling of register status for a long time.

[0008]

According to a first trace data collecting method of the present invention, a state of registers included in a logic section is collected as trace data. An address circuit for creating and holding an address at the time of writing is provided, and a control means is provided. When the registers are grouped into a plurality of register groups for functional operation, each of the register groups is in operation. A part of the bits of the registers indicating an event flag is used as an event flag, and the state of the registers is written into the trace storage means only in a cycle in which any bit of the event flag is turned on, and the address circuit is advanced, The state of the registers is collected only in the cycle of (1).

According to a second trace data collecting method of the present invention, in the first trace data collecting method, there is provided the trace data storing means, the address circuit, a recording interval counter, and a control means. When it is detected that any of the event flags is on, the state of the registers and the recording interval counter value are written to the storage means, the address circuit is incremented, the recording interval counter is reset, and the recording interval counter is reset. Is characterized in that, if there is no writing, the cycle counts up every cycle, and the states of the registers and the like are collected together with the recording interval only during the operating cycle.

A third method of collecting trace data of the present invention is a method of collecting the state of registers included in a logic section as trace data, and creates a trace data storage means and an address for writing to the storage means. An address circuit, a recording interval counter, and control means. The control means, when the registers are grouped into a plurality of register groups for functional operation, indicates that each register group is in operation. A part of bits of the registers as an event flag, comprising: an ON flag for detecting any bit of the event flag; a continuation detecting unit for detecting continuation of the event flag value; and a continuation cycle number counting unit. If the state of registers is collected together with the recording interval only during the middle cycle and the event flag value continues for 3 or more cycles, Is characterized in that collecting is degenerated to the recording of the record and the last cycle of the continuation of the first cycle.

According to a fourth trace data collecting method of the present invention, in the third trace data collecting method, the trace data storing means, the address circuit, the recording interval counter, and the control means are provided. The means has ON detection means for any bit of the event flag, continuation detection means for detecting the continuation of the event flag value, and counting means for the number of continuation cycles. If not, the state of the registers and the flag value indicating that the count is the recording interval and the recording interval count are written into the trace storage means, the address circuit is stepped up, the recording interval counter is reset,
If it is the third cycle after the ON detection and continuation,
The output of the address circuit is replaced with the write address of the second cycle of continuation, the state of the registers and a flag value indicating that the count is a continuation count and the continuation count are written in the trace storage means, and the recording interval counter is reset. It is characterized by doing.

A fifth trace data collecting method according to the present invention is the third trace data collecting method, further comprising a trace data storage means, the address circuit, the recording interval counter, and the control means. The means has a degeneration mode flag in addition to the on detection means for the event flag, the continuation detection means, and the continuation cycle number counting means. If the degeneration mode flag is set, the event flag value continues for three or more cycles. In this case, data is collected by degenerating into the recording of the first cycle of the continuation and the recording of the last cycle.

According to a sixth aspect of the present invention, there is provided the trace data acquisition method according to the second, third, fourth, or fifth trace data acquisition method, wherein the trace data is stored in an LSI including the logic unit. Means, the address circuit, the recording interval counter, and the control means.

According to a seventh trace data collecting method of the present invention, in the sixth trace data collecting method, the trace data storage means, the address circuit, and the recording interval counter are provided in an LSI including the logic part. And the readout register of the trace data storage means. At least the address circuit and the readout register have a normal path and a shift path input which is valid exclusively in the shift mode in addition to the normal input. It has a read state flag that is set only at shift-in in the shift mode, and a read instruction flag that is set at shift-in in the shift mode and is reset by a clock signal after the shift mode is released. Shift-in of the read instruction flag and reading of the storage means after releasing the shift mode are alternately performed. Wherein the reading the trace data storing means.

[0015]

Next, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows an LSI of the present embodiment.
FIG. 3 is a block diagram showing a built-in trace data collection method.

Referring to FIG. 1, the logic section 1 includes a large number of registers (sequential circuits such as registers, counters, and control flip-flops that operate on a clock). Registers necessary for state analysis of these LSIs are, for example, L
Divided into a plurality of blocks by the function in SI, and each is divided into GRP (group) -A register group 121, GR
PB register group 122,... GRP-D register group 1
24.

If the LSI is a processor, for example, an instruction cache unit, an instruction code decoding unit, an address calculation unit,
Operand data preparation unit, register operand preparation unit,
It is divided into functional blocks such as a paging mechanism, an operand cache, an operation processing start unit, various operation units, a register update unit, an instruction counter unit, a program status register unit, and an interrupt processing unit. Each block is one register group.

Then, for each block, an event flag indicating that it is operating is selected. In FIG. 1, the event flag of each group is set to 1 to simplify the description.
Although a bit is used, the present invention is not limited to this. It is only necessary that a set of event flags cover the in-operation display of each block.

In this embodiment, as the control means, the OR circuit 2, the AND circuit 21, the OR circuits 31, 41, the read state flag 6, the read instruction flag 61, and the AND circuits 22, 6
2 and the address circuit is an address counter 3.

When an event flag to be collected in the A register group composed of a plurality of bits is turned on, the output of the event flag is output to an OR (logical sum) circuit 2.

When the OR circuit 2 receives the event flags 111 to 114 of the respective register groups, the OR circuit 2 performs an OR operation on the received event flags, and if the trace ON state (from the start of the trace to the end of the trace), the AND circuit 21 outputs the data. Outputs a registration instruction and stores trace data and recording interval 8
Instructs writing to. Further, it outputs a reset instruction to the recording interval counter 4.

The output of the address counter 3 is connected to the address of the storage means 8, and specifies the address at the time of data registration. When the data registration instruction is received, an increment operation is performed, and the address output is incremented by +1 in the next cycle.

The recording interval counter 4 is an increment counter that counts up every cycle in synchronization with a clock and resets the counter in the next cycle after receiving a counter reset instruction.

The storage means 8 receives the instruction signal from the AND circuit 21 and records the output of each register group to be collected and the output of the recording interval counter 4.

The read register 9 is a register used when reading data and recording intervals stored in the storage means 8. For example, as shown in the figure, the upper data of the storage means 8
The number of bits is reduced by sequentially reading out lower-order data.

A read state flag (RMDF) 6 indicates a read mode of the storage means 8 and is a flip-flop which is turned on / off only at shift-in. I have.

The read instruction flag (RDF) 61 is a flip-flop which is turned on for only one cycle of reading of the storage means 8 and which can be shifted in and whose normal input is "0".

The flip-flops constituting each register group, the address counter 3, the recording interval counter 4, the read flag 6, and the read register 9 of the logic section 1 have a shift-in input in addition to a normal input. In the shift mode, the normal input is disabled, the shift-in input is enabled (enabled), and the register group, counter, and register operate as one shift register in synchronization with the clock.

Therefore, in the read operation, when the leading address to be read into the address counter 3 is shifted into the read instruction 61 by "1", the normal mode (shift mode is turned off) and the clock is supplied, only the first one cycle is read. Since the instruction 61 is on, the data of the head address is read into the read register 9 and the address counter 3 counts +
1 is done.

Then, the value of the read register 9 is shifted out and the data is read. Thereafter, data of the storage means 8 is sequentially read by repeating a series of operations of shifting in the read instruction flag 61 by “1”, returning to the normal mode, supplying a clock, and shifting out the read register 9. By doing so, it is devised that the number of input / output terminals of the LSI for reading does not increase.

Next, a specific example of this embodiment will be described with reference to the timing chart of FIG. 2 and the image of the storage means 8 of FIG. It is assumed that the register groups A to D are composed of a 1-bit event flag and 2-bit data (actually, the event flag has 1 to 2 bits,
The data is several tens of bits or more, but is simplified for convenience of explanation).

First, both the address counter 3 and the recording interval counter 4 are reset in the set cycle in the trace ON state. Assuming that the next cycle is clock 0, when the event flag of register group B is set at clock 0, AND circuit 21 outputs a registration instruction to storage means 8 and a reset instruction of recording interval counter 4. . At this time, the address indicated by the address counter 3 is “00”, and the outputs of the register groups A to D output at the time of clock 0 and the output “00” of the recording interval counter 4 are “00” of the storage device. Registered in.

When the address counter 3 receives the registration instruction from the AND circuit 21, it is incremented by one in the next cycle to become "01". When receiving the registration instruction, the recording interval counter 4 is reset to “0” in the next cycle.

Thereafter, in the cycles of clocks 1 to 3, the event flags of any of the register groups are set.
The data of all the register groups in each cycle and the interval count “0” are sequentially written to the addresses “01” to “03” of the storage means 8.

In the cycles of clocks 4 to 7, since all event flags are reset, the registration instruction is off, the address counter 3 is held at "04", and the registration interval counter 4 counts up every cycle.

When the event flag of the register group C is set at the clock 8, the AND circuit 21 outputs a registration instruction and similarly writes it at the address "04" of the storage means 8, counts up the address counter 3, and sets the recording interval. The reset instruction of the counter 4 is output. Clock 9-1
In one cycle, the event flag of one of the register groups is set, and the address “05” of the storage unit 8 is set.
To "07".

FIG. 3B shows a trace image according to the conventional method. As shown in the figure, the register values in each cycle of clocks 0 to 11 are stored at addresses “00” to
"11" is sequentially written.

Therefore, in the present embodiment, what used to be addresses 0-11 in the past can be collected at addresses 0-7, and it is possible to collect LSI internal data for a longer time than in the conventional method.

In this embodiment, the register groups A to D, the address counter 3, the recording interval counter 4, the read state flag 6,
The read instruction flag 61 and the read register 9 have a shift path, and the output of the read register 9 is read by the shift path. However, in other embodiments, the present invention is not limited to the shift path and the reading by the shift path.

Still another example of the present embodiment is a method of collecting trace data of an apparatus, which has the same configuration as that described above, but a storage means for collecting the states of the logic unit 1 and the registers of the logic unit 1. 8, the address counter 3, the recording interval counter 4, and the control means need not be LSIs, but may be circuits on a wiring board.

Next, a second embodiment of the present invention will be described with reference to the drawings. In the present embodiment, when the trace mode is switched to the degenerate mode, if any one of the event flags is on and the value of the event flag as a whole continues without changing, the second and subsequent cycles of the event flag having the same value are set to 1 cycle. This is a method in which a function of recording in a reduced manner in an entry is added.

At the time of degeneration, the number of continuations (0 origin)
Is stored in the storage means 8 instead of the recording interval count.
Therefore, a 1-bit flag indicating whether the value of the count field is a recording interval or a continuous count is added as write data to the storage means 8. If the count value is a recording interval, this flag is set to "0". If it is a continuous count, it is stored as "1".

FIG. 4 is a block diagram showing a trace data collecting method built in an LSI according to the present embodiment. In the present embodiment, as the control means, an OR circuit 2, an AND circuit 21,
OR circuit 41, read state flag 6, read instruction flag 6
1, in addition to the AND circuits 22 and 62, a count-up logic circuit of the address counter 3, a strobe logic circuit of the spare address register 32, and a selection logic circuit of the selectors 33 and 42 are provided.

The logic circuit shows only the logic formula. The logical expressions #,..., + Represent NOT (negation), logical product, and logical sum, respectively.

The control means includes, as means for detecting the continuation of all bit values of the event flag, a copy EF register 51 for holding the event flag value of each register group in the previous cycle, It has a matcher 52 for detecting a match, and has a continuous counter 5 that counts up with a match output of the matcher 52 and is reset if the match output is off as a means for counting the number of continuous cycles.

The output of the continuation counter 5 is input to the selector 42, and the selector 42 counts the 0-recording interval count (−
Indicates bit combination) and 1-continuation count,
Write to the storage means 8. Accordingly, the flag is set to "0" when writing the recording interval as a count, and is set to "1" when writing a continuous count.

Further, the control means has a degeneration mode flag (SMD) 7 for indicating the degeneration mode.

As an address circuit, an address counter 3
And a reserve address register 32 that keeps track of the value of the address counter 3 in the second cycle in which the event flag value continues, and a selector 33 that switches between the output of the address counter 3 and the output of the reserve address register 32.

The count-up condition of the address counter 3 is the same registration instruction as described above unless it is in the degenerate mode. In the degenerate mode, the continuous count is 0 (the output of the continuous counter 5 is 0) or the coincidence output is off. It is time to register. That is, in the first and second cycles in which the same event flag value continues, a count-up instruction is issued,
Thereafter, it is suppressed.

The reserve address register 32 strobes when the continuation count is 0, the match (output of the matcher 52) is on, and there is a registration instruction. That is, the strobe is performed in the second cycle in which the same event flag value continues.

In the selector 33, if the continuous count is not 0 in the degenerate mode and the coincidence output is on, the spare address register 32 is selected and used as an address to the storage means 8. That is, in the third and subsequent cycles in which the same event flag value continues, the reserve address register 32 is selected, and the second and subsequent cycles update the write continuation count to the same address.
The selection logic of the selector 42 is the same as that of the selector 33.

Next, a specific example of the present embodiment will be described with reference to the time chart of FIG. 5 and the image of the storage means 8 of FIG. 6A. It is assumed that the configurations of the register groups A to D are the same as described above.

First, the address counter 3 and the recording interval counter 4 are both reset in the trace ON set cycle, and when the next cycle is clock 0, the event flags of the register groups A, B, C, and D are sequentially set in clocks 0-3. Is done. Therefore, in each cycle of clocks 0 to 3, the AND circuit 21 outputs a registration instruction, an increment instruction of the address counter 3 and a reset instruction of the recording interval counter 4 to the storage means 8. As a result, “0” as a flag indicating the meaning of the data and the count value of each cycle and “0” as the recording interval count are stored in the storage unit 8.
Are written to the addresses "00" to "03".

At clocks 3 to 6, the coincidence output is turned on because the event flag values of the register groups A to D are "0011" and at clocks 4 to 6, the event flag values of the previous cycle continue. Based on the coincidence output, the continuous counter
Are counted up to 1, 2, and 3 from clocks 5 to 7.

The count-up instruction of the address counter 3 is turned on at the clock 4, but is suppressed at the clocks 5 and 6 where the coincidence count is 1 or more and the coincidence output is on. At clock 8, since all the event flags are off, the registration instruction is not output and is suppressed. Therefore, the address counter 3 becomes "4" at the clock 4, becomes "5" at the clock 5, becomes "6" at the clock 8, and becomes "7" at the clock 10.

At the clock 4, the continuation count is 0 and the coincidence output is on, and the value “4” of the address counter 3 is strobed to the spare address register 32.

In the cycles of clocks 5 and 6 in which the continuation count is not 0 (1 or more) and the coincidence output is on, the selector 33 selects the copy address register 32. As a result, in the cycles of clocks 5 and 6, writing to the same address "04" as in the cycle of clock 4 is performed.

Similarly, in the cycles of clocks 5 and 6, the selector 42 is made to select the above-mentioned "1-continue count". As a result, "04" is obtained in the cycles of clocks 5 and 6.
The address flag is set and the continuation count is updated.

By the above operation, the storage means 8 is stored in FIG.
Data, flags, and counts shown in (A) are collected.

FIG. 6B shows a trace image according to the method of the first embodiment. Compared to this figure (A),
In (B), the records at addresses “04” to “06” are reduced to “04” in (A) and recorded.

As described above, if tracing is performed in the degenerate mode,
At least the state of the event flag can be collected for a longer time. Therefore, investigation of the cause of malfunction,
Even if the entire processing sequence to be investigated and analyzed in the initial stage of performance analysis is large-scale, if the trace is performed in the degenerate mode, the outline of the operation of the entire processing sequence can be grasped from the result.

If the processing sequence to be investigated and analyzed is narrowed down and detailed tracing is performed with the degeneration mode turned off, it is possible to efficiently investigate the cause of the malfunction and analyze the performance problem.

In another embodiment of the present embodiment, the present invention is not limited to the shift path and the reading by this. or,
Still another example of the present embodiment is a method of collecting trace data of an apparatus, which has the same configuration as that of FIG. 4, but has a storage unit 8 for collecting the states of the logic unit 1 and registers of the logic unit 1, an address counter, and the like. 3 and its peripheral circuits, the recording interval counter 4, the continuation counter 5, its peripheral circuits, and the control means need not be LSIs, but may be circuits on a wiring board.

In this embodiment, focusing on the event flag,
Since the value is degenerated when the value continues, the increase in the number of gates of the trace data writing function can be reduced. In addition, the delay time of the coincidence detection circuit and the like does not increase so much that the writing cycle of the storage means 8 is not affected as much as possible.

[0065]

According to the trace data collection method of the present invention, L
It is effective because grouping many registers of SI and device into multiple register groups, selecting event flag in each group, and recording the register group value together with recording interval only when any event flag is ON The first effect is that only the data and its generation timing are recorded, and the tracing can be performed for a longer time than before.

In the second embodiment of the trace data collection method of the present invention, in addition to the above, when the same event flag value continues, there is also provided a means for degenerating the recording of the continuous cycle and recording it. The second effect is that the outline of the register state of the target LSI or device can be collected for a longer time.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a trace data collection method with built-in LSI according to a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining a registration operation of a specific example of a trace according to the first embodiment of the present invention.

FIG. 3A is an image diagram of data collected in a storage unit 8 by a method according to the first embodiment of the present invention for a specific example;
(B) is an image diagram of data collected by a conventional method.

FIG. 4 is a block diagram showing a trace data collection method with a built-in LSI according to a second embodiment of the present invention;

FIG. 5 is a timing chart for explaining a registration operation of a specific example of a trace according to the second embodiment of the present invention.

FIG. 6A is an image diagram of data collected in the storage unit 8 according to the second embodiment of the present invention for another specific example, and FIG. 6B is an image diagram of data collected by the system of the second embodiment; .

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Logic part 3 Address counter 4 Recording interval counter 5 Continuation counter 6 Read state flag 7 Degeneration mode flag 8 Storage means 9 Read register 32 Reserved address register 33, 42 Selector 51 Reserved EF register 52 Matcher 61 Read instruction flag 111-114 Event flag 121-124 register group

Claims (7)

[Claims] 1. A method for collecting the state of registers included in a logic section as trace data, comprising a trace data storage means, an address circuit for creating and holding an address for writing to the storage means, and a control means. Prepared,
When the registers are grouped into a plurality of register groups for functional operation, the control unit sets a part of the bits of the registers indicating that each register group is operating as an event flag, and A trace data acquisition means for writing the state of the registers into the trace storage means only for a cycle in which any one of the bits is turned on, stepping through the address circuit, and collecting the state of the registers only during the operating cycle; method. 2. The apparatus according to claim 1, further comprising: a trace data storage unit, the address circuit, a recording interval counter, and a control unit, wherein the control unit detects a state of the registers and a recording interval when detecting that any of the event flags is on. The counter value is written into the storage means, the address circuit is incremented, the recording interval counter is reset, and the recording interval counter counts up every cycle if there is no writing, and the state of the registers and the like is changed only in the operating cycle. 2. The trace data collection method according to claim 1, wherein the data is collected together with the recording interval. 3. A method for collecting the status of registers included in a logic section as trace data, comprising: a trace data storage means; an address circuit for creating and holding an address for writing to the storage means; a recording interval counter; Control means, the control means, when the registers are grouped into a plurality of register groups in terms of functional operation, for each register group, indicates that it is in operation, some bits of the registers, As an event flag, it has an ON detection means for any bit of the event flag, a continuation detection means for detecting the continuation of the event flag value, and a means for counting the number of continuous cycles, and records the state of the registers only in the operating cycle. If the sampling is performed at intervals and the event flag value continues for three or more cycles, the recording of the first cycle of the continuation and the last A trace data collection method characterized in that collection is performed by degenerating into the record of the cycle. 4. The apparatus according to claim 1, further comprising: a trace data storage unit, said address circuit, said recording interval counter, and said control unit.
The control means has on-detection means for detecting any bit of the event flag, continuation detection means for detecting continuation of the event flag value, and count means for counting the number of continuation cycles. If not, a flag value indicating that the state and count of the registers are the recording interval and a recording interval count are written in the trace storage means, the address circuit is incremented, the recording interval counter is reset, and If ON is detected and the third and subsequent cycles are continued, the output of the address circuit is replaced with the write address of the second cycle of the continuation, and the state of the registers and a flag value indicating that the count is a continuation count and a continuation 4. The method according to claim 3, wherein the count is written into the trace storage means, and the recording interval counter is reset. Sudeta collection system. 5. The apparatus according to claim 1, further comprising a trace data storage unit, said address circuit, said recording interval counter, and said control unit.
The control means has a degeneration mode flag in addition to the event flag on detection means, the continuation detection means, and the continuation cycle number counting means. If the degeneration mode flag is set, the event flag value becomes three cycles. 4. The trace data collection method according to claim 3, wherein when the above continuation is performed, the data is collected by degenerating into the recording of the first cycle of the continuation and the recording of the last cycle. 6. An LSI including the logic unit, wherein the trace data storage means, the address circuit, the recording interval counter, and the control means are provided. 5. Trace data collection method described in 5. 7. An LSI including the logic unit includes the trace data storage means, the address circuit, the recording interval counter, the control means, and a read register of the trace data storage means. The read register has a normal input and a shift path input which is exclusively enabled in the shift mode. The control means includes a read state flag which is set only in the shift-in operation in the shift mode, and a shift-in flag in the shift mode. Set in
A read instruction flag which is reset by a clock signal after the shift mode is released, and alternately performs a shift-out of the read register and a shift-in of the read instruction flag, and a read of the storage means after the shift mode is released; 7. The trace data collection method according to claim 6, wherein the storage unit is read.