GB2124457A

GB2124457A - Improved data display apparatus

Info

Publication number: GB2124457A
Application number: GB08213415A
Authority: GB
Inventors: Thomas H Lecklider
Original assignee: Gould Advance Ltd
Current assignee: Gould Advance Ltd
Priority date: 1982-05-10
Filing date: 1982-05-10
Publication date: 1984-02-15

Abstract

Data display apparatus, such as a digital storage oscilloscope or a transient recorder, includes a smaller number of N-bit wide components than previous arrangements by utilising a single address counter 20 for providing both read and write address counts to the main store 10 of the apparatus. The address counter 20 alternates between read and write address modes, the address count not present in the counter at any one moment being held in a register 22. The address count in the counter is incremented selectively and presented to the main store 10, the address counts in the counter 20 and register 22 being periodically interchanged so as to alternate read and write addresses presented to the memory. This arrangement allows a convenient realisation of 'ROLL' and 'REFRESH' modes on the display. <IMAGE>

Description

SPECIFICATION Improved data display apparatus The present invention relates to improved data display apparatus of the type which may be used to display stored data in the form of a visual representation of a waveform, particular examples of such display apparatus being digital storage oscilloscopes and transient recorders.

Digital storage oscilloscopes (DSOs) and transient recorders, used to store and display low frequency waveforms, often present the sampled data (representative of the incoming waveform) in the 'ROLL' and/or 'REFRESH' modes. 'ROLL' simulates the appearance of an oscillograph or pen recorder where one edge of the oscilloscope cathode ray tube (CRT) corresponds to the 'pen' of the oscillograph. New data (the most recently sampled) appear at this edge and 'roll' across the face of the CRT towards the other edge, corresponding to paper motion in an oscillograph.

At any particular time, oldest data will be disappearing off one edge as new data appear at the other. 'REFRESH' mode presents exactly the same data as 'ROLL', but with respect to a different frame of reference. All data appear stationary on the CRT with only the transition between the oldest and newest words moving across the CRT. Both this motion of the transition point and the motion of all the data in 'ROLL' mode proceed at a rate proportional to that at which new data words are acquired.

The method by which the 'ROLL' and 'REFRESH' modes are generally implemented uses a random access memory (RAM) store in which data samples are stored, store access being time multiplexed between reading of existing data from the store and writing of new data into the store, such that read and write periods of equal length are alternated. However, since the read and write addresses at any one time are generally independent of each other and can increment at different rates, two N-bit counters are utilised (where the address busses to the memory are Nbit wide), one acting as a read address counter while the other acts as a write address counter.

Accordingly, an N-bit selector device also needs to be provided to choose between the outputs of the read and write address counters in accordance with the address time multiplexing. In the 'REFRESH' mode, new data samples are written in the memory, and read out effectively sequentially so as to provide the required transition movement effect between oldest and newest words. In the 'ROLL' mode, the outputs of the read and write counters are added together to generate a new effective display address and this provides the roll movement as existing data being displayed appear to move slowly across the screen, the display sweep being offset by the added-together new display address.The apparatus therefore requires an N-bit wide adder; furthermore, if the apparatus is to be selectable between 'ROLL' and 'REFRESH' modes (as well as the non-renewable storage mode), a number of further N-bit wide components, such as selector switches, latches etc" need to be included in the apparatus.

The present invention reduces the number of N-bit wide components required to implement the 'ROLL' and/or 'REFRESH' modes by providing a single N-bit address counter which alternates between read address and write address modes, and a storage means for holding one of the read and write address counts while the other is in the counter being incremented and subsequently being presented to the memory, the address counts in the address counter and storage means being periodically interchanged so as to alternate read and write addresses presented to the memory.

In such an arrangement, circuit complexity is traded against speed, the 'ROLL/REFRESH' part of the digital circuitry being greatly reduced in complexity (when compared to that previously proposed) by taking advantage of the speed of the simpiified circuit in accordance with a preferred embodiment of the invention.

The previous circuit reduces the complexity of the previous system by eliminating the majority of N-bit wide address buses. It does this by employing the single N-bit counter with outputs directly connected to the store (memory address inputs, and an N-bit storage register acting as the storage means with its inputs also connected to the address counter outputs, but its outputs connected to the address counter preset input.

The contents of the counter and the contents of the register may be interchanged, one for the other simultaneously. Control circuitry for this purpose comprises ordinary gates, latches, etc., but may be supervised by a microprogrammed fast (P)ROM. The requirements of the control circuitry may make this part of the apparatus rather complex, but this does not prejudice the effectiveness of this approach because it does not include N-bit wide busses or circuitry.

Features and advantages of the present invention will become apparent from the following description of an embodiment thereof, when read in conjunction with the accompanying single figure drawing which shows a block diagram of the preferred circuit.

Referring to the drawing, the circuit shows the store and address part of a digital storage oscilloscope according to the present invention. A main store 10 is responsive to a read/write multiplex counter 12 which is timed by a multiplex clock. The store 10 receives data from a conventinal analogue-to-digital (A/D) converter along the line 14 and has an N-bit wide parallel address input 1 6 which, in the write mode, deploys incoming data from the A/D converter to the required address location, and in the read mode, provides data stored in the chosen address location on a line 1 8 to the display output section of the oscilloscope.

A presettable N-bit address counter 20 has its output directly connected to the address input 1 6 of the store 10, and also to the input of an N-bit storage register 22. The output of the storage register 22 is in turn connected to the presetting input 24 of the address counter 20. Various clock and clear functions are provided to the address counter 20 and storage register 22 by a control circuit 26 which has an enabling input 28 receiving a control signal to be described.

The operation of the circuit in the 'REFRESH' mode will be described with reference to the following step sequence.

Sequence of steps of control circuit in 'REFRESH' mode 1. Set address counter and register to .

2. Set Display /write flat to display.

3. Synchronously enable RrW multiplex clock.

4. Read data word from Store. Write it to display.

5. Check if complete store has been transferred to display. Exit or continue.

6. Increment address counter.

7. Simultaneously: (a) Set Displayfl7rite flag to write.

(b) Preset address counter to register contents (current write address).

(c) Load register with next read address (previous contents of address counter).

8. Write to write address ] if'use this 9. Increment address counter sample' flag set 10. Simultaneously: (a) Set Displayfiwrite flag to display.

(b) Preset address counter to register contents (new read address).

(c) Load register with (next) write address.

11. Loop back to step 4.

Initially (step 1), the address counter 20 and register 22 are cleared to zero, then (step 2) the circuit is set in the display mode. The multiplex clock is enabled (step 3) to activate the multiplex counter 1 2. In step 4, the data word corresponding to the address count being presented (at this stage the count is zero) is read out from the store 10 and sent along line 18 to the display output section. Step 5 checks to see whether the complete store has been read out to the display, i.e. whether a display sweep has been completed or not. If not, the address counter 20 is incremented (step 6).Step 7 changes the circuit into the write mode by (a) enabling the store 10 by means of the multiplex counter 12, (b) presetting the address counter 20 with the contents of the storage register 22, i.e. with the current write address, and (c) loading the storage register 22 with the previous contents of the address counter 20, i.e. with the next read address. In other words, step 7 has the effect of interchanging the contents of the address counter 20 and the storage register 22. Step 8 writes new data into the store at the location in accordance with the write address presented by the address counter 20, as long as the "use this sample" flag is set (this feature will be further explained later), and thereafter (step 9) the address counter is incremented, again if the flag is set.Step 10 performs an operation similar to that of step 7 but in relation to the read mode rather than the write mode. Finally, the sequence returns to step 4 and this operation continues with incrementing read and write address counts untii a complete display sweep has been detected by step 5.

When the apparatus is capable of running at a high sampling rate, it is advantageous to allow the A/D converter to continue running at its highest rate even though only a small fraction of the resulting samples may be stored, depending on the timebase setting. In such a case, the extra unused samples may be used for other functions, such as alias detection, envelope display, glitch detection, etc. The "use this sample" flag is provided when a sample is to be stored, and this acts as the control signal to the input 28 of the control circuit 26. In the absence of the control signal, steps 8 and 9 are omitted and the write address count remains unchanged in that and future cycles until a sample is to be stored and the flag is set.

It will thus be seen that in the 'REFRESH' mode, display sweeps are provided by reading out of the same address locations in the store for each "position" on the display, new data being entered sequentially so as to move the interface between old data and new data across the screen.

In the 'ROLL' mode, a further step is included us follows. 9A. Increment address counter if 'use this sample' flag set.

Step 9A follows step 9 of the previously described step sequence and is essentially a repeat of that step, thereby to increment the write address count twice if the "use this sample" flag is set. This is equivalent to (but much simpler to implement than), the incremental addition of the read and write counters of the previously proposed system. The double incrementation effectively leads to the displayed data being shifted along the display as new data are written in, thus providing the 'ROLL' movement effect, since the data being read out of the store are no longer in tha same "position" on the display for the same address locations.

The arrangement as described is particularly advantageous since digital storage oscilloscopes necessarily contain a fast acquisition store and address counter. If 'ROLL' and 'REFRESH' modes, which are only useful at low speeds, are to be implemented, the present arrangement allows the addition of a minimal quantity of high-speed logic.

The arrangement increases the utilisation of the high speed counter and adds only one simple Nbit register and some gating circuitry to the existing high speed hardware.

Claims (Filed on 10/5/83) 1. Data display apparatus for providing a representation of data as a waveform on a display, the apparatus comprising a memory means arranged to receive data samples for

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **. storage register 22. The output of the storage register 22 is in turn connected to the presetting input 24 of the address counter 20. Various clock and clear functions are provided to the address counter 20 and storage register 22 by a control circuit 26 which has an enabling input 28 receiving a control signal to be described. The operation of the circuit in the 'REFRESH' mode will be described with reference to the following step sequence. Sequence of steps of control circuit in 'REFRESH' mode

1. Set address counter and register to .

2. Set Display /write flat to display.

3. Synchronously enable RrW multiplex clock.

4. Read data word from Store. Write it to display.

5. Data display apparatus substantially as herein described with reference to and as illustrated in the accompanying drawing.

5. Check if complete store has been transferred to display. Exit or continue.

6. Increment address counter.

7. Simultaneously: (a) Set Displayfl7rite flag to write.

(b) Preset address counter to register contents (current write address).

8. Write to write address ] if'use this 9. Increment address counter sample' flag set

10. Simultaneously: (a) Set Displayfiwrite flag to display.

(b) Preset address counter to register contents (new read address).

(c) Load register with (next) write address.

11. Loop back to step 4.

Claims (Filed on 10/5/83)

1. Data display apparatus for providing a representation of data as a waveform on a display, the apparatus comprising a memory means arranged to receive data samples for

storage therein at selected locations in response to write address signals and to output stored data samples from selected storage locations to the display in response to read address signals, an address counter for providing the read and write address signals to the memory means, a storage means for holding one of the address signals while the other is in the address counter, and a control means operable to increment selectively the address signal in the address counter, present the incremented address signal to the memory means and to the storage means while transferring the other address signal from the storage means to the address counter, whereby the address signals in the address counter and in the storage means are periodically interchanged so as to alternate read and write address signals presented to the memory means.

2. Data display apparatus according to claim 1, wherein the address counter is responsive to the control means to increment selectively the address signal therein by a count representative of one, so as to provide a 'REFRESH' effect on the display.

3. Data display apparatus according to claim 1 or 2, wherein the address counter is responsive to the control means to increment selectively the read address signal by a count representative of one and the write address signal by a count representative of two thereby to provide a 'ROLL' effect on the display.

4. Data display apparatus according to claim 1, 2 or 3, wherein the memory means receives and stores only some of the data samples avaiiable, the control means being responsive to a control signal when a selected said data sample is to be stored, the write address signal only being incremented when the control signal is present.