JPS6391570A - Apparatus for observing logic signal - Google Patents

Abstract

PURPOSE:To make an observation period long even though a sampling clock is set small without increasing the capacity of a memory, by detecting the change point of a signal and counting the time before the signal changes to store the same. CONSTITUTION:A large number of logic signals inputted from input terminals 1a-1n are sampled based on the clock signal from a clock signal generator 4 by sampling circuits 5a-5n through comparators 3a-3n. When a sampling data state changes, F/F 11a-11n are reset and, at the same time, the count values of the contents of counter circuits 12a-12n are written in memories 6a-6n and subsequently cleared to start the counting of the continuous number of a new state. The contents recorded on the memories 6a-6n are converted by a display signal forming circuit 9 for forming a display signal to be displayed on a CRT display 10.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logic signal observation device commonly called a logic analyzer.

[Conventional technology]

FIG. 3 is a block diagram showing a conventional logic signal observation device disclosed in, for example, Japanese Unexamined Patent Publication No. 56-74659. In the figure, la, lb, lc.

... r in is an input terminal for multiple logic signals, 2
are threshold level circuits 3a, 3b, 3c, . . . that generate threshold levels that are reference voltages.

3n is a comparator provided to compare the threshold level determined by the threshold level circuit 2 with a plurality of digital human input signals to form a binary digital signal; 4 is a clock signal generator; 5a, 5
b, 5C,..., 5n are sampling circuits for respectively sampling the outputs of the plurality of comparators 3a to 3n based on the clock signal supplied from the clock signal generator 4; 6a, 6b, 6c, ・..., 5
n is a memory that sequentially stores sampling signals based on a clock signal, and is usually composed of a semiconductor memory.

Reference numeral 7 denotes a trigger signal circuit that generates a trigger signal for stopping signals to the memories 6a to 6n, and 8 delays the trigger signal generated from this trigger signal circuit 7 by a predetermined time in consideration of the memory capacity. 6n is a delay circuit that generates a signal to stop writing data, 9 is a display signal forming circuit, and 10 is a CRT display device.

Next, the operation will be explained. A plurality of logic signals inputted from input terminals 1a to 1n are connected to a threshold level set by a threshold level circuit 2 and a comparator 3.
A to 3n are compared.

The compared logic signals are converted to "1" if the value is larger than the threshold level, and "0" if the value is smaller than the threshold level, and are supplied from the clock signal generator 4 to the sampling circuits 53 to 5n. The data are sampled by the clock and sequentially stored in the memories 6a to 6n. In this case, the delay circuit 8 delays the trigger signal generated from the trigger signal circuit 7 by a predetermined period of time in consideration of the memory capacity, and generates a signal to stop writing data to the memories 6a to 6n. Thereafter, the signals read out from the plurality of memories 63 to 6n are converted into an appropriate form in the display signal forming circuit 9 and output to the CRT display device 1.
Displayed by 0.

[Problem that the invention seeks to solve]

The conventional logic signal observation device is configured as described above, and since the capacity of the memories 6a to 6n is limited, for example, if the memory capacity is IK bits for one signal, the clock signal to be sampled is 1 cycle Ion
If it is set to s, it is possible to memorize only IonsX I K = 1μs (see Figure 4 (a)). Therefore, if the period to be measured is 1μs or more, and the clock signal to be sub-ringed can be stored in one cycle with the precision of Ions. If you want to do this, you will not be able to observe all the logic signals during the period you want to observe.
In the end, the clock signal to be sampled is set to, for example, one period of 20 ns as shown in FIG. 4(b),
Sampling is rough, and the period you want to observe must be extended. In this case, the observation period is 2 μs (2
0nsx IK), but the sampling period is 2
Since this is performed using a clock signal of 0 ns, there is a problem in that changes in the input signal of 20 ns or less cannot be accurately measured.

This invention was made to solve the above-mentioned problems, and an object of the present invention is to obtain a logic observation device that can lengthen the observation period by setting a small sampling clock without increasing the memory capacity.

[Means for solving problems]

A logic signal observation device according to the present invention is provided with a plurality of comparators that compare a threshold level with logic signals from a plurality of input terminals and perform dual processing, and is based on a clock signal supplied from a clock signal generator. A sampling circuit is provided to sample a binary signal, a detection device is provided to detect a change in the state of the sampled data, and a counter is provided to count the time from one state change to the next state change. A display signal forming circuit is provided for forming a display signal based on the signal read from the memory, and a display corresponding to the display signal supplied from the display signal forming circuit is provided. It is equipped with a display device to display the information.

[Effect]

The logic signal observation device of the present invention detects the change point of the signal, counts the time until the signal changes if it does not change, and stores the value, thereby reducing memory consumption when the signal level is constant. By storing the minimum necessary information, the signal observation period is lengthened while maintaining the fineness of the period of the clock signal to be sampled, using the memory effectively.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, the same components as those in FIG. 3 are denoted by the same reference numerals, and the explanation thereof will be omitted. In Figure 1, lla, ll
b, llc, -, Iln are flip-flops (hereinafter referred to as F/F) that temporarily record state changes;
11a to l1n are set at the first state change and reset at the next state change. 12a
, 12b, 12C1..., 12n are counter circuits,
These counter circuits 12a to 12n are F/Flla to ll.
It is started by F/F 11 and counts how many times the same state, for example, "1" is sampled in succession.
Simultaneously with setting or resetting a to lln, the contents are sent to the memories 6a to 6n, and after selection, the contents are cleared and the next count starts anew. Also, memory 6
After recording the first sampled value, a to 6n store the contents of the counter circuits 12a to 12n in F/Fll.
The counter circuits 12a to 12n are sequentially recorded every cent or reset of a to lln (in addition, the counter circuits 12a to 12n are in a state regardless of the initial state value of the F/Fs 11a to 11n even when data is input for the first time. Make sure that it is recognized as a change.

Next, we will discuss the operation. A plurality of logic signals inputted from input terminals 1a to 1n are sent to a threshold level circuit 2.
The threshold level set in and comparator 3a~
3n.

If the compared logic signal has a value greater than the threshold level, it will be “1”, and if it is smaller, it will be “0”.
The sampling circuits 5a to 5n sample the outputs of the comparators 3a to 3n based on the clock signals supplied from the clock signal generator 4, respectively.

In this way, signal measurement is started, and at the same time the sampling data sent out from the sampling circuits 5a to 5n is stored in the memories 6a to 6n, the F/F 1
1 a to lln are set. Therefore, if the state of the sampling data remains unchanged, the counter circuits 12a~
12n continues counting the number of sampling data.

Also, when the state of missampling data changes, F/F
11a to lln are reset, and at the same time, the count values of the contents of the counter circuits 12a to 12n are stored in the memory 6a.
After being written to ~6n, it is cleared and starts counting the number of consecutive new states. The count values of the counter circuits 12a to 12n are written to the memories 6a to 6n using the F/F.
11 aNl 1 This is performed every time n is set or reset. In this example, which shows the response of a specific input signal in Figure 2, after starting the signal measurement, 1
”, 9th, 61 “O”, 1st, 5 “1”, and in order to record this, the memory for recording the counter value was set to 8 bits in advance, and the total Recording is achieved using a memory capacity of 25 bits.Therefore, with a conventional logic signal observation device, the number of clocks required during the signal measurement period is 49+61+5 in this case.
=115 bits, but it can be seen that the logic signal observation device of the present invention requires a much smaller memory capacity. The contents recorded in the memories 6a to 6n are stored in each memory 6a.
6n is converted by a display signal forming circuit 9 for forming a display signal based on the signal read from 6n, and displayed by a CR7 display device 10.

In the above embodiment, a flip-flop was used to temporarily store state changes, but a simple logic circuit may be used as long as it can store -times.

Further, a bit representing a state change may be recorded every time together with the counter value.

〔Effect of the invention〕

As described above, according to the present invention, a logic signal observation device includes a plurality of comparators that perform binarization by comparing a threshold level with a plurality of logic signals inputted from a plurality of input terminals, and a sampling circuit that samples signals based on a clock signal; a detection device that temporarily stores changes in the state of the sampled data;
A counter for measuring the time of sampling data from one state to the next, a memory for storing the measured value of this counter, and a display for forming a display signal based on the signal read from this memory. Since it is composed of a signal forming circuit and a display device that performs a display corresponding to the display signal supplied from the display signal forming circuit, memory efficiency is greatly improved, and it can be used for long periods while maintaining the fineness of the sampling period. This has the effect of being able to measure signals.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing a logic signal observation device according to an embodiment of the present invention, Fig. 2 is a waveform diagram for explaining the operation of an embodiment of the invention, and Fig. 3 is a conventional logic signal observation device. A block diagram showing an example of the device, and FIG. 4 is a waveform diagram for explaining the operation of the conventional device. In FIG. 1, 3a to 3n are comparators, 5a to 5
n is a sampling circuit, 6a to 6n are memories, 9 is a display signal forming circuit, lla to lln are flip-flops, 1
2a to 12n are counter circuits. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] A plurality of comparators provided to perform binarization by comparing a threshold level, which is a reference voltage determined by a threshold level circuit, with a plurality of logic signals input from a plurality of input terminals, and a clock signal generator. a sampling circuit that samples the signal binarized by the comparator based on a clock signal supplied from the comparator;
a detection device that temporarily stores changes in the state of the data sampled by the sampling circuit; a counter that measures the time during which the sampled data changes from one state to the next; and a measured value of the counter. a display signal forming circuit for forming a display signal based on the signal read from the memory, and a display device for displaying a display corresponding to the display signal supplied from the display signal forming circuit. Logic signal observation device equipped with