JP2934290B2 - Multi-channel voltage / current generator - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-channel voltage / current generator that can be used, for example, in an IC tester or the like.

[Background Art] In an IC test apparatus, a test pattern signal is given to an IC under test to test whether or not the IC under test operates normally in response to the test pattern signal to determine the quality of the IC.

When conducting a test, a voltage value and a current value defining H logic and L logic of a test pattern signal given to each terminal of an IC under test can be arbitrarily set for each type of IC or for each test item. Make up.

Since this setting is configured so that it can be set individually for each terminal, a number of voltage / current generating circuits covering several hundred channels are required.

FIG. 4 shows the configuration of a conventional multi-channel voltage / current generator. In the figure, reference numeral 1 denotes an address counter. A clock φ is applied to the address counter 1, the clock φ is counted, and the counted value is applied to the cell memory 2 and the data memory 3 as an address signal.

The data memory 3 stores data A _{1 to} A ₁₆ and G ₁₆ corresponding to the voltage values or current values of the H logic and the L logic shown in FIG. 3 in the form of a table. As an example of data stored in this table, data defining a voltage waveform will be described. As shown in FIG. 5, the voltage values defining the H logic of the logic waveform are A ₁ , A ₂ , A ₃ . It is given by the A _16.

The voltage values defining the L logic are given by B ₁ , B ₂ , B ₃ ... B ₁₆ . Logic waveform of maximum amplitude is defined when for example selecting the V _iH the A _1, V _iL to B _1. The logical waveform of minimum amplitude when selecting the A ₁₆ and B ₁₆ is defined.

That is with respect to the voltage waveform storage area V _iH, defined by V _iL data A ₁ written in to A ₁₆ and B ₁ ~B _16, with respect to the current waveform storage area I _H, data written to I _L C _{1 to} C ₁₆ and D ₁
Specified in ~D _16.

The comparison voltage for determining whether the logic waveform output from the IC under test is H logic or L logic is defined by the data E _{1 to} E ₁₆ and F _{1 to} F ₁₆ stored in the storage areas _VoH and _VoL. .

Also defined in the data G ₁ ~G ₁₆ storing the voltage in the storage area V _TT to provide one end of the terminating resistor logic waveform when taking output from the test IC.

These storage areas _{V iH, V iL, I H} , I L, V oH, V oL, V TT 7 kinds of waveform data A ₁ to A stored in the _{16, B 1 ~B 16, C} 1 ~C 16, D ₁ ~D _16,
The G ₁ ~G ₁₆ used to set for each pin.

The cell memory 2 stores cell data given to each pin of the memory under test. As shown in FIG. 2, the cell data stored in the cell memory 2 is the data memory 3 shown in FIG.
AD indicating the storage location of the waveform data stored in
R _{0 to} ADR ₁₅ are written.

That is, each waveform data storage area V _iH as shown in FIG. 3 to be written to the data memory _{3, V iL, I L,} I H, is ... V _TT is ensured. Switching of the storage area V _iH ~V _TT address signal ADR ₀ ~
Switched on top of for example 3 bits of ADR _15, the address ADR ₀ ~ADR ₁₅ in the lower bits are defined, each waveform data A ₁ ~G ₁₆ is read from the address ADR ₀ ~ADR ₁₅ of each storage area .

Address for reading out offset data and waveform data given to, for example, the first pin from the memory 2 In this example,
ADR ₂ , ADR ₂ , ADR ₃ , ADR ₃ ... Are sequentially read in this order. The first address ADR ₂ of the waveform data is stored in the cell register 4. The offset data is stored in the offset register 6.

The address ADR ₂ stored in the cell register 4 is given to the matching circuit 5. The other input terminal of the matching circuit 5 is supplied with an address signal from the address counter 1.

The address counter 1 counts the clock φ and increments the address by +1. The data A ₁ , A ₂ ... A ₁₆ written in the first storage area _ViH are read from the data memory 3 in accordance with the increment of the address.

Here, when the address given to the memory 3 matches the address ADR ₂ read from the memory 2, a latch designation signal is given to the register 8 by the match detection signal. At this time, the waveform data (A _{2 in} this example) read from the data memory 3 and the offset data stored in the offset register 6 are added by the adder 7, and the added value is given to the register 8.

Therefore, the address ADR ₂ of the data memory 3 is stored in the register 8.
Data obtained by adding the offset data in the waveform data A ₃ read from is latched, the latch output DA converter 9
Given to the DA conversion, the selected channel is an analog switch 11, the sample-hold circuits 12A provided for each channel, 12B, V _iH of voltage waveforms applied to each pin 12C ... 12N, V _iL, the voltage waveform I _H, I _L, V _oH given to logical comparator, V _oL, respectively sample and hold the V _TT to provide a terminating resistor.

Although not particularly shown here, a voltage output type buffer amplitude device and a current output type buffer amplifier are provided on the output side of each of the sample and hold circuits 12A to 12N. At the time of output, the current output type buffer amplifier is selected and used.

A sample and hold circuit for another channel is connected to the analog switch 11, and the sample and hold circuit for each channel samples and holds the voltage value of the waveform used at each pin.

[Problems to be Solved by the Invention] As described above, according to the conventional multi-channel voltage / current generator, the address read from the cell memory 2 is compared with the address output from the address counter 1 by the matching circuit 5 to detect a match. At this point, the data written in the memory 3 is read out, the offset data stored in the offset register 6 is added to the data at this time, the data is stored in the register 8, and the data is DA-converted. because must issue read all the addresses ADR ₀ ~ADR ₁₅ in each storage each area V _iH ~V _TT data memory 3 for each capture the ～12N, the sample-and-hold circuit 12A~12N into an analog voltage of each channel There is a disadvantage that the sample-hold period becomes long. That is, there is a disadvantage that the refresh cycle for the sample and hold circuits 12A to 12N becomes long.

As the refresh cycle of the sample and hold circuits 12A to 12N becomes longer, the number of sample and hold circuits that can be connected to the analog switch 11 is limited to a small number.

In other words, if the refresh cycle becomes longer, the hold voltage of the sample-and-hold circuit fluctuates, such as decreasing until the next refresh, and the accuracy deteriorates.

For this reason, conventionally, the number of sample and hold circuits connected to the subsequent stage of the analog switch 11 is limited to prevent a refresh cycle to each sample and hold circuit from becoming too long.

By being limited by the number of sample-and-hold circuits that can be connected to one analog switch 11, the cell memory 2, the data memory 3, the cell register 4, the coincidence circuit 5, the offset register 6, the adder 7, the register 8,
A plurality of circuits such as the DA converter 9 and the like are required, and there is a disadvantage that the structure becomes large-scale.

An object of the present invention is to provide a multi-channel voltage / current generator capable of shortening a refresh cycle for a sample and hold circuit.

"Means for Solving the Problems" In the present invention, a data memory is directly accessed by an address signal read from a cell memory, and necessary waveform data can be immediately read from the data memory.

Therefore, according to the present invention, it is possible to shorten the cycle for reading out the waveform data required for each channel, and to obtain the advantage that the refresh cycle of the sample and hold circuit can be shortened.

FIG. 1 shows an embodiment of the present invention. In FIG. 1, 1 is an address counter, 2 is a cell memory, 3 is a data memory, 4 is a cell register, 6 is an offset register, 7
Is an adder, 8 is a register, 9 is a DA converter, 11 is an analog switch, and 12A to 12N are the same as the conventional circuit in that they indicate sample and hold circuits.

In the present invention, the waveform data read from the cell memory 2 is supplied to the data memory 3 as an address signal, and the target data is directly read by the address signal.

For this purpose, as shown in FIG. 2, the cell memory 2 _stores data (ADR) and V
data on _iL (ADR), data on the I _H (ADR) ...
Is stored.

Each of the data ADR ₁ , ADR ₂ , ADR ₃ ... ADR ₁₆ is temporarily stored in the cell register 4 and applied to an address input terminal of the data memory 3.

Multiplexer on the input side of the address of the data memory 3
The data ADR _{1 to} ADR ₁₆ stored in the cell register 4 are input to the data memory 3 by switching of the multiplexer 14.

Writing to the data memory 3 the address signals A ₀ to A ₁₄ is supplied from the input terminal 14A, the address signal A ₀ to A ₁₄ is applied to the address input terminal of the data memory 3 through a multiplexer 14, data written Is performed.

The data memory 3 has a storage area _ViH as shown in FIG.
Write data A _{1 to} A ₁₆ to the storage area _ViL and write data B _{1 to} B
_16, write, write data C ₁ -C ₁₆ in the storage area I _H,
The storage area I _L writes the data D ₁ to D _16, the storage area V _oH write data E ₁ to E _16, the storage area V _oL write data F ₁ to F _16, the storage area V _TT data G ₁ Write ~ G ₁₆ as a table.

Row of the table is accessed by the address ADR ₁ ~ADR _16. The address ADR ₁ ~ADR ₁₆ upper bits the storage area V _iH of, V _iL, ... V _TT is switched.

Therefore, V from the storage area corresponding to the pin of the cell memory 2
_When ADR ₁ is read as data relating to _iH , address ADR ₁ of storage area _ViH of data memory 3 is accessed,
For example A ₁ of the data is read.

Address 0 of the storage area corresponding to the pin of the cell memory 2
By reading 6, each storage area V _iH waveform data to be supplied to the _{pin, V iL, I H, I} L, V oH, V oL, all data V _TT is read.

The data memory 3 is provided with an area for storing offset data in addition to the area of the table shown in FIG. An address signal output from the address counter 1 is supplied to the data memory 3 via the controller 15 and read from the area storing the offset data.

The offset data read from the data memory 3 is stored in the offset register 6, and the offset data stored in the offset register 6 is added to the waveform data of each pin read subsequently by the adder 7, and the addition result is stored in the register. 8 and supplied to sample and hold circuits 12A to 12N through a DA converter 9 and an analog switch 11.

According to the configuration of the present invention described above, since the table stored in the data memory 3 is directly read by the data read from the cell memory 2, a desired waveform can be read from the data memory 3 at the same time data is read from the cell memory 2. Data can be read.

[Effect of the Invention] Therefore, according to the present invention, the data read from the cell memory is compared with the address output from the address counter, and the waveform data stored in the table is read out at the time of coincidence. As a result, the read cycle of the waveform data, that is, the refresh cycle for the sample and hold circuit can be reduced to about 1/4.

Therefore, the refresh cycle for the sample-and-hold circuits 12A to 12N can be shortened.
Can be increased in the number of sample and hold circuits connected to the output side. As a result, there is obtained an advantage that the entire circuit scale can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a diagram for explaining the contents of a cell memory used in the embodiment of the present invention, and FIG. 3 is used in the embodiment of the present invention. FIG. 4 is a block diagram for explaining a conventional technique, and FIG. 5 is a waveform diagram for explaining an example of a setting state of waveform data. 1: address counter, 2: cell memory, 3: data memory,
4: Cell register, 6: Offset register, 7: Adder, 8:
Register, 9: DA converter, 11: Analog switch, 12A-12
N: Sample hold circuit.

Claims (1)

(57) [Claims] 1. A data memory for storing waveform data in a table, B. a cell memory for storing an address for reading the waveform data stored in the data memory as waveform data for giving to each pin, C. DA to convert waveform data read from data memory to DA
A converter; D. an analog switch for distributing the analog voltage output from the DA converter to a plurality of branches; E. a plurality of sample and hold circuits for sampling and holding the analog voltage distributed by the analog switch; Multi-channel voltage / current generator constituted by: