JPS63249090A - Multichannel pulse input time measuring circuit - Google Patents

Abstract

PURPOSE:To simplify circuit constitution and to facilitate the measurement of a time, by detecting pulse input by either one of input channels and successively storing the count value at that time and the data relating to the detected number of channels in an FIFO and subsequently reading the same in succession by a processor to operate the timewise relation between an input pulse cycle and each of the channels. CONSTITUTION:The pulse input signals of (n)-channels are latched on the basis of the clock from a clock generator 3 by the data latches 1 of a time measuring circuit and the rising or falling of the outputs from (n)-stages of the latches 1 is detected by edge detectors 2. The output data detected by the detectors 2 are stored in an FIFO memory 7 as channel data and the counter data obtained by counting the clocks from a counter 4 are stored in an FIFO memory 8. The channel data and counter value from the memories 7, 8 are read to be applied to a processor 10 and the desired timewise relation relating to input pulses is calculated.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to improvements in circuits for timing multichannel input pulses.

[Prior art] Conventionally, time meters that receive pulse input from multiple channels I!
1 (input pulse period, time difference between channels, etc.), it is common to provide a counter or register for each channel and measure it.

Such conventional systems have a problem in that the circuit configuration becomes large-scale as the number of input channels increases.

The present invention has been made in view of these points, and aims to realize a pulse input time measuring circuit that can measure time with a relatively simple circuit configuration even when the number of input channels increases. That is.

[Means for Solving the Problems] In order to achieve such an object, the present invention provides a circuit for time-measuring multi-channel input pulses, which includes a clock generator that generates a reference clock, and a clock generator that generates a reference clock. , a counter that counts the clock, a data latch that latches the input pulse of each channel separately for each channel in synchronization with the clock, and is set by the rising or falling edge of the latch output of this data latch. an edge detector corresponding to a channel; means for storing, when a pulse input is detected by any of the edge detectors, information on the channel in which the pulse input is detected and the value of the counter in a FIFO memory; and a channel obtained by the means; The present invention is characterized by comprising a processor having means for performing arithmetic processing to obtain a desired time relationship regarding input pulses based on information and count values.

[Operation] In the present invention, when a large pulse input is detected in any of the input channels, the value of the counter at that time and the channel information on which the pulse input was detected are sequentially stored in the FIFO memory, and then the processor stores the channel information and the channel information. The counter values are sequentially read out and the input pulse period of a specific channel, the time relationship between channels, etc. are determined by calculation.

[Example] Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a multi-channel pulse large input time measuring circuit according to the present invention. In FIG. 0, 1 latches n-channel pulse input signals from #ICH to $nCH, respectively. The data latch is composed of n latches, which simultaneously latch in synchronization with a clock signal. 2 consists of n latches corresponding to each channel 1, and the rising or falling edge of the output of each latch of data latch 1 (set to either)
An edge detector that detects each and sets a bit,
3 is a clock generator that generates the clock signal; 4 is a counter that counts this clock signal; 5 is an n-bit channel data bus to which the output of each latch of the edge detector 2 is individually sent; 6; is an OR circuit that performs an OR operation on n bits of channel-corresponding bit data on the channel data bus 5, and if there is any bit set on the channel data bus 5, an OR circuit is applied to the FIFO memory 7.8. It is designed to issue a data storage instruction signal.

The FIFO memory 7 is a first-in, first-out type memory that stores the contents (channel data) on the channel data bus 5. The FIFO memory 8 is a first-in, first-out type memory that stores the contents of the counter 4.

Reference numeral 10 denotes a processor (cpu) which performs arithmetic processing such as determining one cycle of reading the contents of the FIFO memory 7.8 through the %CPU data bus 9.

The operation in such a configuration will be explained next with reference to the timing chart of FIG. Note that in order to simplify the explanation, the number of channels is assumed to be three here. The pulse input signals IN#ICH to IN#3CH from the outside are converted to the clock signal CLK from the clock generator 3 by the data latch 1.
and its output signal S # I CH-8
#3CH is input to the next stage edge detector 2 and detected at the designated edge. Then, each time an edge is detected, data (P#1 to P#3
) is output (Figure 2 shows an example in which data is output when a rising edge is detected).

The OR circuit 6 performs an OR operation on the data on the channel data bus 5 and outputs a 0RCH signal. FIFO)lmolj
7,8g*0 Data is stored when the RCH signal becomes Low, and the FIFO memory 7 stores the channel data CHDATA on the channel data bus (3-bit data, the least significant bit is the first channel, the second bit is corresponds to the second channel and the most significant bit corresponds to the third channel), and the FIFO memory 8 stores the data CDATA of the counter 4, respectively.

The contents of the stored FIFO memory are transferred to the CPU data bus 9.
The data is read out by the processor 10 via the processor 10 and subjected to arithmetic processing. FIG. 3 shows a flowchart for calculating the interval of pulses input to the first channel as an example.

In this way, the period and interval of input pulses for each channel can be determined.

[Effects of the Invention] As explained in detail above, according to the present invention, when the number of pulse input channels to be handled increases, the data latch 1,
Edge detector 2. Channel data bus 5, OR circuit 6
This can be handled simply by increasing the bit width of the FIFO memory 7, and therefore time can be measured with a relatively simple configuration despite multi-channel input.

Further, since the channel data indicating whether or not a pulse input is detected and the counter data at that time are temporarily stored in the memory, various time measurements can be made by performing appropriate arithmetic processing in the processor. For example 1
It is possible to measure the following items.

■Cyclic hand side.

■Measure delay time between each channel.

■Pulse count.

■Timing analyzer (however, sampling pulses must be input to a specific channel).

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the multi-channel pulse input time hand subcircuit according to the present invention, FIG. 12 is a timing chart for explaining the operation, and FIG. 3 is a flow chart for determining the pulse interval. be. 1...Data latch, 2...Edge detector, 3...
・Clock generator, 4...Counter, 5...Channel data bus, 6...OR circuit, 7゜8...FIFO memory, 9...CPU data bus. 10... Processor.

Claims (1)

[Scope of Claims] A circuit that measures the time of multi-channel input pulses, comprising: a clock generator that generates a reference clock; a counter that counts the clock; and a circuit that measures the input pulses of each channel as the clock. A data latch that synchronously latches each channel separately, a channel-compatible edge detector that is set by the rising or falling edge of the latch output of this data latch, and a pulse input in either of these edge detectors. means for storing the channel information on which the pulse input was detected and the value of the counter in a FIFO memory; 1. A multi-channel pulse input time measuring circuit comprising: a processor having means for performing arithmetic processing.