JPH04218791A - Simultaneous counter - Google Patents

Abstract

PURPOSE:To obtain a simultaneous counter circuit dispensing with adjustment, being excellent in stability and enabling execution of real-time detection. CONSTITUTION:In a simultaneous counter circuit executing simultaneous counting of a plurality of series of signals comprising time information, a reference clock generating means, sampling means provided for the plurality of series of signals and operating synchronously with a clock of the aforesaid reference clock generating means, a delay means provided for the series on one side and operating synchronously with the aforesaid clock, a means for obtaining a pulse of a prescribed width, which is provided for the series on the other side and operates synchronously with the aforesaid clock, and a means for taking the logical sum of outputs of the means for obtaining the aforesaid pulse of the prescribed width and the logical product of outputs of the aforesaid delay means, are provided.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a coincidence circuit for detecting a pair of temporally correlated events, such as in positron CT.

0002

2. Description of the Related Art First, the principle of positron CT will be explained based on FIG. The positrons emitted from the positron-emitting nuclide 2 taken into the living body 1 or the like lose kinetic energy in the vicinity, and then combine with electrons constituting the substance and disappear. At this time, a pair of annihilation photons 3a and 3b are emitted in opposite directions. These annihilation photons (gamma ray pairs) 3
a and 3b are measured by simultaneous counting of a pair of detectors 4a and 4b placed facing each other with the living body 1 in between. here,
Coincidence is a technique that counts as one event only when the gamma ray pair 3a, 3b is simultaneously incident on both detectors 4a, 4b, and has essential importance in positron CT.

Due to the simultaneous counting of the detectors 4a and 4b, only the positron-emitting nuclide 2 in the cylindrical portion connecting these detectors 4a and 4b is detected. In positron CT, this property is utilized to simultaneously measure multiple directions along a certain cross section of the living body 1. From these data, a computer calculates the distribution of the positron-emitting nuclide 2 in the cross section using a calculation method similar to that of X-ray CT, and displays it as an image.

FIG. 6 shows an electronic circuit of a positron CT apparatus. The signals detected by the detectors 4a, 4b and converted into electrical signals enter preamplifiers 5a, 5b. The time of occurrence of the pulse signals output from the preamplifiers 5a and 5b is identified, and the time signal is transferred to the gate 6a.
, 6b to the coincidence counting circuit 7, and the energy discrimination circuits 11a, 11 confirm that the pulse is not caused by noise but is indeed caused by the gamma ray pair 3a, 3b.
It is necessary to judge based on b. Energy discrimination circuit 11
a, 11b integrates the pulse signal, selects only those signals whose integral value is above a certain level, and requires a time approximately equal to the fluorescence decay time.

On the other hand, the time signal is sent to the time pickoff circuit 8.
a and 8b, it occurs simultaneously with the rising edge of the pulse. Since energy discrimination has not been completed at the time the time signal is generated, the time signal is delayed by a certain amount by the delay circuits 9a and 9b. After a certain period of time has elapsed, when the energy has reached the threshold value, the gates 6a and 6b open and the signal enters the coincidence circuit 7. On the other hand, when the energy is below the threshold value, the gates 6a and 6b are not opened and subsequent processing is not performed. The resolution time in the time pickoff circuits 8a and 8b is an important factor in determining the coincidence window width of the coincidence circuit 7, and must be made as short as possible.

In the coincidence circuit 7, two detectors 4a,
It is determined whether the time signals from 4b come at the same time, and if they come at the same time, the signals are sent to the address encoder 10. However, the time signal from the γ-ray pair 3a, 3b is
They do not enter the coincidence circuit 7 at exactly the same time. Therefore, the coincidence counting circuit 7 determines that signals that have arrived within a certain fixed time are simultaneous.

That is, in FIG. 7, it is assumed that the detector 4a (I in the figure) detects the γ-ray pair 3a at time t0. At this time, another detector 4b (J in the figure) that performs simultaneous determination with this detector 4a detects γ between t0-τ and t0+τ.
When line pair 3b is detected, it is determined that a simultaneous event has occurred. The time width 2τ of this simultaneous determination is called a coincidence window. Note that events 3b' and 3b'' outside the coincidence window 2τ are not determined to be simultaneous events.

Conventional simultaneous determination is performed in FIGS. 8, 9 or 1.
This was done using the method shown in 0. In FIG. 8, 12
is a monostable multivibrator, which produces a pulse with a length of coincidence window 2τ. A delay circuit 13 delays the signal by half of the coincidence window 2τ, that is, τ. And each D
By applying the signal to the D input and C input of the D type flip-flop circuit 14, the output of the D type flip-flop circuit 14 is used to determine simultaneous events.

FIG. 9 shows another conventional example, in which 15 and 16 are first and second monostable multivibrators, each of which forms a pulse with a length τ that is half the length of the coincidence window 2τ. . The outputs of the two first and second monostable multivibrators 15 and 16 are passed through an AND gate 17 to determine whether there is a simultaneous event of 2τ. As such a method, Japanese Patent Application Laid-Open No. 57-131
There is Japanese Patent Publication No. 086, and Japanese Patent Application Laid-Open No. 1986-1989 uses ROM or RAM instead of AND gate 17.
There is a publication No. 197783.

What is common between FIGS. 8 and 9 is that the time intervals between pulses are treated as having continuous properties. The monostable multivibrator 12, 1
Delay circuits 5 and 16 are used, and like the delay circuit 13, these are delay circuits that utilize a delay line or a CR integrator. However, in FIGS. 8 and 9, the delay lines and CR integrators as delay circuits used in the monostable multivibrators 12, 15, and 16 are affected by changes in temperature and power supply voltage, and cannot be used for long periods of time. It was difficult to operate stably without adjustment. In particular, in the case of a CR integrator, there is a problem in that initial adjustments must be made in order to obtain an accurate coincidence window.

In order to solve this problem, H. M. It has been proposed by Dent et al. The principle of this method will be explained with reference to FIG. As shown in FIG. 10(I), it is assumed that one of the gamma rays 3a is detected by a certain detector 4a somewhere between time t0 and t0+Δt. A signal sampled by a common clock having a period Δt is output as a pulse. Although this pulse loses the continuous nature of the time intervals shown in FIGS. 8 and 9, it retains time information with an accuracy of Δt.

In contrast to this γ-ray 3a, the γ-ray 3b, which is detected simultaneously, is detected from t0-Δt to t0, as shown in FIG. 10(J).
If γ-ray 3b is detected somewhere between +2Δt, it is considered a simultaneous event. The superposition function I〇J of γ-rays 3a and γ-rays 3b is a trapezoid, but its area is a uniform distribution of 3Δt horizontally (= rectangle)
Since it is the same as , the coincidence window 2τ = 3
Δt.

In order to realize this principle, Dent et al. adopted the following method. Common clock Δt=4n
Sample the gamma ray detection signal (timing signal) at s, and
One section consists of 4 samples (256 ns). Here, one section will be referred to as one frame. From this sampled result, information is created as to which sample among the 64 samples of this one frame the gamma ray pair 3a, 3b was detected. If the gamma ray pair 3a, 3b is not detected in one frame, it is information that it is not present in any sample. This information is sent to the simultaneous event detector for each frame, and the information is compared with the simultaneous event detection pair, and if the above conditions are met, it is determined that the event is a simultaneous event.

[0014]

[Problems to be Solved by the Invention] The method of Dent et al. had the following problems. (1) Only one gamma ray can be detected within one frame. That is, even if gamma rays are detected twice within one frame, information on one of them must be discarded. In positron CT, several detectors are generally grouped into one group, and timing is extracted for each group. However, in the above method, even if different detectors detect gamma rays in the same frame, only one of them Only information can be used. This means that the probability of miscounting increases when the number of incident gamma rays per unit time is large. (2) Sampling must be performed with the same clock for all detectors. Dent
There are 16 groups in positron CT, such as
For these 16 groups, exactly the same, i.e.
A clock with no phase shift must be provided, and this requires careful adjustment. (3) Simultaneous events that span frames cannot be detected.

The present invention has been made to solve the above-mentioned problems, and aims to provide a coincidence circuit that does not require adjustment, has excellent stability, and can detect in real time. be.

[0016]

Means for Solving the Problems The present invention provides a coincidence circuit for performing coincidence processing on a plurality of sequences of signals having time information, which includes a reference clock generating means, a reference clock generator provided in the plurality of sequences, and a a sampling means that operates in synchronization with the clock of the clock generation means; a delay means that is provided in one series and operates in synchronization with the clock; and a constant that is provided in the other series and operates in synchronization with the clock. A coincidence counting device comprising: means for obtaining a pulse having a constant width; and means for obtaining a logical sum of the outputs of the means for obtaining a pulse of a constant width and an AND of the output of the delay means.

[0017]

[Operation] The first and second sampling means shape the input signal into a constant width, that is, a pulse width corresponding to one clock of the common clock of the reference clock generating means. This waveform shaping is performed in synchronization with a common clock. The time information of one of the input gamma rays is sent to a means for obtaining a constant width pulse. The time information of the other gamma ray is sent to delay means and delayed. If the output of the delay means indicates an event within a predetermined time, it indicates the event of the output of the means for obtaining a pulse of a constant width, so the time information output of this gamma ray is logically summed and By performing a logical product with the output of the delay means, simultaneous events can be determined.

[0018]

Embodiments Hereinafter, embodiments of the present invention will be explained based on the drawings. In FIG. 1, 20 is a reference clock generating means. A first sampling section 21 and a second sampling section 22 shape the input signal into a constant width, for example, a pulse width of one clock of the common clock of the reference clock generating means 22. This waveform shaping is naturally performed in synchronization with the common clock.

The gamma ray 3a is incident on one of the inputs (I in the figure), and the signal whose waveform is shaped by the first sampling section 21 is as follows.
It is sent to the shift register 23. The gamma ray 3b enters the other input (J in the figure), and the signal whose waveform is shaped by the second sampling section 22 is sent to flip-flop circuits 24 and 25, which delay the input signal.

If the output of the flip-flop circuit 25 indicates an event from t0 to t0+Δt, Q0 of the output of the shift register 23 will change from t0+Δt to t0+2Δt.
Since t and Q1 indicate the event from t0 to t0+Δt, and Q2 indicates the event from t0-Δt to t0, the three outputs of Q0, Q1, and Q2 are logically summed by the OR gate 26, and this and the output of the flip-flop circuit 25 are combined. A simultaneous event is determined by performing a logical AND operation using the AND gate 27. Note that, among the general functions of a shift register, the shift register 23 does not require stop, reverse shift, and load, so it can also be configured by a simple cascade connection of flip-flop circuits 24.

In the method shown in FIG. 1, the width of the coincidence window and the delay time are all determined by a common clock, so no adjustment is necessary. In addition, its stability is determined by the stability of the clock, but if the clock is generated using a highly stable element such as a crystal oscillator, it will have much higher stability than a circuit using a delay line or CR integrator. Is possible. Furthermore, since the dead time is extremely short compared to the method of Dent et al., the probability of omitted counting can be reduced. When a large number of coincidence circuits are required, such as in a positron CT, it is sufficient that each clock operates with the same cycle, and there is no need to match the phases, so there is no need to adjust the clock skew. Furthermore, since there is no such thing as a frame, there is no possibility that simultaneous events spanning frames cannot be detected.

In the embodiment shown in FIG. 1, the coincidence window is 2τ=3Δt, but the coincidence window is not limited to this, and is 2τ=(2n+1)·Δt(n=
1, 2, 3,...). What changes at this time is that the output of the shift register 23 becomes (2n+1), the input of the OR gate 26 also becomes (2n+1), and the total number of outputs of the flip-flop circuits 24 and 25 becomes (2n+1).
1) Becoming an individual.

Next, FIG. 2 shows a second embodiment of the present invention, in which a flip-flop circuit 28, OR gates 29 and 32, an AND gate 30, and an inverter
An example is shown in which the width of the coincidence window is made variable by adding 1. That is, when the selection signal 1 of 3Δt is input to the selection signal input terminal S, the circuit including the OR gate 26, the AND gate 27, and the OR gate 32 selects 2τ=3Δt.

Further, when the selection signal 0 of 5Δt is input to the selection signal input terminal S, the circuit including the OR gate 29, the AND gate 30, and the OR gate 32 selects 2τ=5Δt. It is possible to select either the case where 2τ=5Δt or the case where 2τ=5Δt. Further, a similar circuit can be configured even if the width of the coincidence window is three or more types.

In standard coincidence measurement, it is essential to correct the contribution due to random events from the measured coincidence rate in order to determine the counting rate due only to true simultaneous events. For this reason, a method has been adopted in which random events are measured by inserting a large time delay into either of the inputs and performing coincidence counting where true simultaneous events do not occur.

To realize this method, for example, a configuration as shown in FIG. 3 is used. In FIG. 3, the number of stages of the shift register 23 on one input (I) side is increased to insert a time delay, and this delay is defined as (m-1)·Δt, and the OR gate 33
join to. The value of m is determined by the time resolution of the detector and the subsequent processing circuit. And and gate 30
The output of the AND gate 27 is used as a delayed simultaneous event output, and the output of the AND gate 27 is used as an immediate simultaneous event signal (prompt). In this example, a time delay is inserted on one input (I) side, but it is also possible to insert it on the other input (J) side. In this case, by increasing the number of flip-flop circuits 24 and 25. good.

The above embodiment is an example in which I and J perform one-to-one coincidence counting, but it can easily be extended to one-to-many or many-to-many coincidence counting. FIG. 4 shows an example where I:J is 1:3. In this example, sampling units 22, 34, and 35 are coupled to the inputs of J0, J1, and J2, respectively, and a single event determination unit 36 is connected to the output side of these, and a flip-flop circuit 24, 25, 38, and 39 are combined. And J0, J1, J
Only when the single event determination section 36 determines that one of the events of 2 has occurred, simultaneous detection with I is performed and is output from the AND gate 27, and simultaneously with any of J0, J1, and J2. The address signal of J indicating whether it has been detected is
It is determined when the flip-flop circuits 39 simultaneously detect the signals. Conventionally, the J-side identification was generally performed after simultaneous detection, which caused detection dead time, but in the example of FIG. 4, this dead time can be eliminated.

A coincidence circuit can be constructed by combining any two or more of FIGS. 2, 3, and 4. In other words, ``make the width of the coincidence window variable as shown in Fig. 2 or detect different coincidence windows simultaneously'', ``perform delayed coincidence as shown in the example of Fig. 3'', and ``perform the delayed coincidence shown in Fig. 4''. Of course, it is also possible to configure a coincidence circuit by combining two or more of the following: 1-to-many or many-to-many coincidence counting.

[0029]

[Effects of the Invention] Since the present invention is constructed as described above, not only positron CT but also all kinds of coincidence counting can be performed in real time without the need for adjustment, with excellent stability, and with almost no omission of simultaneous events. is possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of a coincidence circuit according to the present invention.

FIG. 2 is a block diagram of a second embodiment of the invention.

FIG. 3 is a block diagram of a third alternative embodiment of the present invention.

FIG. 4 is a block diagram of a fourth embodiment of the present invention.

FIG. 5 is a perspective view of positron CT.

FIG. 6 is a block diagram of an electronic circuit of positron CT.

FIG. 7 is an explanatory diagram of the principle of coincidence counting.

FIG. 8 is a block diagram of a conventional coincidence circuit.

FIG. 9 is another conventional block diagram.

FIG. 10 is a waveform diagram illustrating conventional operation.

[Explanation of symbols]

1... Biological body, 2... Positron emitting nuclide, 3a, 3b... Annihilation photon (gamma ray pair), 4a, 4b... Detector, 5a, 5b... Preamplifier, 6a, 6b... Gate, 7... Coincidence counting circuit, 8
a, 8b... Time pickoff circuit, 9a, 9b... Delay circuit, 10... Address encoder, 11a, 11b... Energy discrimination circuit, 12... Monostable multivibrator, 1
3... Delay circuit, 14... D-type flip-flop circuit, 15
...First monostable multivibrator, 16...Second monostable multivibrator, 17...AND gate, 18...Pulse, 20...Reference clock generator, 21...First sampling section, 22...Second sampling section , 23... Shift register, 24... Flip-flop circuit, 25... Flip-flop circuit, 26... OR gate, 27... AND gate, 28... Flip-flop circuit, 29... OR gate, 30... AND gate 31... Inverter, 32... OR gate, 33 ...ORGATE, 34...Sampling part, 35
... Sampling section, 36... Single event determination section, 37... Encoder, 38... Flip-flop circuit, 39... Flip-flop circuit.

Claims (5)

[Claims] Claims: 1. A coincidence circuit for performing simultaneous counting processing of a plurality of series of signals having time information, comprising a reference clock generation means, a clock provided in the plurality of series and synchronized with a clock of the reference clock generation means. a sampling means operating in one series; a delay means provided in one series and operating in synchronization with the clock; and a delay means provided in the other series,
The device comprises means for obtaining a pulse of a constant width that operates in synchronization with the clock, and means for calculating the logical product of the outputs of the means for obtaining the constant width pulse and the output of the delay means. Characteristic coincidence counting device. 2. The coincidence counting device according to claim 1, wherein the means for obtaining pulses of constant width comprises a shift register or a plurality of flip-flop circuits connected in series. 3. The coincidence counting device according to claim 1, wherein the width of the coincidence window of the means for obtaining pulses of a constant width is made variable. [Claim 4] A delay circuit with a large time delay is inserted into either the means for obtaining pulses of a constant width and the delay means, and by performing coincidence counting where true simultaneous events do not occur, contribution due to accidental events is eliminated. 2. The coincidence counting device according to claim 1, wherein said coincidence counting device corrects said timing. 5. At least one of the means for obtaining a constant width pulse and the delay means on the other side is provided with a plurality of event input terminals, each input is coupled to a sampling means, and furthermore, these outputs are connected to a sampling means. A single event determining section is coupled to a delay means via an encoder on the side, and a simultaneous detection signal of both is outputted only when it is determined that one of each event has occurred in the single event determining section, and 2. The coincidence counting device according to claim 1, wherein an address signal indicating which simultaneous detection is detected is outputted.