JP2018189445A - Waveform recorder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a waveform recorder with which it is possible to detect a desired event relating to a signal waveform efficiently with high accuracy without incurring an increase in cost.SOLUTION: A buffer 12 temporarily stores digital data Dd that is generated by analog-digital conversion of an analog input signal Sa. A buffer control circuit 15 controls a period from when the buffer 12 starts storing operation till when it finishes storing operation on the basis of trigger signals T1, T2. An event detection circuit 16 generates an event detection signal Si when an event is detected from the digital data Dd stored in the buffer 12 at termination of the period from when the buffer 12 starts storing operation till when it finishes storing operation. A memory circuit 18 stores waveform data Dw generated by a process of latching the digital data Dd, and stops storing the waveform data Dw in response to the event detection signal Si.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a waveform recording apparatus that records waveform data of an analog input signal.

  Conventionally, a waveform recording apparatus used as a digital oscilloscope or the like has been proposed (for example, Patent Documents 1 and 2). Many trigger and search functions have been proposed to allow the waveform recorder to acquire, observe and analyze various events. When using the pulse width trigger to implement the trigger function and search function, the pulse width at the set trigger level is counted with the counting clock, and the trigger is triggered when the counted pulse width matches the preset pulse width. A signal is generated. There has also been proposed a waveform recording apparatus that retrieves and displays a desired event after capturing waveform data.

Special table 2009-503458 gazette JP 2003-344454 A

  In the waveform recording apparatus using the pulse width trigger, since the measurement clock for counting the pulse width is not synchronized with the analog input signal, it is necessary to allow an error corresponding to one count of the pulse width. In order to detect the pulse width with high accuracy, it is necessary to use a high-frequency measurement clock, which disadvantageously increases the cost of the waveform recording apparatus.

  Further, in a waveform recording apparatus that retrieves and displays a desired event after capturing waveform data, the desired event does not always exist in the captured waveform data. In particular, when detecting a rare event, it is necessary to repeat the acquisition and search processing of waveform data a plurality of times, and there is an inconvenience that a desired event cannot be detected with high efficiency.

  An object of the present invention is to provide a waveform recording apparatus that can detect a desired event related to a waveform of a signal with high accuracy and high efficiency without increasing costs.

  A waveform recording apparatus according to the present invention generates a trigger signal from an analog input signal or digital data based on a trigger condition and a buffer that temporarily stores digital data generated by analog-to-digital conversion of the analog input signal. A trigger circuit, a buffer control circuit that controls a period from the start of the storage operation to the end of the buffer based on the trigger signal, and an end of the period from the start of the storage operation to the end of the buffer An event detection circuit that generates an event detection signal when an event is detected from the digital data stored in the buffer, and stores waveform data generated by processing the digital data and responds to the event detection signal And a memory circuit for stopping the storage of the waveform data.

  Preferably, the buffer includes a first buffer and a second buffer, and the trigger circuit generates the first trigger signal and the second trigger signal from the analog input signal or the digital data based on the trigger condition. The buffer control circuit controls a period from the start of the storage operation to the end of the first buffer based on the first trigger signal, and from the start of the storage operation of the second buffer to the end. Is controlled based on the second trigger signal, and the period from the end of the storage operation of the first buffer to the start of the storage operation of the second buffer is determined by the first trigger signal and the second The event detection circuit controls the digital data stored in the first buffer and the second data at the end of the period from the start of the storage operation to the end of the storage operation. Ffa generates an event detection signal when an event from the digital data stored in the second buffer during the end of the period from the start to the end of the storage operation is detected.

  Preferably, the buffer includes a plurality of buffers, the trigger circuit generates a plurality of trigger signals from the analog input signal or the digital data based on a trigger condition, and the buffer control circuit is configured to start the storing operation of the buffer. Is controlled based on the trigger signal, and the period from when a predetermined buffer of the plurality of buffers ends the storage operation to when the next buffer starts the storage operation is controlled. The event detection circuit measures the event when an event is detected from the digital data stored in the multiple buffers at the end of the period from the start of the storage operation to the end of the multiple buffers. A detection signal is generated.

  Preferably, the event detection circuit detects an event related to at least one of a level of digital data and a period in which digital data of a predetermined level is detected.

  Preferably, the memory circuit adjusts the timing at which the storage of the waveform data is stopped based on the time difference between the timing at which the trigger signal is generated and the timing at which the event detection signal is generated.

  Digital data temporarily stored in the buffer may be decimated.

  According to the present invention, it is possible to detect a desired event related to a signal waveform with high accuracy and high efficiency without increasing the cost.

It is a figure which shows one Embodiment of the waveform recording device by this invention. It is a figure which shows a part of FIG. 1 in detail. It is a figure which shows an example of the event detected by the event detection circuit. It is a flowchart which shows the waveform recording operation | movement of the waveform recording apparatus shown in FIG. It is a figure which shows other embodiment of the waveform recording device by this invention. It is a figure which shows a part of FIG. 5 in detail. It is a figure which shows the other example of the event detected by the event detection circuit. It is a figure which shows the other example of the event detected by the event detection circuit. It is a figure which shows other embodiment of the waveform recording device by this invention. It is a figure which shows a part of FIG. 9 in detail. It is a figure which shows the other example of the event detected by the event detection circuit.

An embodiment of a waveform recording apparatus according to the present invention will be described with reference to the drawings.
FIG. 1 is a diagram showing an embodiment of a waveform recording apparatus according to the present invention, and FIG. 2 is a diagram showing a part of FIG. 1 in detail. A waveform recording apparatus 1 shown in FIG. 1 is used as a digital oscilloscope or the like, and receives an analog input signal Sa from the outside.

  The waveform recording apparatus 1 includes an analog / digital converter (ADC) 11, a buffer 12, a control unit 13, a trigger circuit 14, a buffer control circuit 15, an event detection circuit 16, a capture processing circuit 17, and a memory. A circuit 18, a waveform processing and display processing circuit 19, and a display device 20 are provided.

  The control part 13 is comprised by CPU, for example. The buffer 12, the buffer control circuit 15, the event detection circuit 16, the capture processing circuit 17, and the waveform processing and display processing circuit 19 are configured by, for example, a field-programmable gate array (FPGA) incorporating a memory. The memory circuit 18 includes a memory that stores waveform data Dw, which will be described later, and a peripheral circuit that controls the memory. The memory is configured by, for example, a DRAM (dynamic random access memory). The peripheral circuit is configured by, for example, an FPGA. The display device 20 is configured by, for example, a liquid crystal display (LCD).

  The ADC 11 converts the analog input signal Sa into digital data Dd (for example, an 8-bit digital value), and the digital data Dd is input to the buffer 12 and the capture processing circuit 17. When the sampling rate of the ADC 11 is 1 gigasample / second, the digital data Dd is generated every nanosecond, but the data processing is parallelized in the buffer 12, the capture processing circuit 17, and the memory circuit 18 at the subsequent stage of the ADC 11. As a result, the processing speed can be reduced. For example, when a 125 MHz system clock (not shown) provided in the FPGA is used, eight digital data Dd are processed in parallel every 8 nanoseconds.

  The buffer 12 temporarily stores the digital data Dd based on the write / read signal C1 from the buffer control circuit 15. In the present embodiment, the buffer 12 starts storing the digital data Dd at the rising edge of the write / read signal C1, ends the storage of the digital data Dd at the falling edge of the write / read signal C1, and is stored in the buffer 12. The digital data Dd is output to the event detection circuit 16.

  The control unit 13 provides the trigger circuit 14 with information Xt related to the trigger condition. Further, the control unit 13 provides the event detection circuit 16 with information Xi related to the event condition. Further, the control unit 13 provides the waveform processing and display processing circuit 19 with information Xd relating to the waveform processing and display processing conditions of the waveform data Dw. Further, the control unit 13 outputs a command C <b> 2 for the memory circuit 18 to start a storage operation to the memory circuit 18. Note that the information Xt related to the trigger condition, the information Xi related to the event condition, the information Xd related to the waveform processing and display processing conditions of the waveform data Dw, and the command C2 are controlled by an operation unit (not shown) such as a keyboard. 13 is input. Further, in response to an event detection signal Si, which will be described later, the control unit 13 terminates the storage operation of the memory circuit 18 and sends a command C3 for reading the waveform data Dw stored in the memory circuit 18 to the memory circuit 18. Output.

  In this embodiment, the case where the width and height (maximum value) of the positive pulse is selected as the event condition will be described as an example, but a negative pulse may be used as the condition. Further, an average value or the like can be used instead of the pulse height.

  In the present embodiment, the trigger conditions are a rising edge and a falling edge of the analog input signal Sa detected based on a preset threshold level Th. In this case, the information Xt regarding the trigger condition is whether or not the analog input signal Sa is higher than the threshold level Th and whether or not the analog input signal Sa is lower than the threshold level Th after being higher than the threshold level Th. Including the condition that the determination is made.

  In the present embodiment, the event is a pulse width W defined by a period in which the digital data Dd (more specifically, interpolation data Dh described later) exceeds the threshold level Th. In this case, the information Xi regarding the event condition includes an interpolation magnification H, a threshold level Th used for interpolating the digital data Dd, a pulse width W of the pulse to be detected, and a maximum value Pm.

  The trigger circuit 14 generates trigger signals T1 and T2 according to the rising edge and falling edge of the analog input signal Sa detected based on a preset threshold level Th. In the present embodiment, the trigger circuit 14 compares the level of the analog input signal Sa with the threshold level Th using a comparator (not shown), and the disable signal (not shown) for the trigger circuit 14 is released. When the analog input signal Sa becomes higher than the threshold level Th in this state, the trigger signal T1 is generated and transmitted to the buffer control circuit 15 (that is, the trigger signal T1 transits from the low level to the high level). The trigger circuit 14 triggers when the analog input signal Sa becomes lower than the threshold level Th after the disable signal (not shown) for the trigger circuit 14 is released and then becomes lower than the threshold level Th. The signal T2 is generated and transmitted to the buffer control circuit 15 (that is, the trigger signal T2 transits from low level to high level). The trigger circuit 14 is disabled after transmitting the trigger signal T2 to the buffer control circuit 15. The trigger circuit 14 does not generate the trigger signal T2 until the trigger signal T1 is generated. When the analog input signal Sa falls below the threshold level Th before a predetermined time has elapsed since the generation of the trigger signal T1, the trigger circuit 14 is initialized and a disable signal for the trigger circuit 14 is generated. By returning to the state where the signal is released (that is, the trigger signal T1 transitions from the high level to the low level), it becomes possible to eliminate the invalid event detection operation. The trigger circuit 14 detects a rising edge and a falling edge of the digital data Dd based on a preset threshold level Th, and generates trigger signals T1 and T2 according to the detected rising edge and falling edge. May be.

  In order to detect an event (in this case, pulse width W) from the digital data Dd, the buffer control circuit 15 controls the period from the start of the storage operation to the end of the buffer 12 based on the trigger signals T1 and T2. . In the present embodiment, when the buffer control circuit 15 receives the trigger signal T1, the buffer 12 sets the write / read signal C1 to high level in order to start storing the digital data Dd. Further, when the buffer control circuit 15 receives the trigger signal T2, the buffer control circuit 15 ends the storage of the digital data Dd and sets the write / read signal C1 low in order to output the digital data Dd stored in the buffer 12 to the event detection circuit 16. To level.

  In this embodiment, the buffer control circuit 15 adjusts the period from the start of the storage operation to the end of the buffer 12 in order to adjust various periods in addition to the time when the trigger signals T1 and T2 are generated. Consider. Various requirements include, for example, a delay time from the generation of the trigger signal T1 to the control of the buffer 12, a delay time from the generation of the trigger signal T2 to the control of the buffer 12, the timing of the generation of the trigger signal T1, and the buffer of the digital data Dd. 12 includes the difference from the timing of storing the data to 12, the number of extra data necessary for the interpolation processing, and the like. Information about various requirements may be provided from the control unit 13 to the buffer control circuit 15 through operation of the operation unit, for example.

  The event detection circuit 16 generates an event detection signal Si when an event is detected from the digital data Dd stored in the buffer 12 at the end of the period from the start of the storage operation to the end of the buffer 12. . In the present embodiment, as shown in FIG. 2, the event detection circuit 16 includes an event detection control circuit 16a, an interpolation processing circuit 16b, a time detection processing circuit 16c, a level detection processing circuit 16d, and an event determination circuit 16e. And having.

  The event detection control circuit 16 a is provided with information Xi related to event conditions from the control unit 13. Then, the event detection control circuit 16a provides information about the interpolation magnification H to the interpolation processing circuit 16b, provides the threshold level Th to the time detection processing circuit 16c, and relates to the pulse width W and the maximum value Pm of the pulse to be detected. Is provided to the event determination circuit 16e.

  The interpolation processing circuit 16b is supplied with digital data Dd for detecting an event from the buffer 12, and generates interpolation data Dh by performing interpolation processing of the digital data Dd at an interpolation magnification H to generate a time detection processing circuit 16c and a level. This is supplied to the detection processing circuit 16d. For the interpolation processing, general sin (x) / x interpolation, linear interpolation, or a combination thereof can be used. When the interpolation magnification H is 100, the digital data Dd every 1 nanosecond is converted into interpolation data Dh every 10 picoseconds. Further, the interpolation processing circuit 16b outputs a time detection signal C11 to the time detection processing circuit 16c during the output period of the interpolation data Dh.

  The time detection processing circuit 16c detects the positive slope time and the negative slope time according to the time detection signal C11, outputs the level detection period signal C12 to the level detection processing circuit 16d, and outputs the pulse width detection processing result Dt. This is supplied to the event determination circuit 16e. The time detection processing circuit 16c can detect the time with high accuracy by using the interpolation data Dh. In order to prevent erroneous measurement due to noise or the like of the analog input signal Sa in the time detection process, a generally used hysteresis process may be performed. Further, the negative slope time may be used as a reference for the time axis when the waveform is displayed on the display device 20 later.

  The level detection processing circuit 16d detects the detection processing result De (interpolation data level) of the maximum value L of the interpolation data Dh according to the level detection period signal C12, and supplies the detection processing result De to the event determination circuit 16e.

  The event determination circuit 16e determines whether or not an event has been detected from the digital data Dd stored in the buffer 12, based on the detection processing results Dt and De and the pulse width W and the maximum value Pm that are event detection conditions. . FIG. 3 is a diagram illustrating an example of a positive pulse event detected by the event detection circuit. In FIG. 3, a period Ti from the positive slope time to the negative slope time crossing the threshold level Th corresponds to the detection process result Dt of the time detection processing circuit, and the maximum value L of the interpolation data Dh in the period Ti is the level detection process. This corresponds to the detection processing result De of the circuit. The event determination circuit 16e determines whether or not the detection processing result Dt corresponds to the pulse width W and whether or not the detection processing result De corresponds to the maximum value Pm. More specifically, the event determination circuit 16e determines whether or not the detection processing result Dt exists between an upper limit value (for example, 20.1 nanoseconds) and a lower limit value (for example, 19.9 nanoseconds) of the pulse width W. And it is determined whether the detection processing result De exists between the upper limit value and the lower limit value of the maximum value Pm.

  Referring to FIG. 1, when an event is detected from digital data Dd stored in buffer 12, event determination circuit 16 e supplies event detection signal Si to control unit 13 and memory circuit 18. On the other hand, when no event is detected from the digital data Dd stored in the buffer 12, the event determination circuit 16e supplies the trigger circuit 14 with a release signal Ss for releasing the disable signal for the trigger circuit 14. . When the period Ti from the positive slope time to the negative slope time is significantly larger than the pulse width W, the time detection processing circuit 16c may not be able to detect the pulse width detection processing result Dt normally. In such a case, the buffer control circuit 15 or the time detection processing circuit 16c may supply the release signal Ss to the trigger circuit 14 (not shown) without waiting for the determination by the event determination circuit 16e.

  The acquisition processing circuit 17 generates waveform data Dw by performing acquisition processing of digital data Dd (peak detection and averaging processing at regular intervals, decimation (decimation), etc.), and the generated waveform data Dw is stored in the memory circuit 18. To store. For example, the capture mode for performing the capture process of the digital data Dd may be selected by the control unit 13 through an operation of the operation unit.

  The memory circuit 18 starts the operation of storing the waveform data Dw in response to the command C2, and stores the waveform data Dw corresponding to the number set as data to be stored in the memory circuit 18 as a pre-trigger (before trigger occurrence). . Thereafter, the control unit 13 releases the disable signal for the trigger circuit 14. The memory circuit 18 continues to store the waveform data Dw even after the disable signal for the trigger circuit 14 is released, and waits for the event detection signal Si from the event detection circuit 16. When the event detection signal Si is supplied from the event detection circuit 16 to the memory circuit 18, the memory circuit 18 performs post-triggering (after the trigger is generated) on the waveform data Dw of the number set based on the display time condition of the display 20. ) After storing the minute, the storage of the waveform data Dw is stopped.

  In order to control the number of waveform data Dw stored in the memory circuit 18 on the basis of the time of the detected event, the memory circuit 18 generates a trigger signal T2 at a timing to stop storing the waveform data Dw. It is preferable to adjust based on the timing. The time difference between the timing at which the trigger signal T2 is generated and the timing at which the event detection signal Si is generated is measured, for example, by counting with the system clock. In addition, in order to control the number of waveform data Dw stored in the memory circuit 18, a time difference between the timing at which the trigger signal T2 is generated and the timing at which the event detection signal Si is generated is predicted in advance, and the predicted time difference is calculated. It may be reflected in the number of waveform data Dw stored as a post-trigger amount or the overrun (excess number of writing) of the memory circuit 18.

  In response to the command C3, the memory circuit 18 reads the waveform data Dw and outputs the waveform data Dw to the waveform processing and display processing circuit 19. The waveform processing and display processing circuit 19 performs waveform processing and display processing of the waveform data Dw based on the information Xd regarding the waveform processing and display processing conditions of the waveform data Dw provided from the control unit 13. Then, the waveform processing and display processing circuit 19 supplies the waveform data Dwd subjected to the waveform processing and display processing to the display device 20, and the display device 20 displays the waveform data Dwd subjected to the waveform processing and display processing. To do.

  FIG. 4 is a flowchart showing the waveform recording operation of the waveform recording apparatus shown in FIG. This flow is based on the premise that the trigger signals T1 and T2 are generated after the disable period is canceled after the waveform recording apparatus 1 starts the waveform recording operation. First, the memory circuit 18 starts to store the waveform data Dw in response to the command C2 (step S1). In this case, the memory circuit 18 continues to store the waveform data Dw after releasing the disable signal for the trigger circuit 14 after storing the waveform data Dw for the pre-trigger.

  Next, the trigger circuit 14 generates the trigger signal T1 based on the trigger condition (rising edge) (step S2). Next, the buffer control circuit 15 sets the write / read signal C1 to the high level in response to the trigger signal T1, and the buffer 12 starts storing the digital data Dd in response to the write / read signal C1 (step S3). ).

  Next, the trigger circuit 14 generates the trigger signal T2 based on the trigger condition (falling edge) (step S4). Next, the buffer control circuit 15 changes the write / read signal C1 to the low level in response to the trigger signal T2, and the buffer 12 finishes storing the digital data Dd in response to the write / read signal C1, and the digital data Dd is supplied to the interpolation processing circuit 16b (step S5).

  Next, the interpolation processing circuit 16b performs an interpolation process on the digital data Dd supplied from the buffer 12 (step S6). Next, the time detection processing circuit 16c detects the pulse width detection processing result Dt from the positive slope time and the negative slope time, and the level detection processing circuit 16d determines the maximum value from the interpolation data Dh according to the level detection period signal C12. The detection processing result De is detected (step S7). Steps S6 and S7 describe functional procedures, and are sequentially processed in the pipeline in order to shorten the time for event detection processing in terms of circuit operation.

  Next, the event determination circuit 16e determines whether an event is detected from the digital data Dd stored in the buffer 12 (step S8). If no event is detected, the process returns to step S2.

  On the other hand, when an event is detected, the memory circuit 18 stores the waveform data Dw for the number set as the post-trigger and then stops storing the waveform data Dw (step S9). Next, the waveform processing and display processing circuit 19 performs waveform processing and display processing of the waveform data Dw stored in the memory circuit 18, and the display unit 20 displays the waveform data Dwd subjected to the waveform processing and display processing. (Step S10). Thereafter, the waveform recording apparatus 1 ends the process.

  According to the present embodiment, since the event detection is performed in real time from the digital data Dd stored in the buffer 12 in parallel with the storage of the waveform data Dw in the memory circuit 18, occurrence of a period of interruption and resumption of waveform recording occurs. Can be avoided.

  In addition, since the digital data Dd used for event detection is limited to the vicinity of the generation timing of the trigger signals T1 and T2, highly efficient event detection is possible. Further, by performing event detection using the interpolation data Dh, highly accurate event detection can be performed without using a high-frequency counting clock, and an increase in the cost of the waveform recording apparatus 1 can be avoided. In addition, it is possible to detect an event independent from the process of taking in the digital data Dd. Further, by performing the time detection process and the level detection process at the time of event detection, it becomes easy to obtain a desired event.

  Furthermore, when it is not required to detect an event with high accuracy, a wide pulse width can be detected by decimating the digital data Dd stored in the buffer 12.

  FIG. 5 is a diagram showing another embodiment of the waveform recording apparatus according to the present invention, and FIG. 6 is a diagram showing a part of FIG. 5 in detail. The waveform recording apparatus 1 ′ includes an ADC 11, buffers 12 ′ and 12 ″, a control unit 13, a trigger circuit 14, a buffer control circuit 15 ′, an event detection circuit 16 ′, an acquisition processing circuit 17, and a memory circuit. 18, a waveform processing and display processing circuit 19, and a display device 20.

  The buffer 12 ′, the buffer 12 ″, the buffer control circuit 15 ′, the event detection circuit 16 ′, the capture processing circuit 17, and the waveform processing and display processing circuit 19 are configured by, for example, an FPGA incorporating a memory.

  The buffer capacity needs to be increased as the pulse width, which is an event to be detected, becomes wider. In the present embodiment, in order to detect a wide pulse width with high accuracy without increasing the buffer capacity, the buffer 12 ′ for storing the digital data Dd around the rising edge of the analog input signal Sa and the rising edge of the analog input signal Sa. A buffer 12 ″ that stores digital data Dd around the falling edge is used. The buffer 12 ′ is an example of a first buffer, and the buffer 12 ″ is an example of a second buffer. Information on the number of digital data Dd stored in the buffer 12 ′ and the buffer 12 ″ is provided from the control unit 13 to the buffer control circuit 15.

  The buffer control circuit 15 'starts the storing operation so that the buffer 12' stores the digital data Dd for detecting the wide pulse width W, that is, the digital data Dd around the rising edge of the analog input signal Sa. The period from the start to the end is controlled based on the trigger signal T1 and the number of data provided from the control unit 13. In the present embodiment, when the buffer control circuit 15 ′ receives the trigger signal T1, the buffer control circuit 15 ′ sets the write / read signal C1 ′ to the high level in order for the buffer 12 ′ to start storing the digital data Dd. To do. Thereafter, the buffer control circuit 15 counts the number of data provided from the control unit 13 with the system clock, and then sets the write / read signal C1 'to the low level. The buffer 12 'stores the digital data Dd around the rising edge of the analog input signal Sa and then ends the storage of the digital data Dd, and outputs the digital data Dd stored in the buffer 12' to the event detection circuit 16 '.

  The buffer control circuit 15 ′ stores the digital data Dd for detecting the wide pulse width W, that is, the digital data Dd around the falling edge of the analog input signal Sa in the buffer 12 ″. The period from the start to the end is controlled based on the trigger signal T2 and the number of data provided from the control unit 13. In the present embodiment, when the buffer control circuit 15 ′ receives the trigger signal T2, the buffer control circuit 15 ′ sets the write / read signal C1 ″ to the high level in order for the buffer 12 ″ to start storing the digital data Dd. To do. Thereafter, the buffer control circuit 15 counts the number of data provided from the control unit 13 with the system clock, and then sets the write / read signal C1 ″ to the low level. The buffer 12 ″ is located around the falling edge of the analog input signal Sa. After the digital data Dd is stored, the storage of the digital data Dd is terminated, and the digital data Dd stored in the buffer 12 ″ is output to the event detection circuit 16 ′.

  The buffer control circuit 15 ′ uses the system clock based on the write / read signal C1 ′ and the write / read signal C1 ″ for the period from when the buffer 12 ′ stops storing until the buffer 12 ″ starts storing. Use to measure.

  In the present embodiment, the buffer control circuit 15 ′ adjusts the period from the start of the storage operation to the end of the buffer 12 ′, 12 ″ so that the time at which the trigger signals T1, T2 are generated is adjusted. Various other requirements are taken into account, for example, the delay time from the generation of the trigger signal T1 to the control of the buffer 12 ′, the delay time from the generation of the trigger signal T2 to the control of the buffer 12 ″, the trigger signal The difference between the timing of generating T1 and the timing of storing the digital data Dd in the buffer 12 ′, from the end of the period from when the write / read signal C1 ′ is output until the buffer 12 ′ stops storing the buffer 12 ′ Including the number of extra data necessary for the interpolation process, etc. Information about various requirements is provided, for example, through the operation of the operation unit. From may be provided to the buffer control circuit 15 '.

  As shown in FIG. 6, the event detection circuit 16 ′ includes an event detection control circuit 16a, an interpolation processing circuit 16b ′, a time detection processing circuit 16c ′, a level detection processing circuit 16d ′, an event determination circuit 16e, Have

  The buffer control circuit 15 ′ provides the time detection processing circuit 16c ′ with a measurement result Tm in a period from when the buffer 12 ′ stops storing until the buffer 12 ″ starts storing. Also, the buffer control circuit 15 ′. Outputs a level detection period signal C12 to the level detection processing circuit 16d ′ during a period from when the buffer 12 ′ stops storing until the buffer 12 ″ starts storing.

  The interpolation processing circuit 16b ′ is supplied with the digital data Dd for detecting the event from the buffer 12 ′ and the buffer 12 ″, and performs the interpolation processing of the digital data Dd at the interpolation magnification H to obtain the interpolation data Dh ′ and Dh ″. Generated and supplied to the time detection processing circuit 16c ′. Further, the interpolation processing circuit 16b ′ outputs the time detection signal C11 ′ to the time detection processing circuit 16c ′ during the provision period of the interpolation data Dh ′, and performs the time detection processing of the time detection signal C11 ″ during the provision period of the interpolation data Dh ″. Output to the circuit 16c '.

  The time detection processing circuit 16c 'detects the positive slope time from the interpolation data Dh' according to the time detection signal C11 ', and detects the negative slope time from the interpolation data Dh "according to the time detection signal C11". Further, the time detection processing circuit 16c ′ supplies the event determination circuit 16e with the detection processing result Dt of the pulse width obtained by calculating the positive slope time and the negative slope time and the measurement result Tm provided from the buffer control circuit 15 ′. . The time detection processing circuit 16c 'can detect the time with high accuracy by using the interpolation data Dh', Dh "and the measurement result Tm.

  The level detection processing circuit 16d ′ receives the digital data Dd from the ADC 11, detects the maximum detection processing result De (digital data level) of the digital data Dd in accordance with the level detection period signal C12, and determines the event determination circuit 16e. To supply. The event determination circuit 16e uses the digital data Dd input from the ADC 11 so that the maximum value of the digital data Dd during the period from the end of the period stored in the buffer 12 ′ to the start of the period stored in the buffer 12 ″ is stored. L can be detected.

  FIG. 7 is a diagram illustrating another example of an event detected by the event detection circuit. When the event is a pulse having a wide pulse width (for example, 1 microsecond), a period S from the end of the storage of the buffer 12 ′ to the start of the storage of the buffer 12 ″ is provided. It is determined whether or not the period Ti ′ from the slope time to the negative slope time corresponds to the pulse width W, and whether or not the maximum value L of the digital data Dd corresponds to the maximum value Pm. 16e indicates whether or not a period Ti ′ from the positive slope time to the negative slope time exists between an upper limit value (for example, 1000.1 nanoseconds) and a lower limit value (for example, 999.9 nanoseconds), and digital data It is determined whether or not the maximum value L of Dd exists between the upper limit value and the lower limit value.

  In the present embodiment, the period S from the end of storage of the buffer 12 ′ to the start of storage of the buffer 12 ″ is set as the detection period of the maximum value L. As a modification of the present embodiment, the maximum value It is possible to extend the detection period of L to a period Ti ′ from the positive slope time to the negative slope time.For example, the time detection processing circuit 16c is preceded by the interpolation data Dh ′ after the positive slope time and the negative slope time. Is provided to the level detection processing circuit 16d ', the level detection processing circuit 16d' can set the period Ti '.

  According to the present embodiment, the buffer 12 ′ stores the digital data Dd around the rising edge of the analog input signal Sa and the buffer 12 ″ stores the digital data Dd around the falling edge of the analog input signal Sa. A wide pulse width can be detected with high accuracy without increasing the buffer capacity.

  In the above embodiment, the case where the pulse width is detected as an event has been described. However, an event other than the pulse width, for example, at least one of the level in which the digital data Dd and the digital data Dd are detected from a predetermined level is detected. The present invention can also be applied to the case of detecting an event related to. FIG. 8 is a diagram illustrating another example of an event detected by the event detection circuit. The event detection circuit 16 (FIG. 1) has hysteresis determined by a transition time between two threshold values Th ′ and Th ″ (Th ′ <Th ″), and a minimum value L ′ and a maximum value L ″ of the interpolation data Dh. A rising edge as shown in FIG. 8 defined by the quantity h (maximum value L ″ −minimum value L ′) can also be detected as an event. In this case, the trigger condition is that the rising edge of the analog input signal Sa detected based on the preset threshold level Th ′ and the rising edge of the analog input signal Sa detected based on the preset threshold level Th ″. In addition, the trigger condition information Xt is used to determine whether or not the analog input signal Sa is higher than the threshold level Th ′ and whether or not the analog input signal Sa is higher than the threshold level Th ″. Including the conditions.

  The information Xi regarding the event is necessary for the interpolation magnification H, the threshold level Th ′, Th ″ used to interpolate the digital data Dd, and the level of the digital data Dd to rise from the threshold level Th ′ to the threshold level Th ″. The time Tx to be included is included. The event information Xi includes a hysteresis amount H of the interpolation data Dh to be detected before the level of the digital data Dd rises from the threshold level Th ′ to the threshold level Th ″.

  The trigger circuit 14 responds to a rising edge of the analog input signal Sa detected based on a preset threshold level Th ′ and a rising edge of the analog input signal Sa detected based on a preset threshold level Th ″. In this case, the trigger circuit 14 compares the level of the analog input signal Sa with the threshold level Th ′ using a comparator, and the disable signal for the trigger circuit 14 is released. When the analog input signal Sa becomes higher than the threshold level Th ′ in the state, the trigger signal T1 is generated and transmitted to the buffer control circuit 15. The trigger circuit 14 also includes the level of the analog input signal Sa and the threshold level Th. ”With another comparator, and a disable signal (not shown) for the trigger circuit 14 is When the analog input signal Sa becomes higher than the threshold level Th ″ in the removed state, the trigger signal T2 is generated and transmitted to the buffer control circuit 15. The trigger circuit 14 sends the trigger signal T2 to the buffer control circuit 15. It is disabled after transmission.

  The event detection control circuit 16a provides information about the interpolation magnification H to the interpolation processing circuit 16b. In addition, the event detection control circuit 16a provides information about the threshold levels Th ′ and Th ″ to the time detection processing circuit 16c. The event detection control circuit 16a has the interpolation data Dh from the threshold level Th ′ to the threshold level Th ″. Information about the transition time Tx that should be taken before rising is provided to the event determination circuit 16e. Furthermore, the event detection control circuit 16a provides the event determination circuit 16e with information on the hysteresis amount H of the interpolation data Dh that should be detected before the level of the digital data Dd rises from the threshold level Th ′ to the threshold level Th ″. .

  The time detection processing circuit 16c detects and processes the time when the interpolation data Dh is higher than the threshold level Th ′ and the time when the interpolation data Dh is higher than the threshold level Th ″ according to the time detection signal C11. The signal C12 is output to the level detection processing circuit 16d, and the transition time detection processing result Dt is supplied to the event determination circuit 16e.

  The level detection processing circuit 16d detects and processes the minimum value L ′ (interpolation data level) and the maximum value L ″ (interpolation data level) of the interpolation data Dh according to the level detection period signal C12, and the hysteresis amount of the interpolation data Dh. The detection processing result De corresponding to is supplied to the event determination circuit 16e.

  The event determination circuit 16e determines whether or not an event has been detected from the digital data Dd stored in the buffer 12 until the detection processing results Dt and De and the interpolation data Dh rise from the threshold level Th ′ to the threshold level Th ″. The determination is made based on the transition time Tx to be required for the above and the hysteresis amount H of the interpolation data Dh.

  In FIG. 8, the transition time Ti ″ from when the interpolation data Dh passes the threshold level Th ′ from the bottom to the top until it passes the threshold level Th ″ from the bottom to the top is the detection processing result Dt of the time detection processing circuit 16c. Correspondingly, the difference (hysteresis amount h) between the maximum value L ″ and the minimum value L ′ of the interpolation data Dh generated during the transition time Ti ″ corresponds to the detection processing result De of the level detection processing circuit 16d.

  The event determination circuit 16e determines whether or not the transition time Ti ″ of the interpolation data Dh exists between the upper limit value (for example, 10.1 nanoseconds) and the lower limit value (for example, 9.9 nanoseconds) of Tx. The event determination circuit 16e determines whether or not the hysteresis amount h exists between the upper limit value and the lower limit value.

  Therefore, the non-monotonicity that occurs while the rising transition time of the analog input signal Sa detected based on the threshold level Th ′ and the threshold level Th ″ and the interpolation data Dh rise from the threshold level Th ′ to the threshold level Th ″ ( The hysteresis amount h) can be detected as an event. Similarly, the falling edge transition time of the analog input signal Sa detected based on the threshold level Th ′ and the threshold level Th ″ and the non-occurrence that occurs while the interpolation data Dh falls from the threshold level Th ′ to the threshold level Th ″. Monotonicity (hysteresis amount h) can be detected as an event.

  In the present embodiment, the hysteresis amount h is described as an example of the event condition, but the minimum value L ′ and the maximum value L ″ of the interpolation data Dh can also be used as the event condition.

  In the above embodiment, the case where the time detection process and the level detection process are performed at the time of event detection has been described. Becomes easier. That is, even when the event is related to at least one of the level of the digital data and the period in which the digital data is detected from the predetermined level, it is easy to obtain a desired event.

  Furthermore, when it is not required to detect an event with high accuracy, a long transition period can be detected by decimating the digital data Dd stored in the buffer 12.

  FIG. 9 is a diagram showing another embodiment of the waveform recording apparatus according to the present invention, and FIG. 10 is a diagram showing a part of FIG. 9 in detail. The waveform recording apparatus 1 ″ includes an ADC 11, buffers 12a, 12b, 12c, and 12d, a control unit 13, a trigger circuit 14 ′, a buffer control circuit 15 ″, an event detection circuit 16 ″, and an acquisition processing circuit 17. , A memory circuit 18, a waveform processing and display processing circuit 19, and a display device 20.

  The buffers 12a, 12b, 12c, and 12d, the buffer control circuit 15 ″, the event detection circuit 16 ″, the capture processing circuit 17, and the waveform processing and display processing circuit 19 are configured by, for example, an FPGA incorporating a memory.

  The trigger circuit 14 ′ generates the trigger signal T1 ′ according to the rising edge of the threshold level Th ′ of the analog input signal Sa based on two threshold levels Th ′ and Th ″ (Th ′ <Th ″) set in advance. Generating a trigger signal T2 ′ in response to a rising edge of the threshold level Th “, generating a trigger signal T3 ′ in response to a falling edge of the threshold level Th”, and in response to a falling edge of the threshold level Th ′ To generate a trigger signal T4 ′. In this embodiment, taking an event of a positive pulse having a gentle slope (a negative slope occurs after a positive slope) as an example, information Xt related to the trigger condition is that the trigger signal is T1 ′, T2 ′, T3 ′. , T4 ′ in this order. Therefore, for example, when a positive runt pulse exceeding the threshold level Th ′ and not exceeding the threshold level Th ″ is input to the analog input signal Sa, that is, after the trigger signal T1 ′ is generated, the trigger signal T2 ′, When the trigger signal T4 ′ is generated without generating T3 ′, the trigger circuit 14 ′ is initialized, and the disable signal for the trigger circuit 14 ′ is released (ie, the trigger signals T1 ′ and T2 ′). , T3 ′ and T4 ′ are all set to the low level), thereby making it possible to eliminate the invalid event detection operation.

  According to the present embodiment, with respect to a pulse event having a gentle slope, the rising transition time and the falling transition time of the analog input signal Sa detected based on the threshold level Th ′ and the threshold level Th ″ are determined with high accuracy. In order to detect, the buffer 12a for storing the digital data Dd around the rising edge of the threshold level Th ′ in the positive slope of the analog input signal Sa, and the buffer 12b for storing the digital data Dd around the rising edge of the threshold level Th ″ A buffer 12c for storing the digital data Dd around the falling edge of the threshold level Th ″ in the falling slope of the analog input signal Sa; a buffer 12d for storing the digital data Dd around the falling edge of the threshold level Th ′; In addition, the buffers 12a, 12b, 12c, 1 Information on the number of data of the digital data Dd stored in 2d is provided from the control unit 13 to the buffer control circuit 15 ".

  The buffer control circuit 15 ″ uses the buffer 12a to store digital data Dd for detecting a transition time of a gradual rising slope, that is, digital data Dd around the rising edge of the threshold level Th ′ of the analog input signal Sa. The period from the start of the storage operation to the end of the storage operation is controlled based on the trigger signal T1 ′ and the number of data provided from the control unit 13. In the present embodiment, the buffer control circuit 15 ″ controls the trigger signal. When T1 ′ is received, the buffer control circuit 15 ″ sets the write / read signal C1a to the high level so that the buffer 12a starts storing the digital data Dd. After counting the number of provided data with the system clock, the write / read signal C1a is To Reberu. The buffer 12a stores the digital data Dd around the rising edge of the threshold level Th ′ of the analog input signal Sa and then ends the storage of the digital data Dd. The digital data Dd stored in the buffer 12a is sent to the event detection circuit 16 ″. Output.

  The buffer control circuit 15 ″ stores the digital data Dd for detecting the transition time of the gentle rising slope, that is, the digital data Dd around the rising edge of the threshold level Th ″ of the analog input signal Sa in the buffer 12b. 12 ″ controls the period from the start of the storage operation to the end based on the trigger signal T2 ′ and the number of data provided from the control unit 13. In this embodiment, the buffer control circuit 15 ″ triggers. When the signal T2 ′ is received, the buffer control circuit 15 ″ sets the write / read signal C1b to the high level so that the buffer 12b starts storing the digital data Dd. After counting the number of data provided from the system clock, the write / read signal C1b is To Reberu. The buffer 12b stores the digital data Dd around the rising edge of the threshold level Th ″ of the analog input signal Sa, and then ends the storage of the digital data Dd. The digital data Dd stored in the buffer 12b is sent to the event detection circuit 16 ″. Output.

  The buffer control circuit 15 ″ measures the period from when the buffer 12a stops storing until the buffer 12b starts storing using the system clock based on the write / read signal C1a and the write / read signal C1b. .

  The buffer control circuit 15 ″ stores digital data Dd for detecting a transition time of a gradual falling slope, that is, digital data Dd around the falling edge of the threshold level Th ″ of the analog input signal Sa in the buffer 12c. The period from the start of the storage operation to the end of the buffer 12c is controlled based on the trigger signal T3 ′ and the number of data provided from the control unit 13. In the present embodiment, when the buffer control circuit 15 ″ receives the trigger signal T3 ′, the buffer control circuit 15 ″ sets the write / read signal C1c to high level in order for the buffer 12c to start storing the digital data Dd. . Thereafter, the buffer control circuit 15 ″ counts the number of data provided from the control unit 13 with the system clock, and then sets the write / read signal C1c to the low level. The buffer 12c has the threshold level Th ″ of the analog input signal Sa ″. After storing the digital data Dd around the falling edge, the storage of the digital data Dd is terminated, and the digital data Dd stored in the buffer 12c is output to the event detection circuit 16 ″.

  The buffer control circuit 15 ″ stores digital data Dd for detecting a gradual falling slope transition time, that is, digital data Dd around the falling edge of the threshold level Th ′ of the analog input signal Sa in the buffer 12d. The buffer 12d controls the period from the start to the end of the storage operation based on the trigger signal T4 ′ and the number of data provided from the control unit 13. In the present embodiment, the buffer control circuit 15 ″ When the trigger signal T4 ′ is received, the buffer control circuit 15 ″ sets the write / read signal C1d to the high level so that the buffer 12d starts storing the digital data Dd. After the number of data provided from 13 is counted by the system clock, the write / read signal C1d is To Reberu. The buffer 12d finishes storing the digital data Dd after storing the digital data Dd around the falling edge of the threshold level Th ′ of the analog input signal Sa, and the event detection circuit 16 ″ stores the digital data Dd stored in the buffer 12d. Output to.

  The buffer control circuit 15 ″ measures the period from when the buffer 12c stops storing to when the buffer 12d starts storing using the system clock based on the write / read signal C1c and the write / read signal C1d. .

  In the present embodiment, the buffer control circuit 15 ″ adjusts the period from the start of the storage operation of the buffers 12a, 12b, 12c, 12d to the end thereof, in order to adjust the trigger signals T1 ′, T2 ′, T3. In addition to the time when ', T4' is generated, various requirements are taken into account, for example, from the generation of trigger signals T1 ', T2', T3 ', T4' to buffers 12a, 12b, 12c, 12d. Delay time until control, trigger signal T1 ′, T2 ′, T3 ′, T4 ′ generation timing difference between digital data Dd stored in buffers 12a, 12b, 12c, 12d, write / read signal The number of extra data necessary for the interpolation process during the period from the output of C1a, C1b, C1c, C1d until the buffers 12a, 12b, 12c, 12d stop storing Information about. Various requirements, including, for example, may be provided to the buffer control circuit 15 'from the control unit 13 through the operation of the operation unit.

  As shown in FIG. 10, the event detection circuit 16 ″ includes an event detection control circuit 16a ″, an interpolation processing circuit 16b ″, a time detection processing circuit 16c ″, a level detection processing circuit 16d ″, and an event determination circuit 16e ″. And having.

  The event detection control circuit 16a ″ provides information about the interpolation magnification H to the interpolation processing circuit 16b ″, provides threshold levels Th ′ and Th ″ to the time detection processing circuit 16c ″, and rise transition time of the pulse to be detected. Information about Tr, falling transition time Tf, and maximum value Pm is provided to the event determination circuit 16e ″.

  The buffer control circuit 15 ″ measures the measurement result Tm ′ during the period from when the buffer 12a stops storing until the buffer 12b starts storing and from when the buffer 12c stops storing until the buffer 12d starts storing. The period measurement result Tm ″ is provided to the time detection processing circuit 16c ″. The buffer control circuit 15 ″ also outputs a level detection period signal during a period from when the buffer 12c stops storing until the buffer 12d starts storing. C12 is output to the level detection processing circuit 16d ″.

  The interpolation processing circuit 16b ″ receives digital data Dd for detecting an event from the buffers 12a, 12b, 12c, and 12d, and performs interpolation processing of the digital data Dd at the interpolation magnification H, thereby interpolating each of the interpolation data Dh1, Dh2. , Dh3, Dh4 are generated and supplied to the time detection processing circuit 16c ″. The interpolation processing circuit 16b ″ outputs time detection signals C11a, C11b, C11c, and C11d corresponding to the provision periods of the respective interpolation data Dh1, Dh2, Dh3, and Dh4 to the time detection processing circuit 16c ″.

  In accordance with the time detection signals C11a and C11b, the time detection processing circuit 16c ″ detects the positive slope start time when the interpolation data Dh1 is higher than the threshold level Th ′ and the positive slope end when the interpolation data Dh2 is higher than the threshold level Th ″. Time detection processing. Further, the time detection processing circuit 16c ″ detects the rising transition time obtained by calculating the positive slope start time and the positive slope stop time and the measurement result Tm ′ provided from the buffer control circuit 15 ″. Similarly, in the time detection processing circuit 16c ″, according to the time detection signals C11c and C11d, the negative slope start time when the interpolation data Dh3 is lower than the threshold level Th ″ and the interpolation data Dh4 are lower than the threshold level Th ′. The negative slope end time is detected. The time detection processing circuit 16c ″ detects the falling transition time obtained by calculating the negative slope start time and negative slope stop time and the measurement result Tm ″ provided from the buffer control circuit 15 ″. Time detection processing circuit 16c "Supplies a detection processing result Dt" consisting of a rising transition time and a falling transition time to the event determination circuit 16e ". The time detection processing circuit 16c ″ can perform time detection with high accuracy by using the interpolation data Dh1, Dh2, Dh3, Dh4 and the measurement results Tm ′, Tm ″.

  The level detection processing circuit 16d ″ receives the digital data Dd from the ADC 11, detects the maximum detection processing result De ″ (digital data level) of the digital data Dd according to the level detection period signal C12, and performs an event determination circuit. The event determination circuit 16e ″ uses the digital data Dd input from the ADC 11 so that the event determination circuit 16e ″ digitally outputs the period from the end of the period stored in the buffer 12b to the start of the period stored in the buffer 12c. The maximum value L of the data Dd can be detected.

  The event determination circuit 16e ″ determines whether or not an event has been detected from the digital data Dd stored in the buffers 12a, 12b, 12c, and 12d, the detection processing results Dt ″ and De ″, and the rise of a pulse that is an event detection condition 11 is a diagram illustrating an example of a pulse event having a gentle slope detected by the event detection circuit, based on the transition time Tr, the falling transition time Tf, and the maximum value Pm. In the case of a pulse event, the period Sx from the end of storage of the buffer 12a to the start of storage of the buffer 12b, the period Sy from the end of storage of the buffer 12b to the start of storage of the buffer 12c, the storage of the buffer 12c A period Sz from the end to the start of storage of the buffer 12d is provided. The circuit 16e ″ determines whether the period Tia during which the positive slope transitions corresponds to the rising transition time Tr, whether the period Tib during which the negative slope transitions corresponds to the falling transition time Tf, and the maximum of the digital data Dd It is determined whether or not the value L corresponds to the maximum value Pm.

  According to the present embodiment, the buffer 12a and the buffer 12b store the digital data Dd around the start and end of the rising slope of the analog input signal Sa, and the buffer 12c and the buffer 12d have the falling slope of the analog input signal Sa. By storing the digital data Dd around the start and end of this, the rising transition time and falling transition time of a pulse event having a gentle slope can be detected with high accuracy without increasing the buffer capacity.

  Although the case where one, two, or four buffers are used has been described in the above embodiment, three or five or more buffers may be used.

1,1 ', 1 "Waveform Recorder 11 Analog to Digital Converter (ADC)
12, 12 ', 12 ", 12a, 12b, 12c, 12d buffer 13 control unit 14, 14' trigger circuit 15, 15 ', 15" buffer control circuit 16, 16', 16 "event detection circuit 16a, 16a" event Detection control circuit 16b, 16b ', 16b "Interpolation processing circuit 16c, 16c', 16c" Time detection processing circuit 16d, 16d ', 16d "Level detection processing circuit 16e, 16e" Event determination circuit 17 Acquisition processing circuit 18 Memory circuit 19 Waveform processing and display processing circuit 20 Display

Claims (6)

A buffer that temporarily stores digital data generated by analog-to-digital conversion of an analog input signal;
A trigger circuit that generates a trigger signal from the analog input signal or the digital data based on a trigger condition;
A buffer control circuit for controlling a period from the start of the storage operation to the end of the buffer based on the trigger signal;
An event detection circuit that generates an event detection signal when an event is detected from digital data stored in the buffer at the end of a period from the start of the storage operation to the end of the buffer;
A memory circuit that stores waveform data generated by capturing the digital data and stops storing the waveform data in response to the event detection signal;
A waveform recording apparatus comprising: The buffer has a first buffer and a second buffer;
The trigger circuit generates a first trigger signal and a second trigger signal from the analog input signal or the digital data based on a trigger condition;
The buffer control circuit controls a period from when the first buffer starts a storage operation to the end based on the first trigger signal, and after the second buffer starts a storage operation Controlling the period until the end based on the second trigger signal, measuring the period from when the first buffer ends the storage operation to when the second buffer starts the storage operation,
The event detection circuit is configured such that the digital data stored in the first buffer and the second buffer perform a storage operation at the end of a period from when the first buffer starts the storage operation to the end. The waveform recording apparatus according to claim 1, wherein an event detection signal is generated when an event is detected from digital data stored in the second buffer at the end of a period from the start to the end. The buffer has a plurality of buffers;
The trigger circuit generates a plurality of trigger signals from the analog input signal or the digital data based on a trigger condition,
The buffer control circuit controls a period from the start of the storage operation to the end of the buffer based on the trigger signal, and a predetermined buffer of the plurality of buffers ends the storage operation. Measure one or more of the period from the start of the storage operation to the next buffer,
The event detection circuit outputs an event detection signal when an event is detected from digital data stored in the plurality of buffers at the end of a period from the start of the storage operation to the end of the plurality of buffers. The waveform recording device according to claim 1 to be generated.   The waveform according to any one of claims 1 to 3, wherein the event detection circuit detects an event related to at least one of a level of the digital data and a period in which digital data of a predetermined level is detected. Recording device.   The said memory circuit adjusts the timing which stops the memory | storage of the said waveform data based on the time difference of the timing which the said trigger signal is produced | generated, and the timing which the said event detection signal is produced | generated. The waveform recording apparatus according to one item.   The waveform recording apparatus according to claim 1, wherein the digital data temporarily stored in the buffer is decimated.

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