JP6844404B2 - Waveform recorder - Google Patents

Description

The present invention relates to a waveform recording device that records waveform data of an analog input signal.

Waveform recording devices used as digital oscilloscopes and the like have been conventionally proposed (for example, Patent Documents 1 and 2). Many trigger and search functions have been proposed to enable the waveform recorder to acquire, observe and analyze various events. When a pulse width trigger is used to realize the trigger function and the search function, the pulse width at the set trigger level is counted by the counting clock, and the triggered when the counted pulse width matches the preset pulse width. A signal is generated. In addition, a waveform recording device that searches for and displays a desired event after capturing waveform data has also been proposed.

Special Table 2009-503458 Gazette Japanese Unexamined Patent Publication No. 2003-344454

In the waveform recording device using the pulse width trigger, since the measurement clock for counting the pulse width is not synchronized with the analog input signal, it is necessary to allow an error corresponding to one count of the pulse width. In order to detect the pulse width with high accuracy, it is necessary to use a high frequency measurement clock, which has an inconvenience that the cost of the waveform recording device increases.

Further, in a waveform recording device that searches for and displays a desired event after capturing the waveform data, the desired event does not always exist in the captured waveform data. In particular, when detecting a rare event, it is necessary to repeat the acquisition of waveform data and the search process a plurality of times, and there is an inconvenience that a desired event cannot be detected with high efficiency.

An object of the present invention is to provide a waveform recording device capable of detecting a desired event related to a signal waveform with high accuracy and high efficiency without increasing the cost.

The waveform recording device according to the present invention generates a trigger signal from an analog input signal or digital data based on a buffer that temporarily stores digital data generated by analog-digital conversion of the analog input signal and a trigger condition. At the end of the trigger circuit, the buffer control circuit that controls the period from the start to the end of the storage operation of the buffer based on the trigger signal, and the period from the start to the end of the storage operation of the buffer. An event detection circuit that generates an event detection signal when an event is detected from the digital data stored in the buffer, and waveform data generated by capturing and processing the digital data are stored and responded to the event detection signal. It includes a memory circuit for stopping the storage of waveform data.

Preferably, the buffer has a first buffer and a second buffer, and the trigger circuit generates a first trigger signal and a second trigger signal from an analog input signal or digital data based on a trigger condition. , The buffer control circuit controls the period from the start to the end of the storage operation of the first buffer based on the first trigger signal, and from the start to the end of the storage operation of the second buffer. The period from the end of the storage operation of the first buffer to the start of the storage operation of the second buffer is controlled based on the first trigger signal and the second trigger signal. The event detection circuit controls based on the trigger signal of the first buffer, and the digital data stored in the first buffer and the second buffer at the end of the period from the start to the end of the storage operation of the first buffer. An event detection signal is generated when an event is detected from the digital data stored in the second buffer at the end of the period from the start to the end of the storage operation of the buffer.

Preferably, the buffer has a plurality of buffers, the trigger circuit generates a plurality of trigger signals from the analog input signal or the digital data based on the trigger condition, and the buffer control circuit starts the storage operation of the buffer. The period from the end to the end is controlled based on the trigger signal, and one of the periods from the end of the storage operation of a predetermined buffer among a plurality of buffers to the start of the storage operation of the next buffer. The event detection circuit measures one or more, and an event is detected when an event is detected from the digital data stored in the multiple buffers at the end of the period from the start to the end of the storage operation of the multiple buffers. Generate a detection signal.

Preferably, the event detection circuit detects an event related to at least one of the level of digital data and the period during which a predetermined level of digital data is detected.

Preferably, the memory circuit adjusts the timing at which the storage of the waveform data is stopped based on the time difference between the timing at which the trigger signal is generated and the timing at which the event detection signal is generated.

Digital data temporarily stored in the buffer may be decimation.

According to the present invention, a desired event related to a signal waveform can be detected with high accuracy and high efficiency without increasing the cost.

It is a figure which shows one Embodiment of the waveform recording apparatus by this invention. It is a figure which shows a part of FIG. 1 in detail. It is a figure which shows an example of the event detected by the event detection circuit. It is a flowchart which shows the waveform recording operation of the waveform recording apparatus shown in FIG. It is a figure which shows the other embodiment of the waveform recording apparatus by this invention. It is a figure which shows a part of FIG. 5 in detail. It is a figure which shows another example of the event detected by the event detection circuit. It is a figure which shows another example of the event detected by the event detection circuit. It is a figure which shows the other embodiment of the waveform recording apparatus by this invention. It is a figure which shows a part of FIG. 9 in detail. It is a figure which shows another example of the event detected by the event detection circuit.

An embodiment of the waveform recording apparatus according to the present invention will be described with reference to the drawings.
FIG. 1 is a diagram showing an embodiment of a waveform recording device according to the present invention, and FIG. 2 is a diagram showing a part of FIG. 1 in detail. The waveform recording device 1 shown in FIG. 1 is used as a digital oscilloscope or the like, and an analog input signal Sa is input from the outside.

The waveform recording device 1 includes an analog-to-digital converter (ADC) 11, a buffer 12, a control unit 13, a trigger circuit 14, a buffer control circuit 15, an event detection circuit 16, an acquisition processing circuit 17, and a memory. A circuit 18, a waveform processing and display processing circuit 19, and a display 20 are provided.

The control unit 13 is composed of, for example, a CPU. The buffer 12, the buffer control circuit 15, the event detection circuit 16, the acquisition processing circuit 17, and the waveform processing and display processing circuit 19 are composed of, for example, an FPGA (field-programmable gate array) having a built-in memory. The memory circuit 18 is composed of a memory for storing waveform data Dw, which will be described later, and a peripheral circuit for controlling the memory. The memory is composed of, for example, a DRAM (dynamic random access memory). The peripheral circuit is composed of, for example, an FPGA. The display 20 is composed of, for example, a liquid crystal display (LCD).

The ADC 11 converts the analog input signal Sa into digital data Dd (for example, an 8-bit digital value), and the digital data Dd is input to the buffer 12 and the acquisition processing circuit 17. When the sampling rate of the ADC 11 is 1 gigasample / sec, the digital data Dd is generated every 1 nanosecond, but the data processing is parallelized in the buffer 12 and the acquisition processing circuit 17 and the memory circuit 18 in the subsequent stage of the ADC 11. As a result, the processing speed can be reduced. For example, when a 125 MHz system clock (not shown) provided inside the FPGA is used, eight digital data Dds are processed in parallel every 8 nanoseconds.

The buffer 12 temporarily stores the digital data Dd based on the write / read signal C1 from the buffer control circuit 15. In the present embodiment, the buffer 12 starts the storage of the digital data Dd at the rising edge of the write / read signal C1, ends the storage of the digital data Dd at the falling edge of the write / read signal C1, and is stored in the buffer 12. The digital data Dd is output to the event detection circuit 16.

The control unit 13 provides the trigger circuit 14 with information Xt regarding the trigger condition. Further, the control unit 13 provides the event detection circuit 16 with information Xi regarding the event conditions. Further, the control unit 13 provides the waveform processing and display processing circuit 19 with information Xd regarding the waveform processing and display processing conditions of the waveform data Dw. Further, the control unit 13 outputs a command C2 for the memory circuit 18 to start the storage operation to the memory circuit 18. The information Xt regarding the trigger condition, the information Xi regarding the event condition, the information Xd regarding the waveform processing and display processing conditions of the waveform data Dw, and the command C2 are controlled by, for example, an operation unit (not shown) such as a keyboard. It is input to 13. Further, in response to the event detection signal Si described later, the control unit 13 terminates the storage operation of the memory circuit 18 and issues a command C3 to the memory circuit 18 for reading the waveform data Dw stored in the memory circuit 18. Output.

The present embodiment will be described by taking the case where the width and height (maximum value) of the positive pulse are selected as the condition of the event, but it is also possible to set the condition of the negative pulse. It is also possible to use an average value or the like instead of the pulse height.

In the present embodiment, the trigger conditions are the rising edge and the falling edge of the analog input signal Sa detected based on the preset threshold level Th. In this case, the information Xt regarding the trigger condition is whether or not the analog input signal Sa is above the threshold level Th and whether or not the analog input signal Sa is above the threshold level Th and then below the threshold level Th. Includes the condition that the judgment is made.

Further, in the present embodiment, the event is a pulse width W defined by a period during which the digital data Dd (more specifically, the interpolated data Dh described later) exceeds the threshold level Th. In this case, the information Xi regarding the condition of the event includes the interpolation magnification H used for interpolating the digital data Dd, the threshold level Th, the pulse width W of the pulse to be detected, and the maximum value Pm.

The trigger circuit 14 generates trigger signals T1 and T2 according to the rising edge and the falling edge of the analog input signal Sa detected based on the preset threshold level Th. In the present embodiment, the trigger circuit 14 compares the level of the analog input signal Sa with the threshold level Th using a comparator (not shown), and the disable signal (not shown) for the trigger circuit 14 is released. When the analog input signal Sa rises above the threshold level Th in this state, the trigger signal T1 is generated and transmitted to the buffer control circuit 15 (that is, the trigger signal T1 transitions from the low level to the high level). Further, the trigger circuit 14 triggers when the analog input signal Sa rises above the threshold level Th and then falls below the threshold level Th in a state where the disable signal (not shown) for the trigger circuit 14 is released. The signal T2 is generated and transmitted to the buffer control circuit 15 (that is, the trigger signal T2 transitions from low level to high level). The trigger circuit 14 is disabled after transmitting the trigger signal T2 to the buffer control circuit 15. The trigger circuit 14 does not generate the trigger signal T2 until the trigger signal T1 is generated. If the analog input signal Sa falls below the threshold level Th by the time a predetermined time elapses after the trigger signal T1 is generated, the trigger circuit 14 is initialized and the disable signal to the trigger circuit 14 is disabled. By returning to the released state (that is, the trigger signal T1 transitions from the high level to the low level), it is possible to eliminate the invalid event detection operation. Further, the trigger circuit 14 detects the rising edge and the falling edge of the digital data Dd based on the preset threshold level Th, and generates the trigger signals T1 and T2 according to the detected rising edge and the falling edge. You may.

The buffer control circuit 15 controls the period from the start to the end of the storage operation of the buffer 12 based on the trigger signals T1 and T2 in order to detect the event (pulse width W in this case) from the digital data Dd. .. In this embodiment, when the buffer control circuit 15 receives the trigger signal T1, the buffer 12 raises the write / read signal C1 to start storing the digital data Dd. Further, when the buffer control circuit 15 receives the trigger signal T2, the buffer control circuit 15 lowers the write / read signal C1 in order to end the storage of the digital data Dd and output the digital data Dd stored in the buffer 12 to the event detection circuit 16. Make it a level.

Further, in the present embodiment, the buffer control circuit 15 requires various requirements in addition to the time when the trigger signals T1 and T2 are generated in order to adjust the period from the start to the end of the storage operation of the buffer 12. Consider. Various requirements include, for example, the delay time from the generation of the trigger signal T1 to the control of the buffer 12, the delay time from the generation of the trigger signal T2 to the control of the buffer 12, the timing of the generation of the trigger signal T1 and the buffer of the digital data Dd. Includes the difference from the timing of storage to 12, the number of extra data required for interpolation processing, and the like. Information about various requirements may be provided from the control unit 13 to the buffer control circuit 15 via, for example, the operation of the operation unit.

The event detection circuit 16 generates an event detection signal Si when an event is detected from the digital data Dd stored in the buffer 12 at the end of the period from the start to the end of the storage operation of the buffer 12. .. In the present embodiment, as shown in FIG. 2, the event detection circuit 16 includes an event detection control circuit 16a, an interpolation processing circuit 16b, a time detection processing circuit 16c, a level detection processing circuit 16d, and an event determination circuit 16e. And have.

In the event detection control circuit 16a, information Xi regarding event conditions is provided by the control unit 13. Then, the event detection control circuit 16a provides information about the interpolation magnification H to the interpolation processing circuit 16b, provides the threshold level Th to the time detection processing circuit 16c, and describes the pulse width W and the maximum value Pm of the pulse to be detected. Information is provided to the event determination circuit 16e.

The interpolation processing circuit 16b generates the interpolation data Dh by supplying the digital data Dd for detecting the event from the buffer 12 and performing the interpolation processing of the digital data Dd at the interpolation magnification H, and the time detection processing circuit 16c and the level. It is supplied to the detection processing circuit 16d. For the interpolation processing, general sin (x) / x interpolation, linear interpolation, a combination thereof, or the like can be used. When the interpolation magnification H is 100, the digital data Dd every 1 nanosecond is converted into the interpolation data Dh every 10 picoseconds. Further, the interpolation processing circuit 16b outputs the time detection signal C11 to the time detection processing circuit 16c during the output period of the interpolation data Dh.

The time detection processing circuit 16c detects and processes the positive slope time and the negative slope time according to the time detection signal C11, outputs the level detection period signal C12 to the level detection processing circuit 16d, and outputs the pulse width detection processing result Dt. It is supplied to the event determination circuit 16e. The time detection processing circuit 16c enables highly accurate time detection by using the interpolated data Dh. In the time detection process, a generally used hysteresis process may be performed in order to prevent erroneous measurement due to noise or the like of the analog input signal Sa. Further, the negative slope time may be used as a reference for the time axis when the waveform is later displayed on the display 20.

The level detection processing circuit 16d detects and processes the detection processing result De (interpolated data level) of the maximum value L of the interpolation data Dh according to the level detection period signal C12, and supplies the detection processing result De to the event determination circuit 16e.

The event determination circuit 16e determines whether or not an event has been detected from the digital data Dd stored in the buffer 12 based on the detection processing results Dt and De, the pulse width W which is the event detection condition, and the maximum value Pm. .. FIG. 3 is a diagram showing an example of a positive pulse event detected by the event detection circuit. In FIG. 3, the period Ti from the positive slope time to the negative slope time across the threshold level Th corresponds to the detection processing result Dt of the time detection processing circuit, and the maximum value L of the interpolated data Dh in the period Ti is the level detection processing. Corresponds to the circuit detection processing result De. The event determination circuit 16e determines whether or not the detection processing result Dt corresponds to the pulse width W and whether or not the detection processing result De corresponds to the maximum value Pm. More specifically, in the event determination circuit 16e, whether or not the detection processing result Dt exists between the upper limit value (for example, 20.1 nanoseconds) and the lower limit value (for example, 19.9 nanoseconds) of the pulse width W. And, it is determined whether or not the detection processing result De exists between the upper limit value and the lower limit value of the maximum value Pm.

With reference to FIG. 1, when an event is detected from the digital data Dd stored in the buffer 12, the event determination circuit 16e supplies the event detection signal Si to the control unit 13 and the memory circuit 18. On the other hand, when an event is not detected from the digital data Dd stored in the buffer 12, the event determination circuit 16e supplies the trigger circuit 14 with a release signal Ss for releasing the disable signal for the trigger circuit 14. .. If the period Ti from the positive slope time to the negative slope time is significantly larger than the pulse width W, the pulse width detection processing result Dt may not be normally detected by the time detection processing circuit 16c. In such a case, the buffer control circuit 15 or the time detection processing circuit 16c may supply the release signal Ss to the trigger circuit 14 without waiting for the determination by the event determination circuit 16e (not shown).

The acquisition processing circuit 17 generates waveform data Dw by performing acquisition processing of digital data Dd (peak detection and averaging processing at regular intervals, decimation (thinning out), etc.), and the generated waveform data Dw is used as the memory circuit 18 Store in. The capture mode for performing the capture process of the digital data Dd may be selected by the control unit 13 via, for example, the operation of the operation unit.

The memory circuit 18 starts the storage operation of the waveform data Dw in response to the command C2, and stores the number of waveform data Dw set as the data to be stored in the memory circuit 18 as the pre-trigger (before the trigger is generated). .. After that, the control unit 13 releases the disable signal for the trigger circuit 14. Then, the memory circuit 18 continues the storage operation of the waveform data Dw even after the disable signal for the trigger circuit 14 is released, and waits for the event detection signal Si from the event detection circuit 16. When the event detection signal Si is supplied from the event detection circuit 16 to the memory circuit 18, the memory circuit 18 post-triggers (after the trigger occurs) the number of waveform data Dw set based on the display time condition of the display 20. ) After storing as minutes, the storage of the waveform data Dw is stopped.

In order to control the number of waveform data Dw stored in the memory circuit 18 with reference to the time of the detected event, the memory circuit 18 generates a trigger signal T2 at the timing when the storage of the waveform data Dw is stopped. It is preferable to adjust based on the timing. The time difference between the timing at which the trigger signal T2 is generated and the timing at which the event detection signal Si is generated is measured, for example, by counting with the system clock. Further, in order to control the number of waveform data Dw stored in the memory circuit 18, the time difference between the timing when the trigger signal T2 is generated and the timing when the event detection signal Si is generated is predicted in advance, and the predicted time difference is calculated. It may be reflected in the number of waveform data Dw to be stored as the post-trigger portion or the overrun (extra number of writes) of the memory circuit 18.

In response to the command C3, the memory circuit 18 reads out the waveform data Dw and outputs the waveform data Dw to the waveform processing and display processing circuit 19. The waveform processing and display processing circuit 19 performs waveform processing and display processing of the waveform data Dw based on the information Xd regarding the waveform processing and display processing conditions of the waveform data Dw provided by the control unit 13. Then, the waveform processing and display processing circuit 19 supplies the waveform data Dwd in which the waveform processing and the display processing have been performed to the display 20, and the display 20 displays the waveform data Dwd in which the waveform processing and the display processing have been performed. To do.

FIG. 4 is a flowchart showing a waveform recording operation of the waveform recording device shown in FIG. This flow is based on the premise that the trigger signals T1 and T2 are generated after the disable period is released after the waveform recording device 1 starts the waveform recording operation. First, the memory circuit 18 starts the storage operation of the waveform data Dw in response to the command C2 (step S1). In this case, the memory circuit 18 continues to store the waveform data Dw even after the waveform data Dw for the pre-trigger is stored and the disable signal for the trigger circuit 14 is released.

Next, the trigger circuit 14 generates a trigger signal T1 based on the trigger condition (rising edge) (step S2). Next, the buffer control circuit 15 raises the write / read signal C1 in response to the trigger signal T1, and the buffer 12 starts storing the digital data Dd in response to the write / read signal C1 (step S3). ).

Next, the trigger circuit 14 generates a trigger signal T2 based on the trigger condition (falling edge) (step S4). Next, the buffer control circuit 15 lowers the write / read signal C1 in response to the trigger signal T2, the buffer 12 ends the storage of the digital data Dd in response to the write / read signal C1, and the digital data. Dd is supplied to the interpolation processing circuit 16b (step S5).

Next, the interpolation processing circuit 16b performs interpolation processing of the digital data Dd supplied from the buffer 12 (step S6). Next, the time detection processing circuit 16c detects and processes the pulse width detection processing result Dt from the positive slope time and the negative slope time, and the level detection processing circuit 16d detects the maximum value from the interpolated data Dh according to the level detection period signal C12. Detection processing result De is detected and processed (step S7). Steps S6 and S7 explain the functional procedure, and are sequentially processed in the pipeline in order to shorten the time for event detection processing in terms of circuit operation.

Next, the event determination circuit 16e determines whether or not an event has been detected from the digital data Dd stored in the buffer 12 (step S8). If no event is detected, the process returns to step S2.

On the other hand, when an event is detected, the memory circuit 18 stops the storage of the waveform data Dw after storing the number of waveform data Dw set as the post-trigger portion (step S9). Next, the waveform processing and display processing circuit 19 performs waveform processing and display processing of the waveform data Dw stored in the memory circuit 18, and the display 20 displays the waveform data Dwd in which the waveform processing and display processing have been performed. (Step S10). After that, the waveform recording device 1 ends the process.

According to the present embodiment, since the event is detected in real time from the digital data Dd stored in the buffer 12 in parallel with the storage of the waveform data Dw in the memory circuit 18, a period of interruption and resumption of waveform recording occurs. Can be avoided.

Further, since the digital data Dd used for event detection is limited to the vicinity of the generation timing of the trigger signals T1 and T2, highly efficient event detection is possible. Further, by performing the event detection using the interpolated data Dh, it is possible to detect the event with high accuracy without using a high frequency counting clock, and it is possible to avoid an increase in the cost of the waveform recording device 1. In addition, event detection independent of the digital data Dd acquisition process becomes possible. Further, by performing the time detection process and the level detection process at the time of event detection, it becomes easy to acquire a desired event.

Further, when it is not required to detect the event with high accuracy, a wide pulse width can be detected by desimating the digital data Dd stored in the buffer 12.

FIG. 5 is a diagram showing another embodiment of the waveform recording apparatus according to the present invention, and FIG. 6 is a diagram showing a part of FIG. 5 in detail. The waveform recording device 1'is an ADC 11, a buffer 12', 12', a control unit 13, a trigger circuit 14, a buffer control circuit 15', an event detection circuit 16', an acquisition processing circuit 17, and a memory circuit. It includes 18, a waveform processing and display processing circuit 19, and a display 20.

The buffer 12', the buffer 12', the buffer control circuit 15', the event detection circuit 16', the acquisition processing circuit 17, and the waveform processing and display processing circuit 19 are composed of, for example, an FPGA having a built-in memory.

It is necessary to increase the buffer capacity as the pulse width, which is an event to be detected, becomes wider. In the present embodiment, in order to detect a wide pulse width with high accuracy without increasing the buffer capacity, the buffer 12'that stores the digital data Dd around the rising edge of the analog input signal Sa and the standing of the analog input signal Sa. A buffer 12 "that stores the digital data Dd around the falling edge is used. The buffer 12'is an example of the first buffer, and the buffer 12" is an example of the second buffer. Further, the information on the number of digital data Dd stored in the buffer 12'and the buffer 12'is provided from the control unit 13 to the buffer control circuit 15'.

In the buffer control circuit 15', the buffer 12'starts a storage operation in order to store the digital data Dd for detecting the wide pulse width W, that is, the digital data Dd around the rising edge of the analog input signal Sa in the buffer 12'. The period from the completion to the end is controlled based on the number of data provided by the trigger signal T1 and the control unit 13. In the present embodiment, when the buffer control circuit 15'receives the trigger signal T1, the buffer control circuit 15'sets the write / read signal C1' to a high level so that the buffer 12'starts storing the digital data Dd. To do. Then, the buffer control circuit 15 ', the write / read signal C1 after the number of data provided from the control unit 13 and counted by the system clock' to the low level. The buffer 12'ends the storage of the digital data Dd after storing the digital data Dd around the rising edge of the analog input signal Sa, and outputs the digital data Dd stored in the buffer 12' to the event detection circuit 16'.

In the buffer control circuit 15', the buffer 12 "stores the digital data Dd for detecting the wide pulse width W, that is, the digital data Dd around the falling edge of the analog input signal Sa in the buffer 12". The period from the start to the end is controlled based on the number of data provided by the trigger signal T2 and the control unit 13. In the present embodiment, when the buffer control circuit 15'receives the trigger signal T2, the buffer control circuit 15'sets the write / read signal C1'to a high level so that the buffer 12' starts storing the digital data Dd. To do. Then, the buffer control circuit 15 '' to the low level. Buffer 12 "write / read signal C1 after the number of data provided from the control unit 13 and counted by the system clock, the falling edge of the analog input signal Sa After storing the peripheral digital data Dd, the storage of the digital data Dd is terminated, and the digital data Dd stored in the buffer 12 "is output to the event detection circuit 16'.

The buffer control circuit 15'sets the system clock based on the write / read signal C1'and the write / read signal C1'for the period from when the buffer 12'stops storage to when the buffer 12' starts storage. Use to measure.

Further, in the present embodiment, the buffer control circuit 15'is the time during which the trigger signals T1 and T2 are generated in order to adjust the period from the start to the end of the storage operation of the buffers 12', 12 ". Various other requirements are considered. The various requirements are, for example, the delay time from the generation of the trigger signal T1 to the control of the buffer 12', the delay time from the generation of the trigger signal T2 to the control of the buffer 12', and the trigger signal. The difference between the generation timing of T1 and the storage timing of the digital data Dd in the buffer 12', the buffer 12 from the end of the period from the output of the write / read signal C1'to the stop of the storage of the buffer 12'. "The period until the start of storage, the number of extra data required for interpolation processing, etc. Information about various requirements is transmitted from the control unit 13 to the buffer control circuit 15'through the operation of the operation unit, for example. May be provided.

As shown in FIG. 6, the event detection circuit 16' includes an event detection control circuit 16a, an interpolation processing circuit 16b', a time detection processing circuit 16c', a level detection processing circuit 16d', and an event determination circuit 16e. Has.

The buffer control circuit 15'provides to the time detection processing circuit 16c' a measurement result Tm of the period from when the buffer 12'stops storage to when the buffer 12' starts storage. Further, the buffer control circuit 15'provides the time detection processing circuit 15'. Outputs the level detection period signal C12 to the level detection processing circuit 16d'during the period from when the buffer 12'stops storage to when the buffer 12' starts storage.

In the interpolation processing circuit 16b', digital data Dd for detecting an event is supplied from the buffer 12'and the buffer 12', and the interpolation data Dh', Dh' is generated by performing the interpolation processing of the digital data Dd at the interpolation magnification H. It is generated and supplied to the time detection processing circuit 16c'. Further, the interpolation processing circuit 16b'outputs the time detection signal C11'to the time detection processing circuit 16c' during the provision period of the interpolation data Dh', and the time detection signal C11'is time-detected during the provision period of the interpolation data Dh'. Output to circuit 16c'.

The time detection processing circuit 16c'detects and processes the positive slope time from the interpolated data Dh'according to the time detection signal C11', and detects and processes the negative slope time from the interpolated data Dh'according to the time detection signal C11'. Further, the time detection processing circuit 16c'supplyes the pulse width detection processing result Dt obtained by calculating the positive slope time, the negative slope time, and the measurement result Tm provided by the buffer control circuit 15' to the event determination circuit 16e. .. The time detection processing circuit 16c'can enable highly accurate time detection by using the interpolated data Dh', Dh' and the measurement result Tm.

In the level detection processing circuit 16d', the digital data Dd is input from the ADC 11, and the detection processing result De (digital data level) of the maximum value of the digital data Dd is detected and processed according to the level detection period signal C12, and the event determination circuit 16e Supply to. By using the digital data Dd input from the ADC 11, the event determination circuit 16e uses the maximum value of the digital data Dd in the period from the end of the period stored in the buffer 12'to the start of the period stored in the buffer 12'. L can be detected and processed.

FIG. 7 is a diagram showing another example of an event detected by the event detection circuit. When the event is a pulse with a wide pulse width (for example, 1 microsecond), a period S from the end of the storage of the buffer 12'to the start of the storage of the buffer 12' is provided. The event determination circuit 16e is positive. It is determined whether or not the period Ti'from the slope time to the negative slope time corresponds to the pulse width W and whether or not the maximum value L of the digital data Dd corresponds to the maximum value Pm. More specifically, the event determination circuit. In 16e, whether or not the period Ti'from the positive slope time to the negative slope time exists between the upper limit value (for example, 1000.1 nanoseconds) and the lower limit value (for example, 999.9 nanoseconds) and digital data. It is determined whether or not the maximum value L of Dd exists between the upper limit value and the lower limit value.

In the present embodiment, the period S from the end of the storage of the buffer 12'to the start of the storage of the buffer 12' is set as the detection period of the maximum value L, but as a modification of the present embodiment, the maximum value is set. The detection period of L can be extended to the period Ti'from the positive slope time to the negative slope time. For example, the time detection processing circuit 16c is before the interpolation data Dh'after the positive slope time and the negative slope time. By providing the interpolated data Dh "of the above to the level detection processing circuit 16d', the level detection processing circuit 16d'can set the period Ti'.

According to the present embodiment, the buffer 12'stores the digital data Dd around the rising edge of the analog input signal Sa, and the buffer 12' stores the digital data Dd around the falling edge of the analog input signal Sa. , A wide pulse width can be detected with high accuracy without increasing the buffer capacity.

In the above embodiment, the case where the pulse width is detected as an event has been described, but an event other than the pulse width, for example, at least one of the level of the digital data Dd and the period during which the digital data Dd is detected from the predetermined level. The present invention can also be applied to detect events related to. FIG. 8 is a diagram showing another example of an event detected by the event detection circuit. The event detection circuit 16 (FIG. 1) has a hysteresis determined by the transition time between the two threshold values Th', Th'(Th' <Th'), and the minimum value L'and the maximum value L'of the interpolated data Dh. The rising edge as shown in FIG. 8 defined by the quantity h (maximum value L "-minimum value L') can also be detected as an event. In this case, the trigger condition is the rising edge of the analog input signal Sa detected based on the preset threshold level Th'and the rising edge of the analog input signal Sa detected based on the preset threshold level Th'. Further, the information Xt regarding the trigger condition determines whether or not the analog input signal Sa is above the threshold level Th'and whether or not the analog input signal Sa is above the threshold level Th'". Including the conditions of.

Information about the event Xi is required for the interpolation magnification H used for interpolating the digital data Dd, the threshold level Th', Th ", and the level of the digital data Dd to rise from the threshold level Th'to the threshold level Th". Includes time Tx to be done. Further, the information Xi regarding the event includes a hysteresis amount H of the interpolated data Dh to be detected before the level of the digital data Dd rises from the threshold level Th'to the threshold level Th'.

The trigger circuit 14 responds to the rising edge of the analog input signal Sa detected based on the preset threshold level Th'and the rising edge of the analog input signal Sa detected based on the preset threshold level Th'. In this case, the trigger circuit 14 compares the level of the analog input signal Sa with the threshold level Th'using a comparator, and the disable signal for the trigger circuit 14 is released. When the analog input signal Sa rises above the threshold level Th'in the state, the trigger signal T1 is generated and transmitted to the buffer control circuit 15. The trigger circuit 14 also generates the level of the analog input signal Sa and the threshold level Th. When the analog input signal Sa rises above the threshold level Th ”in the state where the disable signal (not shown) for the trigger circuit 14 is released, the trigger signal T2 is set. Generated and transmitted to the buffer control circuit 15. The trigger circuit 14 is disabled after transmitting the trigger signal T2 to the buffer control circuit 15.

The event detection control circuit 16a provides the interpolation processing circuit 16b with information about the interpolation magnification H. Further, the event detection control circuit 16a provides information about the threshold level Th', Th'to the time detection processing circuit 16c. In the event detection control circuit 16a, the interpolation data Dh is from the threshold level Th'to the threshold level Th'. Information about the transition time Tx that should be required to rise is provided to the event determination circuit 16e. Further, the event detection control circuit 16a provides the event determination circuit 16e with information about the hysteresis amount H of the interpolated data Dh to be detected until the level of the digital data Dd rises from the threshold level Th'to the threshold level Th'. ..

The time detection processing circuit 16c detects and processes the time when the interpolated data Dh is above the threshold level Th'and the time when the interpolated data Dh is above the threshold level Th'" according to the time detection signal C11, and performs a level detection period. The signal C12 is output to the level detection processing circuit 16d, and the transition time detection processing result Dt is supplied to the event determination circuit 16e.

The level detection processing circuit 16d detects and processes the minimum value L'(interpolation data level) and the maximum value L "(interpolation data level) of the interpolation data Dh according to the level detection period signal C12, and the hysteresis amount of the interpolation data Dh. The detection processing result De corresponding to is supplied to the event determination circuit 16e.

The event determination circuit 16e determines whether or not an event has been detected from the digital data Dd stored in the buffer 12 until the detection processing results Dt, De and the interpolated data Dh rise from the threshold level Th'to the threshold level Th'. Judgment is made based on the transition time Tx required for the above and the hysteresis amount H of the interpolated data Dh.

In FIG. 8, the transition time Ti ”from the interpolation data Dh passing the threshold level Th'from the bottom to the top passing the threshold level Th ″ from the bottom to the top is the detection processing result Dt of the time detection processing circuit 16c. Correspondingly, the difference (hysteresis amount h) between the maximum value L "and the minimum value L'of the interpolated data Dh generated in the transition time Ti" corresponds to the detection processing result De of the level detection processing circuit 16d.

The event determination circuit 16e determines whether or not the transition time Ti "of the interpolated data Dh exists between the upper limit value (for example, 10.1 nanoseconds) and the lower limit value (for example, 9.9 nanoseconds) of Tx. Further, the event determination circuit 16e determines whether or not the hysteresis amount h exists between the upper limit value and the lower limit value.

Therefore, the rising transition time of the analog input signal Sa detected based on the threshold level Th'and the threshold level Th'and the non-monotonicity that occurs while the interpolated data Dh rises from the threshold level Th'to the threshold level Th'. The hysteresis amount h) can be detected as an event. Similarly, the falling edge transition time of the analog input signal Sa detected based on the threshold level Th'and the threshold level Th'and the non-occurrence that occurs while the interpolated data Dh descends from the threshold level Th'to the threshold level Th'. Monotonicity (hysteresis amount h) can be detected as an event.

In the present embodiment, the hysteresis amount h has been described as an example of the event condition, but it is also possible to set the minimum value L'and the maximum value L "of the interpolated data Dh as the event condition.

In the above embodiment, the case where the time detection process and the level detection process are performed at the time of event detection has been described. However, even when at least one of the time detection process and the level detection process is performed at the time of event detection, a desired event is acquired. Becomes easier. That is, it is easy to obtain the desired event even when the event is related to at least one of the level of the digital data and the period during which the digital data is detected from the predetermined level.

Further, when the event is not required to be detected with high accuracy, a long transition period can be detected by desimating the digital data Dd stored in the buffer 12.

FIG. 9 is a diagram showing another embodiment of the waveform recording device according to the present invention, and FIG. 10 is a diagram showing a part of FIG. 9 in detail. The waveform recording device 1 "includes the ADC 11, the buffers 12a, 12b, 12c, 12d, the control unit 13, the trigger circuit 14', the buffer control circuit 15", the event detection circuit 16 ", and the acquisition processing circuit 17. , A memory circuit 18, a waveform processing and display processing circuit 19, and a display 20.

The buffers 12a, 12b, 12c, 12d, the buffer control circuit 15 ", the event detection circuit 16", the acquisition processing circuit 17, and the waveform processing and display processing circuit 19 are composed of, for example, an FPGA having a built-in memory.

The trigger circuit 14'sets a trigger signal T1'according to the rising edge of the threshold level Th'of the analog input signal Sa based on two preset threshold levels Th', Th'(Th'<Th'). Generate, generate a trigger signal T2'according to the rising edge of the threshold level Th", generate a trigger signal T3'according to the falling edge of the threshold level Th ", and respond to the falling edge of the threshold level Th'. To generate the trigger signal T4'. In the present embodiment, taking a positive pulse event with a gentle slope (a negative slope occurs after the positive slope) as an example, the information Xt regarding the trigger condition has trigger signals of T1', T2', and T3'. , T4'includes information that occurs in that order. Therefore, for example, when a positive runt pulse that exceeds the threshold level Th'and does not exceed the threshold level Th'is input to the analog input signal Sa, that is, after the trigger signal T1'is generated, the trigger signal T2', When the trigger signal T4'is generated without generating T3', the trigger circuit 14'is initialized and the disable signal for the trigger circuit 14'is released (that is, the trigger signals T1'and T2' are released. , T3'and T4'are all set to the low level.) By returning to the low level, it is possible to eliminate the invalid event detection operation.

According to the present embodiment, for a pulse event having a gentle slope, the rising transition time and the falling transition time of the analog input signal Sa detected based on the threshold level Th'and the threshold level Th'are set with high accuracy. In order to detect, a buffer 12a for storing the digital data Dd around the rising edge of the threshold level Th'on the positive slope of the analog input signal Sa, and a buffer 12b for storing the digital data Dd around the rising edge of the threshold level Th'". , A buffer 12c for storing the digital data Dd around the falling edge of the threshold level Th "in the falling slope of the analog input signal Sa, and a buffer 12d for storing the digital data Dd around the falling edge of the threshold level Th'. The information on the number of digital data Dd stored in the buffers 12a, 12b, 12c, and 12d is provided by the control unit 13 to the buffer control circuit 15 ".

The buffer control circuit 15 ”is a buffer for storing the digital data Dd for detecting the transition time of the gentle rising slope, that is, the digital data Dd around the rising edge of the threshold level Th'of the analog input signal Sa in the buffer 12a. The period from the start to the end of the storage operation of 12a is controlled based on the trigger signal T1'and the number of data provided by the control unit 13. In the present embodiment, the buffer control circuit 15 "controls the trigger signal. Upon receiving T1', the buffer control circuit 15 "sets the write / read signal C1a to a high level in order for the buffer 12a to start storing the digital data Dd. After that, the buffer control circuit 15" starts from the control unit 13. After counting the number of provided data with the system clock, the write / read signal C1a is set to a low level. The buffer 12a ends the storage of the digital data Dd after storing the digital data Dd around the rising edge of the threshold level Th'of the analog input signal Sa, and converts the digital data Dd stored in the buffer 12a into the event detection circuit 16 ". Output.

The buffer control circuit 15 "is a buffer for storing the digital data Dd for detecting the transition time of the gentle rising slope, that is, the digital data Dd around the rising edge of the threshold level Th of the analog input signal Sa" in the buffer 12b. The period from the start to the end of the storage operation of 12 "is controlled based on the trigger signal T2'and the number of data provided by the control unit 13. In the present embodiment, the buffer control circuit 15" triggers. Upon receiving the signal T2', the buffer control circuit 15 "sets the write / read signal C1b to a high level so that the buffer 12b starts storing the digital data Dd. After that, the buffer control circuit 15" sets the control unit 13 ". After counting the number of data provided by the system clock, the write / read signal C1b is set to a low level. The buffer 12b ends the storage of the digital data Dd after storing the digital data Dd around the rising edge of the threshold level Th "of the analog input signal Sa", and transfers the digital data Dd stored in the buffer 12b to the event detection circuit 16 ". Output.

The buffer control circuit 15 ”measures the period from when the buffer 12a stops storing to when the buffer 12b starts storing using the system clock based on the write / read signal C1a and the write / read signal C1b. ..

The buffer control circuit 15 "is for storing the digital data Dd for detecting the transition time of the gentle falling slope, that is, the digital data Dd around the falling edge of the analog input signal Sa threshold level Th" in the buffer 12c. , The period from the start of the storage operation of the buffer 12c to the end of the storage operation is controlled based on the trigger signal T3'and the number of data provided by the control unit 13. In the present embodiment, when the buffer control circuit 15 "receives the trigger signal T3', the buffer control circuit 15" raises the write / read signal C1c so that the buffer 12c starts storing the digital data Dd. .. After that, the buffer control circuit 15 "counts the number of data provided by the control unit 13 with the system clock and then lowers the write / read signal C1c. The buffer 12c is the threshold level Th of the analog input signal Sa. After storing the digital data Dd around the falling edge, the storage of the digital data Dd is terminated, and the digital data Dd stored in the buffer 12c is output to the event detection circuit 16 ”.

The buffer control circuit 15 "is to store the digital data Dd for detecting the transition time of the gentle falling slope, that is, the digital data Dd around the falling edge of the threshold level Th'of the analog input signal Sa in the buffer 12d. , The period from the start to the end of the storage operation of the buffer 12d is controlled based on the trigger signal T4'and the number of data provided by the control unit 13. In the present embodiment, the buffer control circuit 15 "controls. Upon receiving the trigger signal T4', the buffer control circuit 15 "sets the write / read signal C1d to a high level so that the buffer 12d starts storing the digital data Dd. After that, the buffer control circuit 15" sets the control unit. After counting the number of data provided by 13 with the system clock, the write / read signal C1d is set to a low level. The buffer 12d ends the storage of the digital data Dd after storing the digital data Dd around the falling edge of the threshold level Th'of the analog input signal Sa, and uses the digital data Dd stored in the buffer 12d as the event detection circuit 16 ". Output to.

The buffer control circuit 15 ”measures the period from when the buffer 12c stops storing to when the buffer 12d starts storing using the system clock based on the write / read signal C1c and the write / read signal C1d. ..

Further, in the present embodiment, the buffer control circuit 15 "adjusts the period from the start of the storage operation of the buffers 12a, 12b, 12c, 12d to the end of the storage operation, in order to adjust the trigger signals T1', T2', T3. Consider various requirements in addition to the time when', T4'was generated. The various requirements are, for example, buffers 12a, 12b, 12c, 12d from the generation of trigger signals T1', T2', T3', T4'. Delay time until control, difference between generation timing of trigger signals T1', T2', T3', T4' and storage timing of digital data Dd in buffers 12a, 12b, 12c, 12d, write / read signal The period from the output of C1a, C1b, C1c, C1d to the stop of storage of the buffers 12a, 12b, 12c, 12d, the number of extra data required for the interpolation processing, etc. are included. Information on various requirements is provided. For example, it may be provided from the control unit 13 to the buffer control circuit 15 ”via the operation of the operation unit.

As shown in FIG. 10, the event detection circuit 16 "includes the event detection control circuit 16a", the interpolation processing circuit 16b ", the time detection processing circuit 16c", the level detection processing circuit 16d ", and the event determination circuit 16e". And have.

The event detection control circuit 16a "provides information about the interpolation magnification H to the interpolation processing circuit 16b", provides threshold levels Th', Th "to the time detection processing circuit 16c", and provides the rising transition time of the pulse to be detected. Information about Tr, the falling transition time Tf, and the maximum value Pm is provided to the event determination circuit 16e ”.

The buffer control circuit 15 ”is a measurement result Tm'of the period from when the buffer 12a stops the storage to when the buffer 12b starts the storage, and from when the buffer 12c stops the storage until the buffer 12d starts the storage. The period measurement result Tm "is provided to the time detection processing circuit 16c". Further, the buffer control circuit 15 "provides a level detection period signal during the period from when the buffer 12c stops storage to when the buffer 12d starts storage. C12 is output to the level detection processing circuit 16d ”.

In the interpolation processing circuit 16b ", digital data Dd for detecting an event is supplied from the buffers 12a, 12b, 12c, 12d, and the interpolation processing of the digital data Dd is performed at the interpolation magnification H to perform the interpolation processing of the digital data Dd, respectively. , Dh3, Dh4 are generated and supplied to the time detection processing circuit 16c ”. Further, the interpolation processing circuit 16b "outputs the time detection signals C11a, C11b, C11c, C11d corresponding to the provision periods of the respective interpolation data Dh1, Dh2, Dh3, Dh4 to the time detection processing circuit 16c".

In the time detection processing circuit 16c ", the positive slope start time when the interpolation data Dh1 is above the threshold level Th'and the positive slope end when the interpolation data Dh2 is above the threshold level Th" according to the time detection signals C11a and C11b. Detect and process the time. Further, the time detection processing circuit 16c "detects the normal slope start time, the normal slope stop time, and the rising transition time obtained by arithmetically processing the measurement result Tm'provided from the buffer control circuit 15". Similarly, in the time detection processing circuit 16c ", according to the time detection signals C11c and C11d, the negative slope start time at which the interpolation data Dh3 is below the threshold level Th" and the interpolation data Dh4 are below the threshold level Th'. Detects and processes the end time of the negative slope. Further, the time detection processing circuit 16c "detects the negative slope start time, the negative slope stop time, and the falling transition time obtained by arithmetically processing the measurement result Tm" provided by the buffer control circuit 15 ". "Supplies the detection processing result Dt" consisting of the rising transition time and the falling transition time to the event determination circuit 16e ". The time detection processing circuit 16c "can enable highly accurate time detection by using the interpolation data Dh1, Dh2, Dh3, Dh4 and the measurement results Tm', Tm".

The level detection processing circuit 16d "is input from the ADC 11 of the digital data Dd, detects and processes the detection processing result De" (digital data level) of the maximum value of the digital data Dd according to the level detection period signal C12, and is an event determination circuit. The event determination circuit 16e "is supplied to 16e" by using the digital data Dd input from the ADC 11 to digitalize the period from the end of the period stored in the buffer 12b to the start of the period stored in the buffer 12c. The maximum value L of the data Dd can be detected and processed.

The event determination circuit 16e "determines whether or not an event has been detected from the digital data Dd stored in the buffers 12a, 12b, 12c, 12d, the detection processing results Dt" and De ", and the rising edge of the pulse, which is an event detection condition. Judgment is made based on the transition time Tr, the falling transition time Tf, and the maximum value Pm. FIG. 11 is a diagram showing an example of a pulse event having a gentle slope detected by the event detection circuit. In the case of a pulse event, the period Sx from the end of the storage of the buffer 12a to the start of the storage of the buffer 12b, the period Sy from the end of the storage of the buffer 12b to the start of the storage of the buffer 12c, and the storage of the buffer 12c. A period Sz from the end to the start of storage of the buffer 12d is provided. In the event determination circuit 16e ", whether or not the period Tia at which the positive slope transitions corresponds to the rising transition time Tr and the period during which the negative slope transitions. It is determined whether or not Tib corresponds to the falling transition time Tf, and whether or not the maximum value L of the digital data Dd corresponds to the maximum value Pm.

According to the present embodiment, the buffer 12a and the buffer 12b store the digital data Dd around the start and end of the rising slope of the analog input signal Sa, and the buffer 12c and the buffer 12d store the falling slope of the analog input signal Sa. By storing the digital data Dd around the start and the end of the above, it is possible to detect the rising transition time and the falling transition time of a pulse event having a gentle slope with high accuracy without increasing the buffer capacity.

In the above embodiment, the case where one, two, or four buffers are used has been described, but three or five or more buffers may be used.

1,1', 1 "waveform recorder 11 Analog-to-digital converter (ADC)
12, 12', 12 ", 12a, 12b, 12c, 12d Buffer 13 Control unit 14, 14' Trigger circuit 15, 15', 15" Buffer control circuit 16, 16', 16 "Event detection circuit 16a, 16a" Event Detection control circuit 16b, 16b', 16b "Interpretation processing circuit 16c, 16c', 16c" Time detection processing circuit 16d, 16d', 16d "Level detection processing circuit 16e, 16e" Event judgment circuit 17 Capture processing circuit 18 Memory circuit 19 Waveform processing and display processing circuit 20 Display

Claims (6)

A buffer that temporarily stores digital data generated by analog-to-digital conversion of analog input signals,
A trigger circuit that generates a trigger signal from the analog input signal or the digital data based on the trigger condition,
A buffer control circuit that controls the period from the start to the end of the storage operation of the buffer based on the trigger signal, and
An event detection circuit that generates an event detection signal when an event is detected from the digital data stored in the buffer at the end of the period from the start to the end of the storage operation of the buffer.
A memory circuit that stores waveform data generated by capturing and processing the digital data and stops storage of the waveform data in response to the event detection signal.
Waveform recording device. The buffer has a first buffer and a second buffer.
The trigger circuit generates a first trigger signal and a second trigger signal from the analog input signal or the digital data based on the trigger condition.
The buffer control circuit controls the period from the start of the storage operation of the first buffer to the end of the storage operation based on the first trigger signal, and after the second buffer starts the storage operation. The period until the end is controlled based on the second trigger signal, and the period from the end of the storage operation of the first buffer to the start of the storage operation of the second buffer is measured.
In the event detection circuit, the digital data stored in the first buffer and the second buffer perform the storage operation at the end of the period from the start to the end of the storage operation of the first buffer. The waveform recording device according to claim 1, wherein an event detection signal is generated when an event is detected from the digital data stored in the second buffer at the end of the period from the start to the end. The buffer has a plurality of buffers and has a plurality of buffers.
The trigger circuit generates a plurality of trigger signals from the analog input signal or the digital data based on the trigger condition.
The buffer control circuit controls the period from the start of the storage operation to the end of the storage operation based on the trigger signal, and a predetermined buffer among the plurality of buffers ends the storage operation. Measure one or more of the period from to the next buffer to the start of storage operation,
The event detection circuit outputs an event detection signal when an event is detected from the digital data stored in the plurality of buffers at the end of the period from the start to the end of the storage operation of the plurality of buffers. The waveform recording device according to claim 1, which is generated. The waveform according to any one of claims 1 to 3, wherein the event detection circuit detects an event related to at least one of the level of the digital data and the period during which the digital data of a predetermined level is detected. Recording device. One of claims 1 to 4, wherein the memory circuit adjusts the timing at which the storage of the waveform data is stopped based on the time difference between the timing at which the trigger signal is generated and the timing at which the event detection signal is generated. The waveform recording device according to item 1. The waveform recording device according to any one of claims 1 to 5, which desimates digital data temporarily stored in the buffer.

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