JP2007101293A - Signal measuring apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To measure the rise time of a pulse without using a digitizer. <P>SOLUTION: A high-frequency signal is converted into a low-frequency signal through equivalent sampling by a sampling head 14. A first comparator 18L outputs a first signal when the low-frequency signal exceeds a first threshold (VOL). A second comparator 18H outputs a second signal when the low-frequency signal exceeds a second threshold (VOH), which is larger than the first threshold (VOL). The first signal and the second signal are input to an EXOR gate 22. An AND gate 26 outputs the logical sum of the output of the EXOR gate 22 and a clock signal. Counting the output of the AND gate 26 allows the rise time of the high-frequency signal to be measured. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to measurement of Tr / Tf (rise time / fall time) of a pulse.

  2. Description of the Related Art Conventionally, a tester is known that converts a high-frequency pulse signal into a low-frequency pulse signal using a sampling head and then captures the pulse signal into a digitizer to measure the pulse (see, for example, Patent Document 1).

JP 2002-156389 A

  However, when trying to measure the Tr / Tf (rise time / fall time) of a pulse using such a tester, a signal obtained by digitizing a low-frequency pulse signal is transferred to the memory in the digitizer. It takes a long time to process Tr / Tf by processing the digitized signal by the CPU. In addition, the digitizer is expensive, and a large space for installing the digitizer in the tester is required.

  As described above, measurement of Tr / Tf of a pulse using a digitizer has problems in terms of time, cost, and space.

  Accordingly, an object of the present invention is to measure the pulse rise time Tr or the pulse fall time Tf without using a digitizer.

  The signal measuring device according to the present invention includes a first signal output means for outputting a first signal when the input signal exceeds a first threshold, and a second signal when the input signal exceeds a second threshold greater than the first threshold. The second signal output means for outputting the first signal and the time measurement means for measuring the time from when the first signal is detected until the second signal is detected.

  According to the signal measuring apparatus configured as described above, the first signal output means outputs the first signal when the input signal exceeds the first threshold. The second signal output means outputs a second signal when the input signal exceeds a second threshold value that is greater than the first threshold value. The time measuring means measures a time from when the first signal is detected to when the second signal is detected.

  The signal measuring device according to the present invention includes a first signal output means for outputting a first signal when the input signal exceeds a first threshold, and a second signal when the input signal exceeds a second threshold greater than the first threshold. A second signal output means for outputting a signal, and a time measuring means for measuring a time from when the first signal is no longer detected to when the first signal is no longer detected. It is comprised so that it may comprise.

  According to the signal measuring apparatus configured as described above, the first signal output means outputs the first signal when the input signal exceeds the first threshold. The second signal output means outputs a second signal when the input signal exceeds a second threshold value that is greater than the first threshold value. The time measuring means measures a time from when the second signal is not detected in a state where the first signal is detected to when the first signal is not detected.

  Further, in the signal measuring apparatus according to the present invention, the time measuring means includes an exclusive OR (EXOR) gate having the first signal and the second signal as inputs, an output of the exclusive OR gate and a clock. You may make it have a logical sum (AND) gate which inputs a signal, and a counter which counts the output of the logical sum gate.

  The signal measuring apparatus according to the present invention further includes equivalent sampling means for equivalently sampling a high frequency signal and outputting a low frequency signal, wherein the low frequency signal is the input signal, and the sampling clock for the equivalent sampling is the clock. It may be a signal.

  The signal measuring apparatus according to the present invention may further include a determination unit that receives the first signal and the second signal and determines whether or not the input signal has normally risen or fallen.

  The signal measuring apparatus according to the present invention further comprises recording means for recording the measurement result of the time measuring means, and the recording means for recording the measurement result is determined based on the determination result of the determination means. It may be.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a diagram showing a configuration of a signal measuring apparatus 1 according to an embodiment of the present invention. The signal measuring apparatus 1 includes a clock signal source 10, a pulser 12, a sampling head (equivalent sampling means) 14, an operational amplifier 16, a first comparator (first signal output means) 18L, a second comparator (second signal output means) 18H, A time measuring means 20, a CPU (determination means) 32, and a register (recording means) 34 are provided. The signal measuring device 1 receives a high-frequency signal (for example, the cycle is 100 ns), and measures Tr / Tf (rise time / fall time).

  The clock signal source 10 outputs a clock signal. The period of the clock signal is slightly larger than the period of the high frequency signal. The period of the clock signal is, for example, 100.01 ns.

  The pulser 12 receives the clock signal, converts it into a pulse signal, and gives it to the sampling head 14.

  The sampling head 14 performs equivalent sampling of the high frequency signal and outputs a low frequency signal. FIG. 2 is an explanatory diagram of the operation of the sampling head 14. FIG. 2A is a diagram illustrating a waveform of a high-frequency signal. It is assumed that the period of the high frequency signal is 100 ns. FIG. 2B is a diagram illustrating a waveform of a pulse signal output from the pulser 12. A pulse signal is output in synchronization with the clock signal (period is 100.01 ns) shown in FIG. The sampling head 14 measures the level of the high-frequency signal at the time point p, q, r, s when receiving the pulse signal, and outputs it as shown in FIG. Here, it can be said that the sampling clock for equivalent sampling is a clock signal (see FIG. 2C). Further, as shown in FIG. 2D, it can be said that the output of the sampling head 14 is a low frequency signal having a frequency lower than that of the high frequency signal.

  Here, the measured value at time point q is the level of the signal at the time when 0.01 ns (= 100.01-100) has elapsed from time point p (t = 0), and the measured value at time point r is the time point p (t = 0) Therefore, it can be said that the measured value at the time point s is the signal level at the time point 0.03 ns after the time point p (t = 0). In this way, the level of the high frequency signal can be measured by sampling based on the clock signal having a period longer than that of the high frequency signal. This is equivalent sampling.

  The operational amplifier 16 receives the low frequency signal from the sampling head 14 at the positive input terminal (+), and subtracts the voltage of the signal received at the negative input terminal (−) from the voltage of the signal received at the positive input terminal (+). Amplified or attenuated and output. Since the output is connected to the negative input terminal (−), the operational amplifier 16 constitutes a voltage follower, and the voltage of the low frequency signal is applied to the operational amplifier 16 and the subsequent circuits.

  The first comparator (first signal output means) 18L receives the low frequency signal via the operational amplifier 16, and the voltage of the low frequency signal (input signal input to the first comparator 18L) exceeds the first threshold value (VOL). And the first signal (A) is output. The second comparator (second signal output means) 18H receives the low frequency signal via the operational amplifier 16, and the voltage of the low frequency signal (input signal input to the second comparator 18H) exceeds the second threshold (VOH). And the second signal (B) is output. Note that the second threshold value (VOH) is larger than the first threshold value (VOL).

  FIG. 3 is a diagram for explaining an example of the first threshold and the second threshold. FIG. 3 shows the waveform of the high frequency signal for one period. Here, the value of 10% of the height from the lowest level of the high-frequency signal is the first threshold value (VOL). A value at which the height from the lowest level of the high-frequency signal is 90% is the second threshold (VOH).

  The time measuring means 20 measures the time (rising time Tr) from when the first signal (A) is detected until the second signal (B) is detected. Furthermore, the time measuring means 20 is a time (falling) from when the second signal (B) is not detected while the first signal (A) is detected until the first signal (A) is not detected. Measure time Tf).

  The time measuring means 20 includes an exclusive OR (EXOR) gate 22, an amplifier 24, an OR (AND) gate 26 and a counter 28.

  FIG. 4 is a diagram showing the relationship between the input and output of the exclusive OR (EXOR) gate 22. The exclusive OR (EXOR) gate 22 receives the first signal (A) and the second signal (B). Then, when the first signal (A) and the second signal (B) are 0, and when it is 1, the output of the exclusive OR (EXOR) gate 22 is 0. When the first signal (A) is 1 and the second signal (B) is 0, the output of the exclusive OR (EXOR) gate 22 is 1. When the first signal (A) is 0, the high-frequency signal is not more than VOL and does not exceed VOH, so the second signal (B) is not 1.

  The amplifier 24 receives the clock signal from the clock signal source 10, amplifies it, and gives it to the logical sum (AND) gate 26.

  The logical sum (AND) gate 26 receives the output of the exclusive logical sum (EXOR) gate 22 and a clock signal (provided via the amplifier 24) as inputs. Then, the logical sum (AND) gate 26 outputs a signal when the output of the exclusive logical sum (EXOR) gate 22 and the clock signal are both high.

  The counter 28 counts the output of the logical sum (AND) gate 26. The count (counting) result of the counter 28 is recorded in the register (recording means) 34.

  The CPU (determination means) 32 receives the first signal (A) and the second signal (B), and the input signal (low frequency signal input to the first comparator 18L and the second comparator 18H) normally rises or rises. It is determined whether or not the vehicle has been descended. This determination result indicates whether or not the high-frequency signal has normally risen or fallen.

  FIG. 5 shows the waveform of the high frequency signal when the input signal rises or falls normally (FIG. 5A), the output of the exclusive OR (EXOR) gate 22 (FIG. 5B), the first signal ( The values of A) and the second signal (B) (FIG. 5C) are shown.

  Referring to FIG. 5A, (1) when the input signal rises normally, the output of the exclusive OR (EXOR) gate 22 changes from 0 → 1 → 0, and the first signal (A) The value of the second signal (B) changes from (0,0) → (1,0) → (1,1). When the values of the first signal (A) and the second signal (B) change from (0,0) → (1,0) → (1,1), the CPU 32 (1) the input signal rises normally. It is determined that

  Referring to FIG. 5A, (2) when the input signal falls normally, the output of the exclusive OR (EXOR) gate 22 changes from 0 → 1 → 0, and the first signal (A ) And the value of the second signal (B) change from (1,1) → (1,0) → (0,0). When the values of the first signal (A) and the second signal (B) change from (1,1) → (1,0) → (0,0), the CPU 32 (2) the input signal rises normally. Judged to have fallen.

  FIG. 6 shows the waveform of the high-frequency signal when the input signal does not normally rise or fall (FIG. 6A), the output of the exclusive OR (EXOR) gate 22 (FIG. 6B), and the first signal. The values (A) and the second signal (B) are shown (FIG. 6 (c)).

  Referring to FIG. 6A, (3) when the input signal does not rise normally (the signal level exceeds VOL, does not exceed VOH, and becomes less than VOL), an exclusive OR ( EXOR) The output of the gate 22 changes from 0 → 1 → 0, and the values of the first signal (A) and the second signal (B) are (0,0) → (1,0) → (0,0) And change. When the values of the first signal (A) and the second signal (B) change from (0,0) → (1,0) → (0,0), the CPU 32 (3) the input signal rises normally. Judged not to exist.

  Referring to FIG. 6A, (4) when the input signal does not fall normally (after the signal level becomes less than VOH, it does not become less than VOL and exceeds VOH), an exclusive OR (EXOR) The output of the gate 22 changes from 0 → 1 → 0, and the values of the first signal (A) and the second signal (B) are (1,1) → (1,0) → (1,1 ) And change. When the values of the first signal (A) and the second signal (B) change from (1,1) → (1,0) → (1,1), the CPU 32 (4) the input signal rises normally. Judge that it does not fall.

  The register (recording unit) 34 records the measurement result of the time measuring unit 20. The register (recording means) 34 includes a Tr register 34a, a Tf register 34b, a Tr-Error register 34c, and a Tf-Error register 34d.

  When the CPU 32 determines that the output of the counter 28 of the time measuring means 20 is (1) that the input signal has risen normally, it is determined that (2) the input signal has fallen normally in the Tr register 34a. If it is determined that the input signal does not rise normally in the Tf register 34b, (4) if it is determined that the input signal does not fall normally in the Tr-Error register 34c, Record in the Tf-Error register 34d.

  Next, the operation of the embodiment of the present invention will be described.

  FIG. 7 is a time chart when the input signal rises normally. 7A shows the output waveform of the sampling head 14, FIG. 7B shows the waveform of the clock signal, FIG. 7C shows the waveform of the first signal output from the first comparator 18L, and FIG. The waveform of the second signal output from the two comparators 18H, FIG. 7E is an output waveform of the exclusive OR (EXOR) gate 22, and FIG. 7F is an explanatory diagram of the output of the counter 28.

  The rise time Tr of the high frequency signal is the time from when the high frequency signal exceeds VOL until it exceeds VOH. As described with reference to FIG. 2, this corresponds to the passage of 0.01 ns in the high-frequency signal for each clock signal. Therefore, referring to FIG. 7A, the rise time Tr is 0.01 ns × 3 = 0.03 ns.

  The sampling head 14 receives the high frequency signal, performs equivalent sampling in synchronization with the clock signal (see FIG. 7B), and outputs a low frequency signal (see FIG. 7A). The low frequency signal (input signal) is given to the first comparator 18L and the second comparator 18H via the operational amplifier 16.

  When the level of the low frequency signal is less than VOL, neither the first signal (see FIG. 7C) nor the second signal (see FIG. 7D) is output. That is, both the output of the first comparator 18L and the output of the second comparator 18H are low. Therefore, the output of the exclusive OR (EXOR) gate 22 is also Low (see FIG. 7E).

  However, when the level of the low frequency signal exceeds VOL, the first signal (see FIG. 7C) is output. That is, the output of the first comparator 18L becomes High. Since the second signal (see FIG. 7D) is not yet output, the output of the exclusive OR (EXOR) gate 22 becomes High. However, since the processing of the exclusive OR (EXOR) gate 22 is slow, it is confirmed that the output of the first comparator 18L becomes High slightly later than the moment when the output of the first comparator 18L becomes High. Then, the output of the exclusive OR (EXOR) gate 22 becomes High (see FIG. 7E).

  When the level of the low frequency signal eventually exceeds VOH, the second signal (see FIG. 7D) is also output. That is, the output of the second comparator 18H also becomes High. Therefore, the output of the exclusive OR (EXOR) gate 22 becomes Low. However, since the processing of the exclusive OR (EXOR) gate 22 is slow, the output of the second comparator 18H becomes high slightly later than the moment when the output of the second comparator 18H becomes high. Then, the output of the exclusive OR (EXOR) gate 22 becomes Low (see FIG. 7E).

  The logical sum (AND) gate 26 takes the logical sum of the output of the exclusive logical sum (EXOR) gate 22 and the clock signal (provided via the amplifier 24) and outputs the result (see FIG. 7F). The counter 28 counts the output of the logical sum (AND) gate 26. In the example of FIG. 7F, the result of counting is three (clock signals). The counting result can be said to be a measurement of the time from when the first signal is detected by the exclusive OR (EXOR) gate 22 to when the second signal is detected by the exclusive OR (EXOR) gate 22. . As described with reference to FIG. 2, this corresponds to the passage of 0.01 ns in the high-frequency signal for each clock signal, and therefore, from the detection of the first signal to the detection of the second signal. It can be seen that the time is 0.01 ns × 3 = 0.03 ns. This coincides with the rise time Tr = 0.03 ns of the high frequency signal. That is, the counter 28 of the time measuring means 20 measures the rise time Tr of the high-frequency signal by measuring the time from when the first signal is detected until the second signal is detected.

  Since the values of the first signal (A) and the second signal (B) have changed from (0,0) → (1,0) → (1,1), the CPU 32 (1) input signal is normal It is determined that it has stood up. Therefore, the count results by the counter 28 (three (clock signals)) are recorded in the Tr register 34a.

  Note that the waveforms in FIGS. 7B to 7E are the same even when (3) the input signal does not rise normally (the signal level exceeds VOL, does not exceed VOH, and becomes less than VOL). It is. However, since the values of the first signal (A) and the second signal (B) change from (0,0) → (1,0) → (0,0), the CPU 32 (3) the input signal is normal. It is determined that it did not stand up. Therefore, the result of counting by the counter 28 (three (clock signals)) is recorded in the Tr-Error register 34c.

  FIG. 8 is a time chart when the input signal falls normally. 8A shows the output waveform of the sampling head 14, FIG. 8B shows the waveform of the clock signal, FIG. 8C shows the waveform of the first signal output from the first comparator 18L, and FIG. The waveform of the second signal output from the two comparators 18H, FIG. 8 (e) is an output waveform of the exclusive OR (EXOR) gate 22, and FIG. 8 (f) is an explanatory diagram of the output of the counter 28.

  The falling time Tf of the high frequency signal is the time from when the high frequency signal becomes less than VOH until it becomes less than VOL. As described with reference to FIG. 2, this corresponds to the passage of 0.01 ns in the high-frequency signal for each clock signal. Therefore, referring to FIG. 8A, the rise time Tf is 0.01 ns × 3 = 0.03 ns.

  The sampling head 14 receives the high frequency signal, performs equivalent sampling in synchronization with the clock signal (see FIG. 8B), and outputs a low frequency signal (see FIG. 8A). The low frequency signal (input signal) is given to the first comparator 18L and the second comparator 18H via the operational amplifier 16.

  When the level of the low-frequency signal exceeds VOH, both the first signal (see FIG. 8C) and the second signal (see FIG. 8D) are output. That is, both the output of the first comparator 18L and the output of the second comparator 18H are high. Therefore, the output of the exclusive OR (EXOR) gate 22 is Low (see FIG. 8E).

  However, when the level of the low frequency signal becomes less than VOH, the second signal (see FIG. 8D) is not output. That is, the output of the second comparator 18H becomes Low. Since the first signal (see FIG. 8C) is still output, the output of the exclusive OR (EXOR) gate 22 becomes High. However, since the processing of the exclusive OR (EXOR) gate 22 is slow, the output of the second comparator 18H becomes low slightly later than the moment when the output of the second comparator 18H becomes low. Detection (no second signal is detected), and the output of the exclusive OR (EXOR) gate 22 becomes High (see FIG. 8E).

  Eventually, when the level of the low frequency signal becomes less than VOL, the first signal (see FIG. 8C) is not output. That is, the output of the first comparator 18L is also low. Therefore, the output of the exclusive OR (EXOR) gate 22 becomes Low. However, since the processing of the exclusive OR (EXOR) gate 22 is slow, it is confirmed that the output of the first comparator 18L becomes low slightly after the moment when the output of the first comparator 18L becomes low. Detection is performed (the first signal is not detected), and the output of the exclusive OR (EXOR) gate 22 becomes Low (see FIG. 8E).

  The logical sum (AND) gate 26 takes the logical sum of the output of the exclusive logical sum (EXOR) gate 22 and the clock signal (given through the amplifier 24) and outputs the result (see FIG. 8F). The counter 28 counts the output of the logical sum (AND) gate 26. In the example of FIG. 8F, the count result is three (clock signals). As a result of counting, the first signal is exclusive after the second signal is not detected by the exclusive OR (EXOR) gate 22 while the first signal is detected by the exclusive OR (EXOR) gate 22. It can be said that the time until no longer being detected by the logical OR (EXOR) gate 22 is measured. As described with reference to FIG. 2, this corresponds to the passage of 0.01 ns in the high-frequency signal for each clock signal, so that the second signal is not detected while the first signal is detected. From this, it can be seen that the time until the first signal is not detected is 0.01 ns × 3 = 0.03 ns. This coincides with the falling time Tf = 0.03 ns of the high frequency signal. That is, the counter 28 of the time measuring means 20 measures the time of the high-frequency signal by measuring the time from when the second signal is not detected until the first signal is not detected in the state where the first signal is detected. The fall time Tf is measured.

  Since the values of the first signal (A) and the second signal (B) have changed from (1,1) → (1,0) → (0,0), the CPU 32 determines that (2) the input signal is normal. It is determined that it has fallen. Therefore, the result of counting by the counter 28 (three (clock signals)) is recorded in the Tf register 34b.

  (4) Even when the input signal does not fall normally (the signal level becomes less than VOH and then does not become less than VOL and exceeds VOH), the waveforms shown in FIGS. It is the same. However, since the values of the first signal (A) and the second signal (B) change from (1,1) → (1,0) → (1,1), the CPU 32 (4) input signal is normal. It is determined that it did not fall. Therefore, the result of counting by the counter 28 (three (clock signals)) is recorded in the Tf-Error register 34d.

  According to the embodiment of the present invention, the Tr / Tf (rise time of the pulse) can be obtained by using the low-cost and low-speed first comparator 18L, the second comparator 18H, and the time measuring means 20 without using a digitizer. / Fall time) can be measured.

It is a figure which shows the structure of the signal measurement apparatus 1 concerning embodiment of this invention. FIG. 6 is an explanatory diagram of the operation of the sampling head 14. It is a figure for demonstrating an example of a 1st threshold value and a 2nd threshold value. FIG. 3 is a diagram illustrating a relationship between an input and an output of an exclusive OR (EXOR) gate 22; The waveform of the high frequency signal when the input signal rises or falls normally (FIG. 5 (a)), the output of the exclusive OR (EXOR) gate 22 (FIG. 5 (b)), the first signal (A) and It is a figure which shows the value (FIG.5 (c)) of a 2nd signal (B). The waveform of the high frequency signal when the input signal does not rise normally or does not fall (FIG. 6 (a)), the output of the exclusive OR (EXOR) gate 22 (FIG. 6 (b)), the first signal (A) It is a figure which shows the value (FIG.6 (c)) of 2nd signal (B). It is a time chart when an input signal rises normally. It is a time chart when an input signal falls normally.

Explanation of symbols

A 1st signal B 2nd signal
VOL First threshold
VOH Second threshold 1 Signal measuring device 10 Clock signal source 12 Pulser 14 Sampling head (equivalent sampling means)
16 operational amplifier 18L first comparator (first signal output means)
18H Second comparator (second signal output means)
20 Time measuring means 22 Exclusive OR (EXOR) gate 24 Amplifier 26 OR (AND) gate 28 Counter 32 CPU (determination means)
34 registers (recording means)
34a Tr register 34b Tf register 34c Tr-Error register 34d Tf-Error register

Claims (6)

First signal output means for outputting the first signal when the input signal exceeds the first threshold;
Second signal output means for outputting a second signal when an input signal exceeds a second threshold value greater than the first threshold value;
Time measuring means for measuring the time from when the first signal is detected to when the second signal is detected;
A signal measuring device. First signal output means for outputting the first signal when the input signal exceeds the first threshold;
Second signal output means for outputting a second signal when an input signal exceeds a second threshold value greater than the first threshold value;
Time measuring means for measuring the time from when the second signal is no longer detected while the first signal is detected until the first signal is no longer detected;
A signal measuring device. The signal measuring device according to claim 1 or 2,
The time measuring means includes
An exclusive OR (EXOR) gate having the first signal and the second signal as inputs, and
A logical sum (AND) gate that receives the output of the exclusive OR gate and a clock signal; and
A counter that counts the output of the OR gate;
A signal measuring device. The signal measuring device according to claim 3,
Equivalent sampling means for equivalently sampling high frequency signals and outputting low frequency signals,
The low frequency signal is the input signal;
The sampling clock for the equivalent sampling is the clock signal.
Signal measuring device. The signal measuring device according to claim 1 or 2,
A signal measuring apparatus comprising: a determination unit that receives the first signal and the second signal and determines whether the input signal has normally risen or fallen. The signal measuring device according to claim 5,
Recording means for recording the measurement result of the time measuring means,
Based on the determination result of the determination means, the recording means for recording the measurement result is determined.
Signal measuring device.

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