JP3395462B2 - Synchronous signal recognition system - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronizing signal recognition system included in a control circuit of a display device for a computer, and in particular, whether or not a horizontal synchronizing signal or a vertical synchronizing signal having a predetermined specification is inputted. And a circuit system that recognizes whether the synchronizing signal is positive logic or negative logic.

[0002]

2. Description of the Related Art In a display device for a computer, a circuit for recognizing whether a correct horizontal synchronizing signal and a vertical synchronizing signal are inputted from the computer and recognizing whether the synchronizing signal is positive logic or negative logic. There is. The synchronizing signal to be recognized by this circuit has a mark period t1 and a space period t2 that are predetermined, and therefore a repeating period (t1 + t2) (the mark period t1 is much smaller than the space period t2). Further, the sync signal may be either positive logic (mark is at high level) or negative logic (mark is at low level) (it is not known which signal is input).

(Conventional Circuit A) FIG. 7 and FIG. 8 show the configuration and operation waveform of a conventional horizontal synchronizing signal recognition circuit A. The horizontal synchronizing signal HD applied to the input terminal in is smoothed by the low-pass filter 1, and the smoothed signal A is binarized by the comparator 2 in comparison with the reference voltage Vref1. As described above, since the mark period t1 of the synchronizing signal HD is much smaller than the space period t2, the level of the smoothed signal A is always smaller than Vref1 when the synchronizing signal HD is positive logic, and therefore the output B of the comparator 2 is Is kept at a low level.
When the synchronizing signal HD has a negative logic, the level of the smoothing signal A is always higher than Vref1, so that the output B of the comparator 2 is kept at a high level.

By inputting the synchronizing signal HD of the terminal in and the output signal B of the comparator 2 to the exclusive OR gate 3,
A positive logic synchronizing signal appears at the output C of the gate 3 regardless of whether the synchronizing signal HD is positive logic or negative logic. The monostable multivibrator 4 supplies the synchronization signal C with a duty ratio of 50.
% Square wave signal D, the square wave signal D is smoothed by the low pass filter 5, and the smoothed signal E is binarized by the comparator 6 in comparison with the reference voltage Vref2. Regardless of positive logic or negative logic, if the synchronizing signal HD is input to the terminal in, the square wave signal D having the same cycle as the signal HD is generated from the multivibrator 4, and the smoothed signal E is Vref2.
It will always be higher and therefore the output HDEX of the comparator 6 will be high. That is, the output signal HDEX
Indicates that the synchronizing signal HD is input when the signal is high level, and that the synchronizing signal HD is not input when the signal HDEX is low level. When the synchronizing signal HD is input, it is possible to know whether the synchronizing signal HD is a positive logic or a negative logic by looking at the output B of the comparator 2 as described above.

(Conventional Circuit B) FIG. 9 and FIG. 10 show the structure and operation waveforms of a conventional vertical synchronizing signal recognition circuit B. The vertical synchronizing signal VD applied to the input terminal in is smoothed by the low pass filter 7, and the smoothed signal F is compared with the reference voltage Vref3 by the comparator 8 and binarized. Output G of comparator 8 if positive logic
Is a high level, and if it is a negative logic, the output G is a low level. The configuration in which the synchronization signal VD at the terminal in and the output signal G from the comparator 8 are input to the exclusive OR gate 9 to obtain the synchronization signal H of positive logic is also the same as in FIG.

The output signal H of the gate 9 becomes a trigger signal of the sawtooth wave generator 10. That is, the rising edge of the signal H triggers the sawtooth wave generator 10, and its output I increases from the previous level toward the maximum level VH at a predetermined large rate of change,
When the maximum level VH is reached, it decreases at a predetermined small change rate. The sawtooth signal I is compared with Vref4 by the comparator 11 and binarized.

If a pulse train having a predetermined period (t1 + t2) is generated from the gate 9, the level of the sawtooth wave signal I is always V.
It is greater than ref4 and therefore the output VDEX of the comparator 11 is kept high. If the trigger input of sawtooth generator 10 is removed, its output I will be less than Vref4, thus keeping output VDEX low.
Looking at this output signal VDEX, the vertical sync signal V
It is possible to know whether or not D is input. When the synchronizing signal VD is input, it is possible to know whether the synchronizing signal VD is a positive logic or a negative logic by looking at the output G of the comparator 8.

[0008]

When the conventional circuit A of FIG. 7 is replaced with a digital circuit to form an IC, two up / down counters are required for digitizing the two low pass filters 1 and 5, Further, a counter is also required for digitizing the monostable multivibrator 4, which causes a problem that the circuit scale becomes large as a whole.

Considering that the conventional circuit B of FIG. 9 is configured as an analog IC circuit, in order to realize the low pass filter 7, the sawtooth wave generator 10, etc., the vertical synchronizing signal V
It is necessary to obtain a large time constant that sufficiently covers the period of D, and for that reason, a time constant element such as a capacitor or a resistor must be externally attached. Further, even when the conventional circuit B is replaced with a digital circuit to form an IC, an up-down counter having a large number of bits is required and the circuit scale becomes considerably large.

The present invention has been made in view of the above-mentioned conventional problems, and an object thereof is an IC having a small-scale and simple structure.
An object of the present invention is to provide a synchronization signal recognition system capable of realizing a target synchronization signal recognition function with a circuit that can be easily realized.

[0011]

[Means for Solving the Problems]

(First invention) The synchronization signal to be recognized is a signal whose positive logic or negative logic is indefinite, the mark period and the space period are predetermined and are not equal, and the repetition cycle is predetermined, In the circuit system, the input signal applied to the circuit system is monitored to recognize whether or not the synchronization signal is input, and if it is input, the synchronization signal is recognized as positive logic or negative logic. For the input signal, the accumulated time of either the high level period or the low level period within a fixed measurement time is measured, and if the accumulated time is within a predetermined time range, the synchronization is performed. It is determined that the signal is input, and if it is not within the predetermined time range, it is determined that the synchronization signal is not input, and it is within the predetermined time range. The synchronization signal by discriminating a binary magnitude of the accumulated time with a predetermined threshold in case it is determined whether the positive logic or negative logic.

(Second invention) Whether the synchronization signal to be recognized is positive logic or negative logic is uncertain, the mark period and the space period are predetermined, the mark period is shorter, and the repetition cycle is predetermined. The input signal applied to a predetermined circuit system is monitored to recognize whether or not the synchronization signal is input, and when input, the synchronization signal is positive logic or negative logic. A circuit system for recognizing whether the input signal is a rising edge or a falling edge, and a time counting operation is started each time an edge detection signal is generated from the means, and is longer than the mark period. A means for generating a timeout signal when a predetermined time shorter than the space period is reached, and a logic of the input signal when the timeout signal is generated Means for determining whether the synchronization signal is positive logic or negative logic, and means for determining that a signal different from the synchronization signal is input when a predetermined number or more of the edge detection signals occur within a fixed time With.

[0013]

DETAILED DESCRIPTION OF THE INVENTION

(First Invention) The structure and operating principle of a horizontal synchronizing signal recognition system according to the first invention are shown in FIGS. As described above, the horizontal synchronizing signal HD to be recognized by this system may be positive logic that makes the mark high level or negative logic that makes the mark low level. However, the mark period t1 and the space period t2 are determined in advance, and thus the repetition cycle (t1 + t2) is also determined. The mark period t1 is the space period t2.
Much smaller.

The horizontal synchronizing signal HD applied to the terminal in serves as an enable signal for the counter 12 (in this example, an up counter is used). In this embodiment, the accumulated time of the high level period of the input signal from the terminal in is measured based on the clock CLK. The measurement time Tp is controlled by the central processing unit (hereinafter referred to as “CPU”) 14. CPU14
Resets the counter 12 at a cycle twice as long as the cycle (t1 + t2) of the synchronization signal HD, and the reset cycle 2 (t1 +
A time slightly shorter than t2) is set as the measurement time Tp, and the cumulative time of the high level period of the input signal (horizontal synchronizing signal HD) within the measurement time Tp is repeatedly measured by the counter 12.

The measured value of the counter 12 is the comparator 13
Is input to the CPU, and a comparison is made to determine whether it falls within a predetermined time range or is out of the predetermined time range. The CPU 14 takes in the determination result by the comparator 13 immediately before resetting the counter 12. Further, the CPU 14 takes in the MSB of the measured value output of the counter 12 immediately before resetting the counter 12. This MSB signal uses the median value of the time range set in the comparator 13 as a threshold value and the counter 12
Corresponds to a signal obtained by binarizing the measured value of.

Since the measurement time controlled by the CPU 14 is about twice the cycle (t1 + t2) of the horizontal synchronizing signal HD, about two mark periods 2 × t1 and two space periods 2 × t2 within the measurement time. Is included. When a positive logic horizontal synchronization signal HD is input to the terminal in, the counter 12
Measures the cumulative time 2 × t1 of the mark period. On the other hand, when the negative logic horizontal synchronizing signal HD is input to the terminal in, the counter 12 measures the cumulative time 2 × t2 of the space period.

The lower limit value of the time range set in the comparator 13 is (2 × t1−Δ), and the upper limit value is (2 × t1−Δ).
t2 + Δ). Note that Δ is an appropriate minute value. Therefore, if the horizontal synchronizing signal HD is input to the terminal in, whether the logic is positive logic or negative logic, the cumulative time of the high level period measured by the counter 12 is set in the comparator 13. Within the time range. CPU14
Sees the output of the comparator 13
Recognize whether or not D is input. When the horizontal synchronizing signal HD is input, the MSB of the output of the counter 12 is checked to recognize whether the horizontal synchronizing signal HD has a positive logic or a negative logic. That is, if the MSB is "0", the logic is positive, and if the MSB is "1", the logic is negative.

The comparison operation performed by the comparator 13 can also be performed by the CPU 14. Further, the periodic resetting of the counter 12 performed by the CPU 14 can be performed by a dedicated circuit. Furthermore, it is also possible for the CPU 14 to perform the time counting operation of the counter 12. Of course, even if the counter 12 measures the accumulated time of the low level period of the input signal, the same is true.
It doesn't matter at all whether 2 is an up counter or a down counter.

(Second Invention) The structure and operation principle of a vertical synchronizing signal recognition system according to the second invention are shown in FIGS. The specifications of the vertical synchronization signal VD to be recognized are as described above. The edge detection circuit 18 outputs a pulse having a minute width in response to both the rising edge and the falling edge of the vertical synchronizing signal VD input to the terminal in. The error detection circuit 19 sets the clear signal of the timer 15 to "1" each time it receives an edge detection pulse from the edge detection circuit 18. As a result, each time an edge detection pulse is generated from the edge detection circuit 18, the timer 15 starts counting time from zero. The timer 15 is a retrigger type counter that counts the clock CLK.

The timer 15 outputs a time-out signal when a predetermined time Ts has elapsed after starting the time measurement, and the latch circuit 16 responds to the time-out signal, and the logical value of the input signal (vertical synchronizing signal VD) at that time. Is latched. The set time Ts of the timer 15 is longer than the mark period t1 of the vertical synchronizing signal VD and shorter than (t2-t1). Note that t2 is a space period. Therefore, if the timer 15 times out after a time Ts after being triggered by the end edge of the mark period and "0" = low level is latched in the latch circuit 16 at that time, the input vertical synchronizing signal VD is a positive logic. If "1" = high level is latched, it is understood that the vertical synchronizing signal VD has negative logic.
The central processing unit (hereinafter referred to as "CPU") 17 recognizes the positive logic / negative logic of the input signal VD by looking at the output of the latch circuit 16 in this way.

The error detection circuit 19 includes a counter that counts the number of edge detection pulses input from the edge detection circuit 18. The pulse counter is cleared by the time-out signal from the timer 15, and when the count value reaches a certain value (for example, 10), the VD presence / absence signal for the CPU 17 is inverted from "1" to "0". In other words, as shown in FIG. 5, when a predetermined number or more of the edge detection pulses are generated without generating the time-out signal of the timer 15, it is not the correct vertical synchronization signal VD, but a different period shorter than that. It is determined that the signal is noise or noise, and the signal with or without VD is set to "0". This is because the horizontal sync signal H
This is a measure for detecting that D is input (the horizontal synchronizing signal HD has a shorter period than the vertical synchronizing signal VD). It should be noted that this functional portion can be replaced with a configuration in which it is simply monitored whether or not a predetermined number or more of the edge detection pulses are detected within a certain period of time, and the same effect is obtained.

As shown in FIG. 6, the error detecting circuit 19 may be constructed so that the timer 15 always operates without preparing a complicated signal such as the above-mentioned clear signal.

In the embodiments of FIGS. 1 and 3, some or all of the circuit functions may be replaced with analog circuits, or some or all of the circuit functions may be performed by a microprocessor. You may carry out in.

[0024]

According to the synchronization signal recognition system of the new method of the present invention, the intended synchronization signal recognition function can be realized by a circuit which is small and has a simple structure and which can be easily integrated into an IC.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a horizontal synchronization signal recognition system according to an embodiment of the first invention.

FIG. 2 is a timing chart for explaining the operation of the system of FIG.

FIG. 3 is a configuration diagram of a vertical synchronization signal recognition system according to an embodiment of the second invention.

4 is a timing chart for explaining the operation of the system of FIG.

FIG. 5 is a time chart when an error processing function is added.

FIG. 6 is a time chart when another discrimination method is used.

FIG. 7 is a block diagram of a conventional horizontal sync signal recognition circuit.

8 is a timing chart for explaining the operation of the circuit of FIG.

FIG. 9 is a block diagram of a conventional vertical synchronization signal recognition circuit.

10 is a timing chart for explaining the operation of the circuit of FIG.

[Explanation of symbols]

HD ... Horizontal sync signal VD ... Vertical sync signal t1 ... Mark period t2: Space period in… input terminal CLK1, CLK2 ... Clock Tp ... Measurement time 15 ... Timer 16 ... Latch circuit 17 ... Central processing unit 18 ... Edge detection circuit 19 ... Error detection circuit

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G09G 5/00-5/42 H04N 5/04

Claims (2)

(57) [Claims] 1. A synchronization signal to be recognized is a signal whose positive logic or negative logic is indefinite, whose mark period and space period are predetermined and are not equal, and whose repetition period is predetermined, It is a circuit system that monitors an input signal applied to a circuit system to recognize whether or not the synchronization signal is input, and when it is input, recognizes whether the synchronization signal is positive logic or negative logic. Then, for the input signal, the cumulative time of either the high level period or the low level period within a fixed measurement time is measured, and if the cumulative time is within a predetermined time range, the synchronization signal If it is within the predetermined time range, it is determined that the sync signal is not input, and if it is within the predetermined time range. In the case where the sync signal is positive logic or negative logic, the magnitude of the cumulative time is binary-discriminated by a predetermined threshold value to determine whether the sync signal is positive logic or negative logic. 2. A synchronization signal to be recognized is a signal in which it is uncertain whether the logic is positive or negative, the mark period and space period are predetermined, the mark period is shorter, and the repetition cycle is predetermined. Yes, the input signal applied to a predetermined circuit system is monitored to recognize whether or not the synchronization signal is input, and when input, it is determined whether the synchronization signal is positive logic or negative logic. In the circuit system, means for detecting a rising edge and a falling edge of the input signal, and a time counting operation is started each time an edge detection signal is generated from the means, and is longer than the mark period and shorter than the space period. Means for generating a time-out signal when a predetermined time is reached, and the synchronization signal by checking the logic of the input signal when the time-out signal is generated Is provided with a positive logic or a negative logic, and a means for determining that a signal different from the synchronization signal is input when a predetermined number or more of the edge detection signals are generated within a certain period of time. A synchronization signal recognition system characterized in that